Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T35,T38,T20
1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T35,T38,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T38,T20
1	0	Covered	T35,T20,T63
1	1	Covered	T35,T38,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T38,T20
0	1	Covered	T35,T38,T20
1	0	Covered	T35,T20,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T63,T65,T66
0	1	Covered	T63,T65,T66
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T63,T65,T66
1	-	Covered	T63,T65,T66

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T38,T20
0	1	Covered	T35,T38,T20
0	0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T38,T20
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T35,T38,T20
IdleSt	0	-	-	-	-	-	-	Covered	T35,T38,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T38,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T264,T265
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T38,T20
DetectSt	-	-	-	-	1	-	-	Covered	T35,T38,T20
DetectSt	-	-	-	-	0	1	-	Covered	T63,T65,T66
DetectSt	-	-	-	-	0	0	-	Covered	T35,T38,T20
StableSt	-	-	-	-	-	-	1	Covered	T63,T65,T66
StableSt	-	-	-	-	-	-	0	Covered	T63,T65,T66
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	3098	0	0
CntIncr_A	5743868	106945	0	0
CntNoWrap_A	5743868	5089753	0	0
DetectStDropOut_A	5743868	404	0	0
DetectedOut_A	5743868	71950	0	0
DetectedPulseOut_A	5743868	846	0	0
DisabledIdleSt_A	5743868	4660868	0	0
DisabledNoDetection_A	5743868	4662959	0	0
EnterDebounceSt_A	5743868	1566	0	0
EnterDetectSt_A	5743868	1535	0	0
EnterStableSt_A	5743868	846	0	0
PulseIsPulse_A	5743868	846	0	0
StayInStableSt	5743868	71019	0	0
gen_high_event_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	761	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	3098	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	44	0	0
T35	6387	14	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	50	0	0
T63	0	40	0	0
T64	0	10	0	0
T65	0	48	0	0
T66	0	32	0	0
T73	447	0	0	0
T263	0	54	0	0
T266	0	26	0	0
T267	0	58	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	106945	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	2888	0	0
T35	6387	357	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	1178	0	0
T63	0	1740	0	0
T64	0	290	0	0
T65	0	1824	0	0
T66	0	480	0	0
T73	447	0	0	0
T263	0	1863	0	0
T266	0	559	0	0
T267	0	1798	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5089753	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5972	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4515	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	404	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	17	0	0
T35	6387	3	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	25	0	0
T53	0	1	0	0
T73	447	0	0	0
T111	0	17	0	0
T112	0	28	0	0
T114	0	11	0	0
T264	0	11	0	0
T281	0	15	0	0
T283	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	71950	0	0
T49	1274	0	0	0
T50	565	0	0	0
T63	10230	2266	0	0
T64	0	508	0	0
T65	25743	3025	0	0
T66	27711	1251	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	1555	0	0
T135	421	0	0	0
T173	429	0	0	0
T263	0	1759	0	0
T266	0	1618	0	0
T267	0	2347	0	0
T268	0	1128	0	0
T269	0	242	0	0
T286	502	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	846	0	0
T49	1274	0	0	0
T50	565	0	0	0
T63	10230	20	0	0
T64	0	5	0	0
T65	25743	24	0	0
T66	27711	16	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	13	0	0
T135	421	0	0	0
T173	429	0	0	0
T263	0	27	0	0
T266	0	13	0	0
T267	0	29	0	0
T268	0	17	0	0
T269	0	10	0	0
T286	502	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4660868	0	0
T15	25917	25455	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	3234	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	2014	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4662959	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	3234	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	2014	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1566	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	22	0	0
T35	6387	7	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	25	0	0
T63	0	20	0	0
T64	0	5	0	0
T65	0	24	0	0
T66	0	16	0	0
T73	447	0	0	0
T263	0	27	0	0
T266	0	13	0	0
T267	0	29	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	1535	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T18	1663	0	0	0
T19	33673	0	0	0
T20	33590	22	0	0
T35	6387	7	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	25	0	0
T63	0	20	0	0
T64	0	5	0	0
T65	0	24	0	0
T66	0	16	0	0
T73	447	0	0	0
T263	0	27	0	0
T266	0	13	0	0
T267	0	29	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	846	0	0
T49	1274	0	0	0
T50	565	0	0	0
T63	10230	20	0	0
T64	0	5	0	0
T65	25743	24	0	0
T66	27711	16	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	13	0	0
T135	421	0	0	0
T173	429	0	0	0
T263	0	27	0	0
T266	0	13	0	0
T267	0	29	0	0
T268	0	17	0	0
T269	0	10	0	0
T286	502	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	846	0	0
T49	1274	0	0	0
T50	565	0	0	0
T63	10230	20	0	0
T64	0	5	0	0
T65	25743	24	0	0
T66	27711	16	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	13	0	0
T135	421	0	0	0
T173	429	0	0	0
T263	0	27	0	0
T266	0	13	0	0
T267	0	29	0	0
T268	0	17	0	0
T269	0	10	0	0
T286	502	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	71019	0	0
T49	1274	0	0	0
T50	565	0	0	0
T63	10230	2246	0	0
T64	0	502	0	0
T65	25743	2993	0	0
T66	27711	1230	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	1542	0	0
T135	421	0	0	0
T173	429	0	0	0
T263	0	1732	0	0
T266	0	1604	0	0
T267	0	2316	0	0
T268	0	1110	0	0
T269	0	232	0	0
T286	502	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	761	0	0
T49	1274	0	0	0
T50	565	0	0	0
T63	10230	20	0	0
T64	0	4	0	0
T65	25743	16	0	0
T66	27711	11	0	0
T76	882	0	0	0
T77	11612	0	0	0
T110	0	13	0	0
T135	421	0	0	0
T173	429	0	0	0
T263	0	27	0	0
T266	0	12	0	0
T267	0	27	0	0
T268	0	16	0	0
T269	0	10	0	0
T286	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T35,T38
1	Covered	T48,T15,T32

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T35,T38
1	0	Covered	T48,T15,T32
1	1	Covered	T48,T15,T32

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T48,T15,T32	VC_COV_UNR
1	Covered	T15,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T48,T15,T32
1	Covered	T15,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T17,T19
1	0	Covered	T15,T35,T16
1	1	Covered	T15,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T17,T19
0	1	Covered	T15,T24,T69
1	0	Covered	T53,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T21
0	1	Covered	T17,T19,T21
1	0	Covered	T89,T287

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T19,T21
1	-	Covered	T17,T19,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T17,T19
0	1	Covered	T15,T17,T19
0	0	Excluded	T48,T15,T32	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T17,T19
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T17,T19
IdleSt	0	-	-	-	-	-	-	Covered	T48,T15,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T88
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T17,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T59,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T17,T19
DetectSt	-	-	-	-	1	-	-	Covered	T15,T24,T69
DetectSt	-	-	-	-	0	1	-	Covered	T17,T19,T21
DetectSt	-	-	-	-	0	0	-	Covered	T15,T17,T19
StableSt	-	-	-	-	-	-	1	Covered	T17,T19,T21
StableSt	-	-	-	-	-	-	0	Covered	T17,T19,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T48,T15,T32
0	Covered	T48,T15,T32

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5743868	735	0	0
CntIncr_A	5743868	38765	0	0
CntNoWrap_A	5743868	5092116	0	0
DetectStDropOut_A	5743868	66	0	0
DetectedOut_A	5743868	13532	0	0
DetectedPulseOut_A	5743868	280	0	0
DisabledIdleSt_A	5743868	4730953	0	0
DisabledNoDetection_A	5743868	4732603	0	0
EnterDebounceSt_A	5743868	386	0	0
EnterDetectSt_A	5743868	350	0	0
EnterStableSt_A	5743868	280	0	0
PulseIsPulse_A	5743868	280	0	0
StayInStableSt	5743868	13213	0	0
gen_high_level_sva.HighLevelEvent_A	5743868	5095117	0	0
gen_not_sticky_sva.StableStDropOut_A	5743868	236	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	735	0	0
T15	25917	21	0	0
T16	2477	0	0	0
T17	9820	2	0	0
T19	0	10	0	0
T21	0	2	0	0
T24	0	2	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	10	0	0
T59	0	1	0	0
T65	0	12	0	0
T66	0	10	0	0
T69	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	38765	0	0
T15	25917	1363	0	0
T16	2477	0	0	0
T17	9820	116	0	0
T19	0	615	0	0
T21	0	50	0	0
T24	0	43	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	835	0	0
T59	0	51	0	0
T65	0	492	0	0
T66	0	295	0	0
T69	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5092116	0	0
T15	25917	25434	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	66	0	0
T15	25917	9	0	0
T16	2477	0	0	0
T17	9820	0	0	0
T24	0	1	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T69	0	1	0	0
T91	0	5	0	0
T118	0	2	0	0
T284	0	3	0	0
T285	0	3	0	0
T288	0	1	0	0
T289	0	6	0	0
T290	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	13532	0	0
T17	9820	17	0	0
T18	1663	0	0	0
T19	33673	310	0	0
T20	33590	0	0	0
T21	7670	48	0	0
T51	0	24	0	0
T63	10230	0	0	0
T64	0	47	0	0
T65	0	433	0	0
T66	0	237	0	0
T71	0	189	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T266	0	634	0	0
T267	0	270	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	280	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	5	0	0
T20	33590	0	0	0
T21	7670	1	0	0
T51	0	5	0	0
T63	10230	0	0	0
T64	0	1	0	0
T65	0	6	0	0
T66	0	5	0	0
T71	0	4	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T266	0	7	0	0
T267	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4730953	0	0
T15	25917	20145	0	0
T16	2477	214	0	0
T32	463	62	0	0
T33	437	36	0	0
T34	504	103	0	0
T35	6387	5986	0	0
T36	1404	202	0	0
T37	421	20	0	0
T38	4966	4565	0	0
T48	8403	2	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	4732603	0	0
T15	25917	20145	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	386	0	0
T15	25917	12	0	0
T16	2477	0	0	0
T17	9820	1	0	0
T19	0	5	0	0
T21	0	1	0	0
T24	0	1	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	5	0	0
T59	0	1	0	0
T65	0	6	0	0
T66	0	5	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	350	0	0
T15	25917	9	0	0
T16	2477	0	0	0
T17	9820	1	0	0
T19	0	5	0	0
T21	0	1	0	0
T24	0	1	0	0
T32	463	0	0	0
T33	437	0	0	0
T34	504	0	0	0
T35	6387	0	0	0
T36	1404	0	0	0
T37	421	0	0	0
T38	4966	0	0	0
T51	0	5	0	0
T65	0	6	0	0
T66	0	5	0	0
T69	0	1	0	0
T266	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	280	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	5	0	0
T20	33590	0	0	0
T21	7670	1	0	0
T51	0	5	0	0
T63	10230	0	0	0
T64	0	1	0	0
T65	0	6	0	0
T66	0	5	0	0
T71	0	4	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T266	0	7	0	0
T267	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	280	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	5	0	0
T20	33590	0	0	0
T21	7670	1	0	0
T51	0	5	0	0
T63	10230	0	0	0
T64	0	1	0	0
T65	0	6	0	0
T66	0	5	0	0
T71	0	4	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T266	0	7	0	0
T267	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	13213	0	0
T17	9820	16	0	0
T18	1663	0	0	0
T19	33673	305	0	0
T20	33590	0	0	0
T21	7670	47	0	0
T51	0	19	0	0
T63	10230	0	0	0
T64	0	46	0	0
T65	0	421	0	0
T66	0	227	0	0
T71	0	185	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T266	0	627	0	0
T267	0	267	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	5095117	0	0
T15	25917	25465	0	0
T16	2477	219	0	0
T32	463	63	0	0
T33	437	37	0	0
T34	504	104	0	0
T35	6387	5987	0	0
T36	1404	204	0	0
T37	421	21	0	0
T38	4966	4566	0	0
T48	8403	3	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5743868	236	0	0
T17	9820	1	0	0
T18	1663	0	0	0
T19	33673	5	0	0
T20	33590	0	0	0
T21	7670	1	0	0
T51	0	5	0	0
T63	10230	0	0	0
T64	0	1	0	0
T71	0	4	0	0
T73	447	0	0	0
T74	498	0	0	0
T75	408	0	0	0
T76	882	0	0	0
T83	0	5	0	0
T263	0	1	0	0
T266	0	7	0	0
T267	0	3	0	0