Module Definition
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Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.65 100.00 86.61 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_combo_intr_status_cdc 96.43 100.00 85.71 100.00 100.00
tb.dut.u_reg.u_key_intr_status_cdc 96.43 100.00 85.71 100.00 100.00
tb.dut.u_reg.u_ulp_status_cdc 96.88 100.00 87.50 100.00 100.00
tb.dut.u_reg.u_wkup_status_cdc 96.88 100.00 87.50 100.00 100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_key_invert_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_pin_out_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_pin_out_value_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_key_intr_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc 97.73 100.00 90.91 100.00 100.00
tb.dut.u_reg.u_ulp_ctl_cdc 98.08 100.00 92.31 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
97.73 90.91
tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_key_invert_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_pin_out_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_pin_out_value_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_key_intr_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORECOND
97.73 90.91
tb.dut.u_reg.u_com_out_ctl_3_cdc

SCORECOND
96.43 85.71
tb.dut.u_reg.u_combo_intr_status_cdc

SCORECOND
96.43 85.71
tb.dut.u_reg.u_key_intr_status_cdc

TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T7,T8
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT15,T16,T17
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T7,T8
10Not Covered
11CoveredT15,T16,T17

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
SCORECOND
98.08 92.31
tb.dut.u_reg.u_ulp_ctl_cdc

SCORECOND
96.88 87.50
tb.dut.u_reg.u_ulp_status_cdc

SCORECOND
96.88 87.50
tb.dut.u_reg.u_wkup_status_cdc

TotalCoveredPercent
Conditions161487.50
Logical161487.50
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT6,T7,T8
01Unreachable
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---
-1--2-StatusTests
0-CoveredT1,T2,T3
1-CoveredT1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT15,T16,T17
10CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT6,T7,T8
10Not Covered
11CoveredT15,T16,T17

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T7,T8


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T6,T7,T8


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 2147483647 98953778 0 0
DstReqKnown_A 221378178 190618413 0 0
SrcAckBusyChk_A 2147483647 111721 0 0
SrcBusyKnown_A 2147483647 2147483647 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 98953778 0 0
T1 14296689 47624 0 0
T2 3844559 56635 0 0
T3 3967177 287109 0 0
T4 0 308764 0 0
T5 0 84529 0 0
T9 0 785908 0 0
T10 0 22837 0 0
T11 0 126223 0 0
T12 0 19906 0 0
T25 7213261 0 0 0
T26 6624554 0 0 0
T27 1888850 0 0 0
T28 1812704 0 0 0
T29 7538454 0 0 0
T30 7369105 0 0 0
T31 7363666 0 0 0
T67 0 803855 0 0
T68 0 1588 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 221378178 190618413 0 0
T1 29785 185 0 0
T6 14874 74 0 0
T7 14911 111 0 0
T8 14948 148 0 0
T25 14874 74 0 0
T26 14874 74 0 0
T27 15096 296 0 0
T28 15096 296 0 0
T29 15392 592 0 0
T30 14874 74 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 111721 0 0
T1 14296689 37 0 0
T2 3844559 73 0 0
T3 3967177 710 0 0
T4 0 174 0 0
T5 0 205 0 0
T9 0 694 0 0
T10 0 30 0 0
T11 0 198 0 0
T12 0 24 0 0
T13 0 134 0 0
T14 0 12 0 0
T25 7213261 0 0 0
T26 6624554 0 0 0
T27 1888850 0 0 0
T28 1812704 0 0 0
T29 7538454 0 0 0
T30 7369105 0 0 0
T31 7363666 0 0 0
T67 0 1927 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 14296689 14292730 0 0
T6 7148918 7145662 0 0
T7 6925993 6923181 0 0
T8 7477663 7475147 0 0
T25 7213261 7209672 0 0
T26 6624554 6621335 0 0
T27 1888850 1885816 0 0
T28 1812704 1809152 0 0
T29 7538454 7536012 0 0
T30 7369105 7366700 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%