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Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_pre_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_sel_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_det_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_0_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_1_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_2_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.73 100.00 90.91 100.00 100.00 u_com_out_ctl_3_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 93.02 95.65 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 87.76 97.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_combo_intr_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 93.02 95.65 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 87.76 97.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_key_intr_status_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 87.50 100.00 50.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb
tb.dut.u_reg.u_key_intr_status_cdc.u_arb
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T3,T9
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T3,T9
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T3,T9
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T3,T9
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT2,T3,T9
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT2,T3,T9
Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T3,T9
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T3,T9
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT3,T9,T4
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT3,T9,T4
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3
Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28411100.00
CONT_ASSIGN28511100.00
CONT_ASSIGN30000
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
284 1 1
285 1 1
300 unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT2,T3,T9
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT2,T3,T9
Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS12266100.00
CONT_ASSIGN13611100.00
ALWAYS14066100.00
ALWAYS1561010100.00
CONT_ASSIGN18411100.00
ALWAYS1881919100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 1 1
130 1 1
133 1 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
211 1 1
212 1 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
MISSING_ELSE
229 1 1
244 1 1
245 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb
TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT15,T70,T87
10CoveredT1,T2,T3
11CoveredT15,T16,T17 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT15,T16,T17 

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T11,T13
11CoveredT2,T4,T5 

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT2,T3,T9
101Not Covered
110CoveredT1,T2,T3
111CoveredT2,T4,T5 

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT1,T2,T3
10CoveredT2,T4,T5 

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4 

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT15,T16,T17
10CoveredT5,T11,T13
11CoveredT1,T2,T3 

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT6,T7,T8
11CoveredT15,T16,T17 

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT6,T7,T8
11CoveredT1,T2,T3 

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T70,T87 

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT15,T70,T87
010CoveredT1,T2,T3
100CoveredT1,T2,T3 

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT15,T16,T17
11CoveredT1,T2,T3 

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT15,T16,T17
1CoveredT6,T7,T8 

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT15,T16,T17
10CoveredT1,T2,T3
11CoveredT15,T16,T17 

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT15,T16,T17
Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 112 2 2 100.00
IF 122 4 4 100.00
IF 140 4 4 100.00
IF 156 6 6 100.00
CASE 198 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	112	if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8 



	LineNo.	Expression
-1-:	122	if ((!rst_dst_ni))
-2-:	124	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	130	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T2,T4,T5
0 0 1 Covered T2,T4,T5
0 0 0 Covered T6,T7,T8 



	LineNo.	Expression
-1-:	140	if ((!rst_dst_ni))
-2-:	142	if (gen_wr_req.dst_lat_d)
-3-:	144	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T1,T2,T3
0 0 1 Covered T15,T70,T87
0 0 0 Covered T6,T7,T8 



	LineNo.	Expression
-1-:	156	if ((!rst_dst_ni))
-2-:	158	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	160	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	162	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	164	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T6,T7,T8
0 1 - - - Covered T2,T3,T4
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T15,T16,T17
0 0 0 0 1 Covered T15,T70,T87
0 0 0 0 0 Covered T6,T7,T8 



	LineNo.	Expression
-1-:	198	case (gen_wr_req.state_q)
-2-:	201	if (gen_wr_req.dst_req)
-3-:	205	if (dst_update)
-4-:	208	if ((dst_qs_o != dst_qs_i))
-5-:	218	if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T15,T16,T17
StIdle 0 0 1 - Covered T15,T70,T87
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T2,T3,T4
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 5983194 681 0 915
gen_wr_req.HwIdSelCheck_A 5983194 707 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5983194 681 0 915
T15 25917 6 0 1
T16 2477 1 0 1
T17 9820 2 0 1
T19 0 25 0 0
T20 0 9 0 0
T21 0 2 0 0
T22 0 18 0 0
T24 0 5 0 0
T32 463 0 0 1
T33 437 0 0 1
T34 504 0 0 1
T35 6387 0 0 1
T36 1404 0 0 1
T37 421 0 0 1
T38 4966 0 0 1
T51 0 7 0 0
T69 0 2 0 0

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5983194 707 0 0
T15 25917 8 0 0
T16 2477 1 0 0
T17 9820 2 0 0
T19 0 25 0 0
T20 0 9 0 0
T21 0 2 0 0
T22 0 18 0 0
T24 0 5 0 0
T32 463 0 0 0
T33 437 0 0 0
T34 504 0 0 0
T35 6387 0 0 0
T36 1404 0 0 0
T37 421 0 0 0
T38 4966 0 0 0
T51 0 7 0 0
T69 0 2 0 0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL5050100.00
CONT_ASSIGN10011100.00
ALWAYS11233100.00
ALWAYS12266100.00
CONT_ASSIGN13611100.00
ALWAYS14066100.00
ALWAYS1561010100.00
CONT_ASSIGN18411100.00
ALWAYS1881919100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN24411100.00
CONT_ASSIGN24511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
112 1 1
113 1 1
115 1 1
122 1 1
123 1 1
124 1 1
129 1 1
130 1 1
133 1 1
MISSING_ELSE
136 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
145 1 1
MISSING_ELSE
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 1 1
163 1 1
164 1 1
165 1 1
MISSING_ELSE
184 1 1
188 1 1
189 1 1
193 1 1
194 1 1
196 1 1
198 1 1
200 1 1
201 1 1
203 1 1
204 1 1
205 1 1
206 1 1
207 1 1
208 1 1
211 1 1
212 1 1
MISSING_ELSE
217 1 1
218 1 1
219 1 1
MISSING_ELSE
229 1 1
244 1 1
245 1 1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb
TotalCoveredPercent
Conditions434093.02
Logical434093.02
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT17,T23,T51
10CoveredT1,T2,T3
11CoveredT17,T23,T51 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT17,T23,T51 

 LINE       124
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T13
11CoveredT4,T5,T11 

 LINE       130
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT2,T3,T9
101Not Covered
110CoveredT1,T2,T3
111CoveredT4,T5,T11 

 LINE       136
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT6,T7,T8
01CoveredT1,T2,T3
10CoveredT4,T5,T11 

 LINE       158
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T3,T4 

 LINE       160
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT17,T23,T51
10CoveredT4,T5,T13
11CoveredT1,T2,T3 

 LINE       162
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT6,T7,T8
11CoveredT17,T23,T51 

 LINE       184
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T11
10CoveredT6,T7,T8
11CoveredT1,T2,T3 

 LINE       208
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T23,T51 

 LINE       229
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT6,T7,T8
001CoveredT17,T23,T51
010CoveredT1,T2,T3
100CoveredT1,T2,T3 

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT17,T23,T51
11CoveredT1,T2,T3 

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT17,T23,T51
1CoveredT6,T7,T8 

 LINE       245
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT17,T23,T51
10CoveredT1,T2,T3
11CoveredT17,T23,T51 

 LINE       245
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT17,T23,T51
Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 22 95.65
IF 112 2 2 100.00
IF 122 4 4 100.00
IF 140 4 4 100.00
IF 156 6 6 100.00
CASE 198 7 6 85.71

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	112	if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T6,T7,T8
0 Covered T6,T7,T8 



	LineNo.	Expression
-1-:	122	if ((!rst_dst_ni))
-2-:	124	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	130	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T4,T5,T11
0 0 1 Covered T4,T5,T11
0 0 0 Covered T6,T7,T8 



	LineNo.	Expression
-1-:	140	if ((!rst_dst_ni))
-2-:	142	if (gen_wr_req.dst_lat_d)
-3-:	144	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T6,T7,T8
0 1 - Covered T1,T2,T3
0 0 1 Covered T17,T23,T51
0 0 0 Covered T6,T7,T8 



	LineNo.	Expression
-1-:	156	if ((!rst_dst_ni))
-2-:	158	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	160	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	162	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	164	if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T6,T7,T8
0 1 - - - Covered T2,T3,T4
0 0 1 - - Covered T1,T2,T3
0 0 0 1 - Covered T17,T23,T51
0 0 0 0 1 Covered T17,T23,T51
0 0 0 0 0 Covered T6,T7,T8 



	LineNo.	Expression
-1-:	198	case (gen_wr_req.state_q)
-2-:	201	if (gen_wr_req.dst_req)
-3-:	205	if (dst_update)
-4-:	208	if ((dst_qs_o != dst_qs_i))
-5-:	218	if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T3
StIdle 0 1 - - Covered T17,T23,T51
StIdle 0 0 1 - Covered T17,T23,T51
StIdle 0 0 0 - Covered T1,T2,T3
StWait - - - 1 Covered T2,T3,T4
StWait - - - 0 Covered T1,T2,T3
default - - - - Not Covered

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 5983194 297 0 915
gen_wr_req.HwIdSelCheck_A 5983194 441 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5983194 297 0 915
T17 9820 4 0 1
T18 1663 0 0 1
T19 33673 0 0 1
T20 33590 0 0 1
T21 7670 0 0 1
T23 0 2 0 0
T51 0 9 0 0
T55 0 2 0 0
T56 0 2 0 0
T59 0 2 0 0
T60 0 4 0 0
T63 10230 0 0 1
T70 0 3 0 0
T71 0 3 0 0
T72 0 2 0 0
T73 447 0 0 1
T74 498 0 0 1
T75 408 0 0 1
T76 882 0 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 5983194 441 0 0
T17 9820 5 0 0
T18 1663 0 0 0
T19 33673 0 0 0
T20 33590 0 0 0
T21 7670 0 0 0
T23 0 3 0 0
T51 0 15 0 0
T55 0 4 0 0
T56 0 2 0 0
T59 0 2 0 0
T60 0 6 0 0
T63 10230 0 0 0
T70 0 3 0 0
T71 0 6 0 0
T72 0 3 0 0
T73 447 0 0 0
T74 498 0 0 0
T75 408 0 0 0
T76 882 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%