93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 0 | 50 | 0.00 | ||
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 0 | 5 | 0.00 | ||
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 0 | 5 | 0.00 | ||
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 165 | 0.00 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 0 | 50 | 0.00 | ||
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 0 | 100 | 0.00 | ||
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 0 | 50 | 0.00 | ||
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 0 | 50 | 0.00 | ||
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 0 | 50 | 0.00 | ||
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 0 | 50 | 0.00 | ||
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 0 | 50 | 0.00 | ||
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 0 | 50 | 0.00 | ||
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 0 | 50 | 0.00 | ||
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 0 | 2 | 0.00 | ||
| V2 | stress_all | sysrst_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | sysrst_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | sysrst_ctrl_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| sysrst_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| sysrst_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| sysrst_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 692 | 0.00 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| sysrst_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 932 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 0 | 0.00 |
| V2 | 15 | 15 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 934 failures:
0.sysrst_ctrl_smoke.59824541302715731009793557566000711017593007359835179199802856352417253830376
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest/run.log
1.sysrst_ctrl_smoke.69842048671807421217771426123876166008503377593053864063172056319102430238286
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest/run.log
... and 48 more failures.
0.sysrst_ctrl_in_out_inverted.64867777661876880982229883290395823893630782652479292883135423249503196955451
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest/run.log
1.sysrst_ctrl_in_out_inverted.106971547803981892137706757211213252039312597030477242856496162905772720170232
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest/run.log
... and 48 more failures.
0.sysrst_ctrl_combo_detect_ec_rst.30507937258139960793549533449414616072887215038999060512513731000039515608494
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest/run.log
1.sysrst_ctrl_combo_detect_ec_rst.72201915446149536908727784029631921718637968595532835736313733545219496466357
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest/run.log
... and 3 more failures.
0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.15664222001331488224513339817869778044335598563784713008561092159499363388236
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest/run.log
1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.5608556022231442815502308986743104412079839215739342102897988933059289837611
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest/run.log
... and 3 more failures.
0.sysrst_ctrl_pin_access_test.23396728759173373967846114205416255048939257210529936718767220752009662528663
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest/run.log
1.sysrst_ctrl_pin_access_test.112245485091189972651950067370073678899456937555613353400755283542043193914785
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest/run.log
... and 48 more failures.
Job sysrst_ctrl-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/default/build.log
Job ID: smart:39be4f58-fcd8-455a-a31d-96aa3f657082
Job sysrst_ctrl-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/cover_reg_top/build.log
Job ID: smart:fcac9e79-c953-4dd3-95f8-a94aa369cf8a