Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1305000248	9667	0	0
auto_block_debounce_ctl_rd_A	1305000248	1388	0	0
auto_block_out_ctl_rd_A	1305000248	1685	0	0
com_det_ctl_0_rd_A	1305000248	3368	0	0
com_det_ctl_1_rd_A	1305000248	3570	0	0
com_det_ctl_2_rd_A	1305000248	3621	0	0
com_det_ctl_3_rd_A	1305000248	3515	0	0
com_out_ctl_0_rd_A	1305000248	3703	0	0
com_out_ctl_1_rd_A	1305000248	3831	0	0
com_out_ctl_2_rd_A	1305000248	3739	0	0
com_out_ctl_3_rd_A	1305000248	3684	0	0
com_pre_det_ctl_0_rd_A	1305000248	1010	0	0
com_pre_det_ctl_1_rd_A	1305000248	951	0	0
com_pre_det_ctl_2_rd_A	1305000248	1033	0	0
com_pre_det_ctl_3_rd_A	1305000248	939	0	0
com_pre_sel_ctl_0_rd_A	1305000248	3935	0	0
com_pre_sel_ctl_1_rd_A	1305000248	3903	0	0
com_pre_sel_ctl_2_rd_A	1305000248	3832	0	0
com_pre_sel_ctl_3_rd_A	1305000248	3915	0	0
com_sel_ctl_0_rd_A	1305000248	3827	0	0
com_sel_ctl_1_rd_A	1305000248	3666	0	0
com_sel_ctl_2_rd_A	1305000248	3961	0	0
com_sel_ctl_3_rd_A	1305000248	3821	0	0
ec_rst_ctl_rd_A	1305000248	2177	0	0
intr_enable_rd_A	1305000248	1709	0	0
key_intr_ctl_rd_A	1305000248	1689	0	0
key_intr_debounce_ctl_rd_A	1305000248	1041	0	0
key_invert_ctl_rd_A	1305000248	3474	0	0
pin_allowed_ctl_rd_A	1305000248	3957	0	0
pin_out_ctl_rd_A	1305000248	3599	0	0
pin_out_value_rd_A	1305000248	3487	0	0
regwen_rd_A	1305000248	1374	0	0
ulp_ac_debounce_ctl_rd_A	1305000248	1087	0	0
ulp_ctl_rd_A	1305000248	1229	0	0
ulp_lid_debounce_ctl_rd_A	1305000248	1152	0	0
ulp_pwrb_debounce_ctl_rd_A	1305000248	1056	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	9667	0	0
T2	313506	19	0	0
T3	226608	0	0	0
T6	730055	17	0	0
T7	162836	0	0	0
T9	0	14	0	0
T13	0	14	0	0
T15	0	5	0	0
T17	0	4	0	0
T22	0	7	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T28	236877	0	0	0
T29	58441	0	0	0
T73	0	31	0	0
T81	0	30	0	0
T87	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1388	0	0
T9	470883	36	0	0
T10	458037	0	0	0
T17	0	39	0	0
T41	240844	0	0	0
T47	357684	19	0	0
T48	86592	0	0	0
T50	0	3	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T103	0	6	0	0
T110	0	9	0	0
T119	0	3	0	0
T151	401202	0	0	0
T271	0	2	0	0
T272	0	13	0	0
T273	0	5	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1685	0	0
T9	470883	16	0	0
T10	458037	0	0	0
T17	0	26	0	0
T41	240844	0	0	0
T47	357684	13	0	0
T48	86592	0	0	0
T50	0	6	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T103	0	1	0	0
T110	0	9	0	0
T119	0	20	0	0
T151	401202	0	0	0
T271	0	4	0	0
T272	0	16	0	0
T273	0	10	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3368	0	0
T1	138503	32	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	46	0	0
T14	0	39	0	0
T17	0	13	0	0
T20	0	60	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	61	0	0
T69	0	31	0	0
T185	0	59	0	0
T231	0	57	0	0
T237	0	68	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3570	0	0
T1	138503	47	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	55	0	0
T14	0	44	0	0
T17	0	15	0	0
T20	0	75	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	69	0	0
T69	0	37	0	0
T185	0	53	0	0
T231	0	85	0	0
T237	0	62	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3621	0	0
T1	138503	31	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	45	0	0
T14	0	33	0	0
T17	0	10	0	0
T20	0	65	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	72	0	0
T69	0	43	0	0
T185	0	64	0	0
T231	0	71	0	0
T237	0	56	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3515	0	0
T1	138503	44	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	35	0	0
T14	0	45	0	0
T17	0	15	0	0
T20	0	60	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	61	0	0
T69	0	23	0	0
T185	0	53	0	0
T231	0	60	0	0
T237	0	70	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3703	0	0
T1	138503	37	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	42	0	0
T14	0	23	0	0
T17	0	18	0	0
T20	0	56	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	62	0	0
T69	0	42	0	0
T185	0	66	0	0
T231	0	63	0	0
T237	0	56	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3831	0	0
T1	138503	21	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	50	0	0
T14	0	49	0	0
T17	0	24	0	0
T20	0	84	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	62	0	0
T69	0	55	0	0
T185	0	71	0	0
T231	0	88	0	0
T237	0	83	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3739	0	0
T1	138503	21	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	48	0	0
T14	0	32	0	0
T17	0	27	0	0
T20	0	67	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	63	0	0
T69	0	33	0	0
T185	0	67	0	0
T231	0	96	0	0
T237	0	62	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3684	0	0
T1	138503	38	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	39	0	0
T14	0	35	0	0
T17	0	14	0	0
T20	0	67	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	71	0	0
T69	0	41	0	0
T185	0	73	0	0
T231	0	81	0	0
T237	0	54	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1010	0	0
T9	470883	46	0	0
T10	458037	0	0	0
T17	0	30	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	16	0	0
T146	0	38	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	7	0	0
T233	0	8	0	0
T274	0	26	0	0
T275	0	21	0	0
T276	0	31	0	0
T277	0	9	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	951	0	0
T9	470883	24	0	0
T10	458037	0	0	0
T17	0	13	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	13	0	0
T146	0	25	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	7	0	0
T233	0	17	0	0
T274	0	18	0	0
T275	0	32	0	0
T276	0	37	0	0
T277	0	3	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1033	0	0
T9	470883	33	0	0
T10	458037	0	0	0
T17	0	15	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	11	0	0
T146	0	37	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	9	0	0
T233	0	5	0	0
T274	0	13	0	0
T275	0	25	0	0
T276	0	33	0	0
T277	0	9	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	939	0	0
T9	470883	36	0	0
T10	458037	0	0	0
T17	0	14	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	6	0	0
T146	0	28	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	4	0	0
T233	0	9	0	0
T274	0	13	0	0
T275	0	13	0	0
T276	0	33	0	0
T277	0	19	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3935	0	0
T1	138503	47	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	39	0	0
T14	0	32	0	0
T17	0	11	0	0
T20	0	59	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	56	0	0
T69	0	36	0	0
T185	0	47	0	0
T231	0	67	0	0
T237	0	80	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3903	0	0
T1	138503	54	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	45	0	0
T14	0	30	0	0
T17	0	12	0	0
T20	0	84	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	63	0	0
T69	0	23	0	0
T185	0	95	0	0
T231	0	61	0	0
T237	0	68	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3832	0	0
T1	138503	36	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	48	0	0
T14	0	19	0	0
T17	0	20	0	0
T20	0	84	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	91	0	0
T69	0	38	0	0
T185	0	64	0	0
T231	0	80	0	0
T237	0	60	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3915	0	0
T1	138503	49	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	56	0	0
T14	0	33	0	0
T17	0	20	0	0
T20	0	72	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	50	0	0
T69	0	44	0	0
T185	0	58	0	0
T231	0	78	0	0
T237	0	62	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3827	0	0
T1	138503	65	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	30	0	0
T14	0	32	0	0
T17	0	29	0	0
T20	0	70	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	43	0	0
T69	0	36	0	0
T185	0	52	0	0
T231	0	61	0	0
T237	0	67	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3666	0	0
T1	138503	61	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	42	0	0
T14	0	49	0	0
T17	0	12	0	0
T20	0	90	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	56	0	0
T69	0	47	0	0
T185	0	65	0	0
T231	0	53	0	0
T237	0	68	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3961	0	0
T1	138503	51	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	30	0	0
T14	0	50	0	0
T17	0	11	0	0
T20	0	86	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	82	0	0
T69	0	25	0	0
T185	0	78	0	0
T231	0	61	0	0
T237	0	65	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3821	0	0
T1	138503	43	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	43	0	0
T14	0	40	0	0
T17	0	19	0	0
T20	0	80	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T44	0	71	0	0
T69	0	31	0	0
T185	0	65	0	0
T231	0	89	0	0
T237	0	61	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	2177	0	0
T1	138503	18	0	0
T2	313506	0	0	0
T3	226608	0	0	0
T4	53189	0	0	0
T5	51284	0	0	0
T6	730055	0	0	0
T9	0	48	0	0
T14	0	9	0	0
T17	0	23	0	0
T20	0	35	0	0
T24	171952	0	0	0
T25	74471	0	0	0
T26	95003	0	0	0
T27	246961	0	0	0
T68	0	4	0	0
T69	0	7	0	0
T184	0	1	0	0
T185	0	6	0	0
T237	0	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1709	0	0
T9	470883	34	0	0
T10	458037	0	0	0
T17	0	20	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T66	0	66	0	0
T97	0	40	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	1	0	0
T233	0	11	0	0
T274	0	44	0	0
T275	0	18	0	0
T276	0	22	0	0
T278	0	8	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1689	0	0
T9	470883	35	0	0
T10	458037	0	0	0
T17	0	16	0	0
T18	0	2	0	0
T21	0	5	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T130	0	2	0	0
T148	0	2	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T180	0	8	0	0
T196	0	2	0	0
T233	0	6	0	0
T274	0	28	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1041	0	0
T9	470883	33	0	0
T10	458037	0	0	0
T17	0	12	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	21	0	0
T146	0	27	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T233	0	11	0	0
T274	0	23	0	0
T275	0	22	0	0
T276	0	23	0	0
T277	0	23	0	0
T279	0	32	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3474	0	0
T9	470883	103	0	0
T10	458037	0	0	0
T17	0	64	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T62	0	41	0	0
T65	63012	0	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T183	0	67	0	0
T267	0	91	0	0
T274	0	99	0	0
T280	0	80	0	0
T281	0	67	0	0
T282	0	59	0	0
T283	0	49	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3957	0	0
T9	470883	60	0	0
T10	458037	0	0	0
T17	0	21	0	0
T40	626416	0	0	0
T47	357684	0	0	0
T52	50602	0	0	0
T57	544244	0	0	0
T61	59751	0	0	0
T63	241159	64	0	0
T64	63239	79	0	0
T67	0	75	0	0
T111	0	81	0	0
T204	0	48	0	0
T236	206771	0	0	0
T284	0	78	0	0
T285	0	62	0	0
T286	0	72	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3599	0	0
T9	470883	44	0	0
T10	458037	0	0	0
T17	0	18	0	0
T40	626416	0	0	0
T47	357684	0	0	0
T52	50602	0	0	0
T57	544244	0	0	0
T61	59751	0	0	0
T63	241159	63	0	0
T64	63239	60	0	0
T67	0	56	0	0
T111	0	94	0	0
T204	0	77	0	0
T236	206771	0	0	0
T284	0	80	0	0
T285	0	72	0	0
T286	0	23	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	3487	0	0
T9	470883	38	0	0
T10	458037	0	0	0
T17	0	12	0	0
T40	626416	0	0	0
T47	357684	0	0	0
T52	50602	0	0	0
T57	544244	0	0	0
T61	59751	0	0	0
T63	241159	52	0	0
T64	63239	89	0	0
T67	0	92	0	0
T111	0	57	0	0
T204	0	72	0	0
T236	206771	0	0	0
T284	0	68	0	0
T285	0	74	0	0
T286	0	30	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1374	0	0
T9	470883	38	0	0
T10	458037	0	0	0
T17	0	15	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	2	0	0
T146	0	29	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	7	0	0
T233	0	16	0	0
T274	0	22	0	0
T275	0	5	0	0
T276	0	21	0	0
T277	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1087	0	0
T9	470883	24	0	0
T10	458037	0	0	0
T17	0	27	0	0
T31	0	1	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	8	0	0
T127	0	13	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	14	0	0
T233	0	24	0	0
T274	0	20	0	0
T287	0	3	0	0
T288	0	5	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1229	0	0
T9	470883	40	0	0
T10	458037	0	0	0
T17	0	19	0	0
T31	0	4	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	23	0	0
T127	0	12	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	12	0	0
T233	0	7	0	0
T274	0	13	0	0
T287	0	1	0	0
T288	0	6	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1152	0	0
T9	470883	37	0	0
T10	458037	0	0	0
T17	0	22	0	0
T31	0	4	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	7	0	0
T127	0	8	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	8	0	0
T233	0	28	0	0
T274	0	35	0	0
T287	0	3	0	0
T288	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1305000248	1056	0	0
T9	470883	29	0	0
T10	458037	0	0	0
T17	0	26	0	0
T31	0	6	0	0
T41	240844	0	0	0
T48	86592	0	0	0
T53	250988	0	0	0
T54	210183	0	0	0
T58	499912	0	0	0
T65	63012	0	0	0
T97	0	6	0	0
T127	0	13	0	0
T151	401202	0	0	0
T152	210930	0	0	0
T219	0	15	0	0
T233	0	1	0	0
T274	0	20	0	0
T287	0	1	0	0
T288	0	6	0	0