ASSERT | PROPERTIES | SEQUENCES | |
Total | 1058 | 0 | 10 |
Category 0 | 1058 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 1058 | 0 | 10 |
Severity 0 | 1058 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 1058 | 100.00 |
Uncovered | 9 | 0.85 |
Success | 1049 | 99.15 |
Failure | 0 | 0.00 |
Incomplete | 4 | 0.38 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 9375037 | 737 | 0 | 913 | |
tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 9375037 | 247 | 0 | 913 | |
tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 9375037 | 80 | 0 | 913 | |
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 9375037 | 810 | 0 | 913 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1396953480 | 1509337 | 1509337 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1396953480 | 4082 | 4082 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1396953480 | 9580 | 9580 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1396953480 | 7052 | 7052 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1396953480 | 8836 | 8836 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1396953480 | 5652 | 5652 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1396953480 | 4505 | 4505 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1396953480 | 7066 | 7066 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1396953480 | 12400 | 12400 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1396953480 | 97417 | 97417 | 845 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1396953480 | 1509337 | 1509337 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1396953480 | 4082 | 4082 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1396953480 | 9580 | 9580 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1396953480 | 7052 | 7052 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1396953480 | 8836 | 8836 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1396953480 | 5652 | 5652 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1396953480 | 4505 | 4505 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1396953480 | 7066 | 7066 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1396953480 | 12400 | 12400 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1396953480 | 97417 | 97417 | 845 |