Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T11,T14,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T11,T14,T15
1	1	Covered	T2,T3,T7

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	232711	0	0
SrcPulseCheck_M	2147483647	235102	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	232711
T1	1797297	0
T2	2852079	188
T3	6451514	85
T4	865662	0
T5	316008	0
T6	161340	0
T7	4039012	176
T8	7572088	224
T9	518327	51
T10	170885	70
T13	0	96
T25	1200414	0
T26	1343166	0
T27	1661147	0
T28	2698536	12
T29	583936	0
T30	1372857	0
T31	744950	0
T32	5309136	0
T33	0	17
T38	0	14
T50	236235	0
T51	966366	12
T52	0	17
T59	0	17
T60	0	1
T61	0	14
T62	0	14
T63	0	12
T64	0	16
T65	0	18
T66	0	8
T67	0	2
T68	94109	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	235102
T1	1683455	0
T2	3007445	188
T3	6826006	85
T4	865662	0
T5	316008	0
T6	161340	0
T7	4237028	176
T8	6793337	224
T9	10798	51
T10	18817	70
T13	0	96
T25	1399417	0
T26	1468962	0
T27	1774033	0
T28	2881464	12
T29	626582	0
T30	1422353	0
T31	744950	0
T32	5309136	0
T33	0	17
T38	0	14
T50	492	0
T51	860335	12
T52	0	17
T59	0	17
T60	0	1
T61	0	14
T62	0	14
T63	0	12
T64	0	16
T65	0	18
T66	0	8
T67	0	2
T68	408	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T47,T48,T49

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T47,T48,T49
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	2000	0	0
SrcPulseCheck_M	1396952907	2058	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	2000
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	3
T26	507	0
T27	405	0
T28	768	0
T29	547	1
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	2058
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	3
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	1
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T47,T48,T49

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T47,T48,T49
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	2050	0	0
SrcPulseCheck_M	9375037	2050	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	2050
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	3
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	1
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T69	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	2050
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	3
T26	507	0
T27	405	0
T28	768	0
T29	547	1
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T69	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T30,T10,T11
1	1	Covered	T11,T15,T39

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T11,T15,T39
1	1	Covered	T30,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1071	0	0
SrcPulseCheck_M	1396952907	1133	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1071
T8	33137	0
T9	10798	0
T10	18817	1
T11	0	3
T14	0	1
T15	0	3
T30	663	1
T31	451	0
T32	450	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	492	0
T51	711	0
T52	8539	0
T68	408	0
T70	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1133
T8	811888	0
T9	518327	0
T10	170885	1
T11	0	3
T14	0	1
T15	0	3
T30	50159	1
T31	29347	0
T32	220764	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	236235	0
T51	106742	0
T52	418443	0
T68	94109	0
T70	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T30,T10,T11
1	1	Covered	T11,T15,T39

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T11,T15,T39
1	1	Covered	T30,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1124	0	0
SrcPulseCheck_M	9375037	1124	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1124
T8	811888	0
T9	518327	0
T10	170885	1
T11	0	3
T14	0	1
T15	0	3
T30	50159	1
T31	29347	0
T32	220764	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	236235	0
T51	106742	0
T52	418443	0
T68	94109	0
T70	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1124
T8	33137	0
T9	10798	0
T10	18817	1
T11	0	3
T14	0	1
T15	0	3
T30	663	1
T31	451	0
T32	450	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	492	0
T51	711	0
T52	8539	0
T68	408	0
T70	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T30,T10,T11
1	1	Covered	T11,T15,T39

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T11,T15,T39
1	1	Covered	T30,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1075	0	0
SrcPulseCheck_M	1396952907	1138	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1075
T8	33137	0
T9	10798	0
T10	18817	1
T11	0	3
T14	0	1
T15	0	3
T30	663	1
T31	451	0
T32	450	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	492	0
T51	711	0
T52	8539	0
T68	408	0
T70	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1138
T8	811888	0
T9	518327	0
T10	170885	1
T11	0	3
T14	0	1
T15	0	3
T30	50159	1
T31	29347	0
T32	220764	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	236235	0
T51	106742	0
T52	418443	0
T68	94109	0
T70	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T30,T10,T11
1	1	Covered	T11,T15,T39

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T11,T15,T39
1	1	Covered	T30,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1128	0	0
SrcPulseCheck_M	9375037	1128	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1128
T8	811888	0
T9	518327	0
T10	170885	1
T11	0	3
T14	0	1
T15	0	3
T30	50159	1
T31	29347	0
T32	220764	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	236235	0
T51	106742	0
T52	418443	0
T68	94109	0
T70	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1128
T8	33137	0
T9	10798	0
T10	18817	1
T11	0	3
T14	0	1
T15	0	3
T30	663	1
T31	451	0
T32	450	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	492	0
T51	711	0
T52	8539	0
T68	408	0
T70	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T30,T10,T11
1	1	Covered	T11,T15,T39

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T11,T15,T39
1	1	Covered	T30,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1030	0	0
SrcPulseCheck_M	1396952907	1095	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1030
T8	33137	0
T9	10798	0
T10	18817	1
T11	0	3
T14	0	1
T15	0	3
T30	663	1
T31	451	0
T32	450	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	492	0
T51	711	0
T52	8539	0
T68	408	0
T70	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1095
T8	811888	0
T9	518327	0
T10	170885	1
T11	0	3
T14	0	1
T15	0	3
T30	50159	1
T31	29347	0
T32	220764	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	236235	0
T51	106742	0
T52	418443	0
T68	94109	0
T70	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T30,T10,T11
1	1	Covered	T11,T15,T39

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T30,T10,T11
1	0	Covered	T11,T15,T39
1	1	Covered	T30,T10,T11

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1085	0	0
SrcPulseCheck_M	9375037	1085	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1085
T8	811888	0
T9	518327	0
T10	170885	1
T11	0	3
T14	0	1
T15	0	3
T30	50159	1
T31	29347	0
T32	220764	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	236235	0
T51	106742	0
T52	418443	0
T68	94109	0
T70	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1085
T8	33137	0
T9	10798	0
T10	18817	1
T11	0	3
T14	0	1
T15	0	3
T30	663	1
T31	451	0
T32	450	0
T39	0	2
T40	0	1
T41	0	1
T42	0	1
T50	492	0
T51	711	0
T52	8539	0
T68	408	0
T70	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1071	0	0
SrcPulseCheck_M	1396952907	1134	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1071
T11	1537	4
T12	944	0
T13	16310	0
T14	7559	2
T15	0	4
T33	5966	0
T34	502	0
T35	406	0
T36	403	0
T37	493	0
T38	729	0
T39	0	2
T40	0	2
T41	0	2
T42	0	2
T43	0	2
T44	0	6
T71	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1134
T11	240975	4
T12	335568	0
T13	195733	0
T14	327219	2
T15	0	4
T33	283414	0
T34	248400	0
T35	48767	0
T36	98705	0
T37	123504	0
T38	69295	0
T39	0	2
T40	0	2
T41	0	2
T42	0	2
T43	0	2
T44	0	6
T71	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1125	0	0
SrcPulseCheck_M	9375037	1125	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1125
T11	240975	4
T12	335568	0
T13	195733	0
T14	327219	2
T15	0	4
T33	283414	0
T34	248400	0
T35	48767	0
T36	98705	0
T37	123504	0
T38	69295	0
T39	0	2
T40	0	2
T41	0	2
T42	0	2
T43	0	2
T44	0	6
T71	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1125
T11	1537	4
T12	944	0
T13	16310	0
T14	7559	2
T15	0	4
T33	5966	0
T34	502	0
T35	406	0
T36	403	0
T37	493	0
T38	729	0
T39	0	2
T40	0	2
T41	0	2
T42	0	2
T43	0	2
T44	0	6
T71	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15
1	1	Covered	T11,T15,T44

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T15,T44
1	1	Covered	T11,T14,T15

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	540	0	0
SrcPulseCheck_M	1396952907	606	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	540
T11	1537	2
T12	944	0
T13	16310	0
T14	7559	1
T15	0	2
T33	5966	0
T34	502	0
T35	406	0
T36	403	0
T37	493	0
T38	729	0
T39	0	1
T40	0	1
T41	0	1
T42	0	1
T43	0	1
T44	0	3
T45	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	606
T11	240975	2
T12	335568	0
T13	195733	0
T14	327219	1
T15	0	2
T33	283414	0
T34	248400	0
T35	48767	0
T36	98705	0
T37	123504	0
T38	69295	0
T39	0	1
T40	0	1
T41	0	1
T42	0	1
T43	0	1
T44	0	3
T45	0	1

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T11,T15,T60

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T11,T15,T60
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1183	0	0
SrcPulseCheck_M	1396952907	1262	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1183
T2	27744	2
T3	17023	4
T7	27126	9
T8	0	13
T9	0	3
T10	0	1
T11	0	2
T13	0	5
T14	0	1
T15	0	2
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1262
T2	105427	2
T3	204269	4
T7	126134	9
T8	0	13
T9	0	3
T10	0	1
T11	0	2
T13	0	5
T14	0	1
T15	0	2
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T25,T10,T50
1	0	Covered	T25,T10,T50
1	1	Covered	T25,T10,T50

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T25,T10,T50
1	0	Covered	T25,T10,T50
1	1	Covered	T25,T10,T50

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	3117	0	0
SrcPulseCheck_M	1396952907	3181	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	3117
T2	27744	0
T3	17023	0
T7	27126	0
T10	0	20
T14	0	20
T25	492	20
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T37	0	20
T50	0	20
T62	0	20
T63	0	20
T74	0	20
T75	0	20
T76	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	3181
T2	105427	0
T3	204269	0
T7	126134	0
T10	0	20
T14	0	20
T25	199495	20
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T37	0	20
T50	0	20
T62	0	20
T63	0	20
T74	0	20
T75	0	20
T76	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T25,T10,T50
1	0	Covered	T25,T10,T50
1	1	Covered	T25,T10,T50

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T25,T10,T50
1	0	Covered	T25,T10,T50
1	1	Covered	T25,T10,T50

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	3173	0	0
SrcPulseCheck_M	9375037	3173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	3173
T2	105427	0
T3	204269	0
T7	126134	0
T10	0	20
T14	0	20
T25	199495	20
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T37	0	20
T50	0	20
T62	0	20
T63	0	20
T74	0	20
T75	0	20
T76	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	3173
T2	27744	0
T3	17023	0
T7	27126	0
T10	0	20
T14	0	20
T25	492	20
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T37	0	20
T50	0	20
T62	0	20
T63	0	20
T74	0	20
T75	0	20
T76	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T25,T2
1	0	Covered	T4,T25,T2
1	1	Covered	T4,T2,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T25,T2
1	0	Covered	T4,T2,T26
1	1	Covered	T4,T25,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	6571	0	0
SrcPulseCheck_M	1396952907	6639	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	6571
T1	215137	0
T2	27744	40
T3	17023	0
T4	2290	40
T5	419	0
T6	444	0
T10	0	61
T25	492	1
T26	507	20
T27	405	0
T28	768	0
T34	0	20
T50	0	1
T74	0	1
T77	0	20
T78	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	6639
T1	101295	0
T2	105427	40
T3	204269	0
T4	286264	40
T5	104917	0
T6	53336	0
T10	0	61
T25	199495	1
T26	63405	20
T27	56848	0
T28	92232	0
T34	0	20
T50	0	1
T74	0	1
T77	0	20
T78	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T25,T2
1	0	Covered	T4,T25,T2
1	1	Covered	T4,T2,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T25,T2
1	0	Covered	T4,T2,T26
1	1	Covered	T4,T25,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	6624	0	0
SrcPulseCheck_M	9375037	6624	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	6624
T1	101295	0
T2	105427	40
T3	204269	0
T4	286264	40
T5	104917	0
T6	53336	0
T10	0	61
T25	199495	1
T26	63405	20
T27	56848	0
T28	92232	0
T34	0	20
T50	0	1
T74	0	1
T77	0	20
T78	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	6624
T1	215137	0
T2	27744	40
T3	17023	0
T4	2290	40
T5	419	0
T6	444	0
T10	0	61
T25	492	1
T26	507	20
T27	405	0
T28	768	0
T34	0	20
T50	0	1
T74	0	1
T77	0	20
T78	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T25,T2
1	0	Covered	T4,T25,T2
1	1	Covered	T4,T2,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T25,T2
1	0	Covered	T4,T2,T26
1	1	Covered	T4,T25,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	7733	0	0
SrcPulseCheck_M	1396952907	7800	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	7733
T1	215137	0
T2	27744	51
T3	17023	5
T4	2290	40
T5	419	0
T6	444	0
T7	0	11
T8	0	14
T9	0	3
T10	0	65
T25	492	1
T26	507	20
T27	405	0
T28	768	0
T29	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	7800
T1	101295	0
T2	105427	51
T3	204269	5
T4	286264	40
T5	104917	0
T6	53336	0
T7	0	11
T8	0	14
T9	0	3
T10	0	65
T25	199495	1
T26	63405	20
T27	56848	0
T28	92232	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T25,T2
1	0	Covered	T4,T25,T2
1	1	Covered	T4,T2,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T25,T2
1	0	Covered	T4,T2,T26
1	1	Covered	T4,T25,T2

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	7787	0	0
SrcPulseCheck_M	9375037	7787	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	7787
T1	101295	0
T2	105427	51
T3	204269	5
T4	286264	40
T5	104917	0
T6	53336	0
T7	0	11
T8	0	14
T9	0	3
T10	0	65
T25	199495	1
T26	63405	20
T27	56848	0
T28	92232	0
T29	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	7787
T1	215137	0
T2	27744	51
T3	17023	5
T4	2290	40
T5	419	0
T6	444	0
T7	0	11
T8	0	14
T9	0	3
T10	0	65
T25	492	1
T26	507	20
T27	405	0
T28	768	0
T29	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T26
1	0	Covered	T4,T2,T26
1	1	Covered	T4,T2,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T26
1	0	Covered	T4,T2,T26
1	1	Covered	T4,T2,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	6472	0	0
SrcPulseCheck_M	1396952907	6537	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	6472
T1	215137	0
T2	27744	40
T3	17023	0
T4	2290	40
T5	419	0
T6	444	0
T10	0	60
T14	0	20
T25	492	0
T26	507	20
T27	405	0
T28	768	0
T34	0	20
T63	0	20
T77	0	20
T78	0	20
T79	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	6537
T1	101295	0
T2	105427	40
T3	204269	0
T4	286264	40
T5	104917	0
T6	53336	0
T10	0	60
T14	0	20
T25	199495	0
T26	63405	20
T27	56848	0
T28	92232	0
T34	0	20
T63	0	20
T77	0	20
T78	0	20
T79	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T26
1	0	Covered	T4,T2,T26
1	1	Covered	T4,T2,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T2,T26
1	0	Covered	T4,T2,T26
1	1	Covered	T4,T2,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	6523	0	0
SrcPulseCheck_M	9375037	6523	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	6523
T1	101295	0
T2	105427	40
T3	204269	0
T4	286264	40
T5	104917	0
T6	53336	0
T10	0	60
T14	0	20
T25	199495	0
T26	63405	20
T27	56848	0
T28	92232	0
T34	0	20
T63	0	20
T77	0	20
T78	0	20
T79	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	6523
T1	215137	0
T2	27744	40
T3	17023	0
T4	2290	40
T5	419	0
T6	444	0
T10	0	60
T14	0	20
T25	492	0
T26	507	20
T27	405	0
T28	768	0
T34	0	20
T63	0	20
T77	0	20
T78	0	20
T79	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T12
1	0	Covered	T91,T92,T47
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1033	0	0
SrcPulseCheck_M	1396952907	1096	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1033
T1	215137	1
T2	27744	0
T3	17023	0
T7	27126	0
T10	0	1
T12	0	1
T14	0	1
T17	0	1
T20	0	1
T21	0	1
T22	0	2
T23	0	1
T24	0	1
T25	492	0
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1096
T1	101295	1
T2	105427	0
T3	204269	0
T7	126134	0
T10	0	1
T12	0	1
T14	0	1
T17	0	1
T20	0	1
T21	0	1
T22	0	2
T23	0	1
T24	0	1
T25	199495	0
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T12
1	0	Covered	T91,T92,T47
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1088	0	0
SrcPulseCheck_M	9375037	1088	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1088
T1	101295	1
T2	105427	0
T3	204269	0
T7	126134	0
T10	0	1
T12	0	1
T14	0	1
T17	0	1
T20	0	1
T21	0	1
T22	0	2
T23	0	1
T24	0	1
T25	199495	0
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1088
T1	215137	1
T2	27744	0
T3	17023	0
T7	27126	0
T10	0	1
T12	0	1
T14	0	1
T17	0	1
T20	0	1
T21	0	1
T22	0	2
T23	0	1
T24	0	1
T25	492	0
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T91,T92,T47
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1993	0	0
SrcPulseCheck_M	1396952907	2059	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1993
T1	215137	1
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	4
T12	0	1
T25	492	0
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T33	0	1
T52	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	2059
T1	101295	1
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	4
T12	0	1
T25	199495	0
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T33	0	1
T52	0	1

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T91,T92,T47
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	2050	0	0
SrcPulseCheck_M	9375037	2050	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	2050
T1	101295	1
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	4
T12	0	1
T25	199495	0
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T33	0	1
T52	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	2050
T1	215137	1
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	4
T12	0	1
T25	492	0
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T33	0	1
T52	0	1

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T28,T51
1	0	Covered	T2,T28,T51
1	1	Covered	T2,T28,T51

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T28,T51
1	0	Covered	T2,T28,T51
1	1	Covered	T2,T28,T51

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1328	0	0
SrcPulseCheck_M	1396952907	1391	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1328
T2	27744	4
T3	17023	0
T7	27126	0
T10	0	10
T26	507	0
T27	405	0
T28	768	4
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T38	0	4
T51	0	3
T61	0	4
T62	0	4
T63	0	3
T64	0	5
T65	0	6

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1391
T2	105427	4
T3	204269	0
T7	126134	0
T10	0	10
T26	63405	0
T27	56848	0
T28	92232	4
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T38	0	4
T51	0	3
T61	0	4
T62	0	4
T63	0	3
T64	0	5
T65	0	6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T28,T51
1	0	Covered	T2,T28,T51
1	1	Covered	T2,T28,T51

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T28,T51
1	0	Covered	T2,T28,T51
1	1	Covered	T2,T28,T51

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1381	0	0
SrcPulseCheck_M	9375037	1381	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1381
T2	105427	4
T3	204269	0
T7	126134	0
T10	0	10
T26	63405	0
T27	56848	0
T28	92232	4
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T38	0	4
T51	0	3
T61	0	4
T62	0	4
T63	0	3
T64	0	5
T65	0	6

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1381
T2	27744	4
T3	17023	0
T7	27126	0
T10	0	10
T26	507	0
T27	405	0
T28	768	4
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T38	0	4
T51	0	3
T61	0	4
T62	0	4
T63	0	3
T64	0	5
T65	0	6

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T28,T51
1	0	Covered	T2,T28,T51
1	1	Covered	T2,T28,T51

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T28,T51
1	0	Covered	T2,T28,T51
1	1	Covered	T2,T28,T51

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1150	0	0
SrcPulseCheck_M	1396952907	1217	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1150
T2	27744	2
T3	17023	0
T7	27126	0
T10	0	7
T26	507	0
T27	405	0
T28	768	2
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T38	0	3
T51	0	3
T61	0	3
T62	0	3
T63	0	3
T64	0	3
T65	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1217
T2	105427	2
T3	204269	0
T7	126134	0
T10	0	7
T26	63405	0
T27	56848	0
T28	92232	2
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T38	0	3
T51	0	3
T61	0	3
T62	0	3
T63	0	3
T64	0	3
T65	0	3

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T28,T51
1	0	Covered	T2,T28,T51
1	1	Covered	T2,T28,T51

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T28,T51
1	0	Covered	T2,T28,T51
1	1	Covered	T2,T28,T51

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1206	0	0
SrcPulseCheck_M	9375037	1206	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1206
T2	105427	2
T3	204269	0
T7	126134	0
T10	0	7
T26	63405	0
T27	56848	0
T28	92232	2
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T38	0	3
T51	0	3
T61	0	3
T62	0	3
T63	0	3
T64	0	3
T65	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1206
T2	27744	2
T3	17023	0
T7	27126	0
T10	0	7
T26	507	0
T27	405	0
T28	768	2
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T38	0	3
T51	0	3
T61	0	3
T62	0	3
T63	0	3
T64	0	3
T65	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	7053	0	0
SrcPulseCheck_M	1396952907	7116	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	7053
T3	17023	68
T7	27126	0
T8	33137	0
T9	0	60
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T51	711	0
T52	0	69
T59	0	74
T60	0	51
T66	0	85
T67	0	63
T80	0	51
T81	0	71

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	7116
T3	204269	68
T7	126134	0
T8	811888	0
T9	0	60
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T51	106742	0
T52	0	69
T59	0	74
T60	0	51
T66	0	85
T67	0	63
T80	0	51
T81	0	71

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	7107	0	0
SrcPulseCheck_M	9375037	7107	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	7107
T3	204269	68
T7	126134	0
T8	811888	0
T9	0	60
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T51	106742	0
T52	0	69
T59	0	74
T60	0	51
T66	0	85
T67	0	63
T80	0	51
T81	0	71

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	7107
T3	17023	68
T7	27126	0
T8	33137	0
T9	0	60
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T51	711	0
T52	0	69
T59	0	74
T60	0	51
T66	0	85
T67	0	63
T80	0	51
T81	0	71

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	6884	0	0
SrcPulseCheck_M	1396952907	6949	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	6884
T3	17023	69
T7	27126	0
T8	33137	0
T9	0	63
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T51	711	0
T52	0	75
T59	0	62
T60	0	59
T66	0	58
T67	0	87
T80	0	51
T81	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	6949
T3	204269	69
T7	126134	0
T8	811888	0
T9	0	63
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T51	106742	0
T52	0	75
T59	0	62
T60	0	59
T66	0	58
T67	0	87
T80	0	51
T81	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	6941	0	0
SrcPulseCheck_M	9375037	6941	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	6941
T3	204269	69
T7	126134	0
T8	811888	0
T9	0	63
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T51	106742	0
T52	0	75
T59	0	62
T60	0	59
T66	0	58
T67	0	87
T80	0	51
T81	0	75

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	6941
T3	17023	69
T7	27126	0
T8	33137	0
T9	0	63
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T51	711	0
T52	0	75
T59	0	62
T60	0	59
T66	0	58
T67	0	87
T80	0	51
T81	0	75

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	6813	0	0
SrcPulseCheck_M	1396952907	6878	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	6813
T3	17023	94
T7	27126	0
T8	33137	0
T9	0	76
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T51	711	0
T52	0	70
T59	0	70
T60	0	51
T66	0	85
T67	0	69
T80	0	51
T81	0	63

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	6878
T3	204269	94
T7	126134	0
T8	811888	0
T9	0	76
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T51	106742	0
T52	0	70
T59	0	70
T60	0	51
T66	0	85
T67	0	69
T80	0	51
T81	0	63

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	6869	0	0
SrcPulseCheck_M	9375037	6869	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	6869
T3	204269	94
T7	126134	0
T8	811888	0
T9	0	76
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T51	106742	0
T52	0	70
T59	0	70
T60	0	51
T66	0	85
T67	0	69
T80	0	51
T81	0	63

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	6869
T3	17023	94
T7	27126	0
T8	33137	0
T9	0	76
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T51	711	0
T52	0	70
T59	0	70
T60	0	51
T66	0	85
T67	0	69
T80	0	51
T81	0	63

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	7082	0	0
SrcPulseCheck_M	1396952907	7146	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	7082
T3	17023	80
T7	27126	0
T8	33137	0
T9	0	76
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T51	711	0
T52	0	56
T59	0	73
T60	0	70
T66	0	85
T67	0	89
T80	0	51
T81	0	89

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	7146
T3	204269	80
T7	126134	0
T8	811888	0
T9	0	76
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T51	106742	0
T52	0	56
T59	0	73
T60	0	70
T66	0	85
T67	0	89
T80	0	51
T81	0	89

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	7138	0	0
SrcPulseCheck_M	9375037	7138	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	7138
T3	204269	80
T7	126134	0
T8	811888	0
T9	0	76
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T51	106742	0
T52	0	56
T59	0	73
T60	0	70
T66	0	85
T67	0	89
T80	0	51
T81	0	89

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	7138
T3	17023	80
T7	27126	0
T8	33137	0
T9	0	76
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T51	711	0
T52	0	56
T59	0	73
T60	0	70
T66	0	85
T67	0	89
T80	0	51
T81	0	89

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T91,T92,T47
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1312	0	0
SrcPulseCheck_M	1396952907	1375	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1312
T3	17023	5
T7	27126	0
T8	33137	0
T9	0	3
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T51	711	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1375
T3	204269	5
T7	126134	0
T8	811888	0
T9	0	3
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T51	106742	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T91,T92,T47
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1366	0	0
SrcPulseCheck_M	9375037	1366	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1366
T3	204269	5
T7	126134	0
T8	811888	0
T9	0	3
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T51	106742	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1366
T3	17023	5
T7	27126	0
T8	33137	0
T9	0	3
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T51	711	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T91,T92,T47
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1336	0	0
SrcPulseCheck_M	1396952907	1403	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1336
T3	17023	5
T7	27126	0
T8	33137	0
T9	0	3
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T51	711	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1403
T3	204269	5
T7	126134	0
T8	811888	0
T9	0	3
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T51	106742	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T91,T92,T47
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1394	0	0
SrcPulseCheck_M	9375037	1394	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1394
T3	204269	5
T7	126134	0
T8	811888	0
T9	0	3
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T51	106742	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1394
T3	17023	5
T7	27126	0
T8	33137	0
T9	0	3
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T51	711	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T91,T92,T47
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1262	0	0
SrcPulseCheck_M	1396952907	1325	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1262
T3	17023	5
T7	27126	0
T8	33137	0
T9	0	3
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T51	711	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1325
T3	204269	5
T7	126134	0
T8	811888	0
T9	0	3
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T51	106742	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T91,T92,T47
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1316	0	0
SrcPulseCheck_M	9375037	1316	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1316
T3	204269	5
T7	126134	0
T8	811888	0
T9	0	3
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T51	106742	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1316
T3	17023	5
T7	27126	0
T8	33137	0
T9	0	3
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T51	711	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T91,T92,T47
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1261	0	0
SrcPulseCheck_M	1396952907	1328	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1261
T3	17023	5
T7	27126	0
T8	33137	0
T9	0	3
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T51	711	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1328
T3	204269	5
T7	126134	0
T8	811888	0
T9	0	3
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T51	106742	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T3,T9,T52
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T3,T9,T52
1	0	Covered	T91,T92,T47
1	1	Covered	T3,T9,T52

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1319	0	0
SrcPulseCheck_M	9375037	1319	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1319
T3	204269	5
T7	126134	0
T8	811888	0
T9	0	3
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T51	106742	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1319
T3	17023	5
T7	27126	0
T8	33137	0
T9	0	3
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T51	711	0
T52	0	1
T59	0	1
T60	0	1
T66	0	8
T67	0	2
T80	0	1
T81	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T9,T52
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	7666	0	0
SrcPulseCheck_M	1396952907	7729	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	7666
T2	27744	11
T3	17023	68
T7	27126	11
T8	0	14
T9	0	60
T10	0	3
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T52	0	69
T59	0	74

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	7729
T2	105427	11
T3	204269	68
T7	126134	11
T8	0	14
T9	0	60
T10	0	3
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T52	0	69
T59	0	74

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T9,T52
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	7720	0	0
SrcPulseCheck_M	9375037	7720	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	7720
T2	105427	11
T3	204269	68
T7	126134	11
T8	0	14
T9	0	60
T10	0	3
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T52	0	69
T59	0	74

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	7720
T2	27744	11
T3	17023	68
T7	27126	11
T8	0	14
T9	0	60
T10	0	3
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T52	0	69
T59	0	74

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T9,T52
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	7426	0	0
SrcPulseCheck_M	1396952907	7492	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	7426
T2	27744	11
T3	17023	69
T7	27126	11
T8	0	14
T9	0	63
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T52	0	75
T59	0	62

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	7492
T2	105427	11
T3	204269	69
T7	126134	11
T8	0	14
T9	0	63
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T52	0	75
T59	0	62

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T9,T52
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	7482	0	0
SrcPulseCheck_M	9375037	7482	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	7482
T2	105427	11
T3	204269	69
T7	126134	11
T8	0	14
T9	0	63
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T52	0	75
T59	0	62

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	7482
T2	27744	11
T3	17023	69
T7	27126	11
T8	0	14
T9	0	63
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T52	0	75
T59	0	62

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T9,T52
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	7383	0	0
SrcPulseCheck_M	1396952907	7448	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	7383
T2	27744	11
T3	17023	94
T7	27126	11
T8	0	14
T9	0	76
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T52	0	70
T59	0	70

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	7448
T2	105427	11
T3	204269	94
T7	126134	11
T8	0	14
T9	0	76
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T52	0	70
T59	0	70

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T9,T52
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	7438	0	0
SrcPulseCheck_M	9375037	7438	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	7438
T2	105427	11
T3	204269	94
T7	126134	11
T8	0	14
T9	0	76
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T52	0	70
T59	0	70

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	7438
T2	27744	11
T3	17023	94
T7	27126	11
T8	0	14
T9	0	76
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T52	0	70
T59	0	70

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T9,T52
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	7624	0	0
SrcPulseCheck_M	1396952907	7689	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	7624
T2	27744	11
T3	17023	80
T7	27126	11
T8	0	14
T9	0	76
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T52	0	56
T59	0	73

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	7689
T2	105427	11
T3	204269	80
T7	126134	11
T8	0	14
T9	0	76
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T52	0	56
T59	0	73

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T3,T9,T52

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T3,T9,T52
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	7681	0	0
SrcPulseCheck_M	9375037	7681	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	7681
T2	105427	11
T3	204269	80
T7	126134	11
T8	0	14
T9	0	76
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	51
T52	0	56
T59	0	73

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	7681
T2	27744	11
T3	17023	80
T7	27126	11
T8	0	14
T9	0	76
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	51
T52	0	56
T59	0	73

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1918	0	0
SrcPulseCheck_M	1396952907	1980	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1918
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	3
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1980
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	3
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1971	0	0
SrcPulseCheck_M	9375037	1971	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1971
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	3
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1971
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	3
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1829	0	0
SrcPulseCheck_M	1396952907	1892	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1829
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1892
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1883	0	0
SrcPulseCheck_M	9375037	1883	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1883
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1883
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1836	0	0
SrcPulseCheck_M	1396952907	1900	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1836
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1900
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1891	0	0
SrcPulseCheck_M	9375037	1891	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1891
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1891
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1834	0	0
SrcPulseCheck_M	1396952907	1896	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1834
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1896
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1887	0	0
SrcPulseCheck_M	9375037	1887	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1887
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1887
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1922	0	0
SrcPulseCheck_M	1396952907	1986	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1922
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	3
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1986
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	3
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1977	0	0
SrcPulseCheck_M	9375037	1977	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1977
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	3
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1977
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	3
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1875	0	0
SrcPulseCheck_M	1396952907	1940	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1875
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1940
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1931	0	0
SrcPulseCheck_M	9375037	1931	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1931
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1931
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1853	0	0
SrcPulseCheck_M	1396952907	1916	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1853
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1916
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1907	0	0
SrcPulseCheck_M	9375037	1907	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1907
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1907
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1852	0	0
SrcPulseCheck_M	1396952907	1915	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1852
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1915
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T91,T92,T47

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T91,T92,T47
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1396952907	1906	0	0
SrcPulseCheck_M	9375037	1906	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1396952907	1906
T2	105427	11
T3	204269	5
T7	126134	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0
T33	0	1
T52	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	9375037	1906
T2	27744	11
T3	17023	5
T7	27126	11
T8	0	14
T9	0	3
T10	0	2
T13	0	6
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0
T33	0	1
T52	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T7
1	1	Covered	T60,T111,T242

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T2,T3,T7
1	0	Covered	T60,T111,T242
1	1	Covered	T2,T3,T7

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	1149	0	0
SrcPulseCheck_M	1396952907	1215	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	1149
T2	27744	2
T3	17023	4
T7	27126	9
T8	0	13
T9	0	3
T10	0	1
T13	0	5
T16	0	8
T18	0	9
T19	0	1
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0
T31	451	0
T32	450	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	1215
T2	105427	2
T3	204269	4
T7	126134	9
T8	0	13
T9	0	3
T10	0	1
T13	0	5
T16	0	8
T18	0	9
T19	0	1
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0
T31	29347	0
T32	220764	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T10,T12
1	1	Covered	T1,T10,T12

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9375037	706	0	0
SrcPulseCheck_M	1396952907	770	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	9375037	706
T1	215137	2
T2	27744	0
T3	17023	0
T7	27126	0
T10	0	3
T12	0	2
T14	0	2
T17	0	3
T20	0	2
T21	0	2
T22	0	3
T23	0	2
T24	0	2
T25	492	0
T26	507	0
T27	405	0
T28	768	0
T29	547	0
T30	663	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1396952907	770
T1	101295	2
T2	105427	0
T3	204269	0
T7	126134	0
T10	0	3
T12	0	2
T14	0	2
T17	0	3
T20	0	2
T21	0	2
T22	0	3
T23	0	2
T24	0	2
T25	199495	0
T26	63405	0
T27	56848	0
T28	92232	0
T29	21870	0
T30	50159	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc