Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T42,T2
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T42

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T2
1	0	Covered	T4,T42,T2
1	1	Covered	T4,T5,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T42
0	1	Covered	T4,T2,T28
1	0	Covered	T4,T2,T28

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T42,T7
0	1	Covered	T42,T7,T13
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T42,T7
1	-	Covered	T42,T7,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T5,T42
DetectSt	168	Covered	T4,T5,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T42,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T5,T42
DebounceSt->IdleSt	163	Covered	T84,T234,T235
DetectSt->IdleSt	186	Covered	T4,T2,T28
DetectSt->StableSt	191	Covered	T5,T42,T7
IdleSt->DebounceSt	148	Covered	T4,T5,T42
StableSt->IdleSt	206	Covered	T42,T7,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T42
0	1	Covered	T4,T5,T42
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T5,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T42,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T5,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T234,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T5,T42
DetectSt	-	-	-	-	1	-	-	Covered	T4,T2,T28
DetectSt	-	-	-	-	0	1	-	Covered	T5,T42,T7
DetectSt	-	-	-	-	0	0	-	Covered	T4,T5,T42
StableSt	-	-	-	-	-	-	1	Covered	T42,T7,T13
StableSt	-	-	-	-	-	-	0	Covered	T5,T42,T7
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	3301	0	0
CntIncr_A	5957637	123199	0	0
CntNoWrap_A	5957637	5335698	0	0
DetectStDropOut_A	5957637	326	0	0
DetectedOut_A	5957637	112467	0	0
DetectedPulseOut_A	5957637	1075	0	0
DisabledIdleSt_A	5957637	4823315	0	0
DisabledNoDetection_A	5957637	4825361	0	0
EnterDebounceSt_A	5957637	1665	0	0
EnterDetectSt_A	5957637	1638	0	0
EnterStableSt_A	5957637	1075	0	0
PulseIsPulse_A	5957637	1075	0	0
StayInStableSt	5957637	111234	0	0
gen_high_event_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	917	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	3301	0	0
T1	17765	0	0	0
T2	0	54	0	0
T4	5919	48	0	0
T5	460	2	0	0
T6	1976	0	0	0
T7	0	46	0	0
T11	0	22	0	0
T13	0	44	0	0
T25	24867	0	0	0
T28	0	18	0	0
T32	0	16	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	28	0	0
T43	402	0	0	0
T75	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	123199	0	0
T1	17765	0	0	0
T2	0	1950	0	0
T4	5919	1049	0	0
T5	460	21	0	0
T6	1976	0	0	0
T7	0	1196	0	0
T11	0	3398	0	0
T13	0	1628	0	0
T25	24867	0	0	0
T28	0	618	0	0
T32	0	393	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	924	0	0
T43	402	0	0	0
T75	0	2015	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5335698	0	0
T1	17765	17322	0	0
T4	5919	5470	0	0
T5	460	57	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11470	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	326	0	0
T1	17765	0	0	0
T2	0	18	0	0
T4	5919	13	0	0
T5	460	0	0	0
T6	1976	0	0	0
T11	0	2	0	0
T25	24867	0	0	0
T28	0	2	0	0
T32	0	8	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	0	0	0
T43	402	0	0	0
T75	0	28	0	0
T93	0	13	0	0
T217	0	7	0	0
T236	0	23	0	0
T237	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	112467	0	0
T1	17765	0	0	0
T5	460	35	0	0
T6	1976	0	0	0
T7	0	2790	0	0
T13	0	2123	0	0
T18	0	866	0	0
T25	24867	0	0	0
T26	440	0	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	1065	0	0
T43	402	0	0	0
T86	0	726	0	0
T93	0	2	0	0
T214	0	409	0	0
T238	0	80	0	0
T239	0	2096	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1075	0	0
T1	17765	0	0	0
T5	460	1	0	0
T6	1976	0	0	0
T7	0	23	0	0
T13	0	22	0	0
T18	0	13	0	0
T25	24867	0	0	0
T26	440	0	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	14	0	0
T43	402	0	0	0
T86	0	6	0	0
T93	0	2	0	0
T214	0	16	0	0
T238	0	1	0	0
T239	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4823315	0	0
T1	17765	17322	0	0
T4	5919	3164	0	0
T5	460	3	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	6771	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4825361	0	0
T1	17765	17328	0	0
T4	5919	3164	0	0
T5	460	3	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	6773	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1665	0	0
T1	17765	0	0	0
T2	0	27	0	0
T4	5919	24	0	0
T5	460	1	0	0
T6	1976	0	0	0
T7	0	23	0	0
T11	0	11	0	0
T13	0	22	0	0
T25	24867	0	0	0
T28	0	9	0	0
T32	0	8	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	14	0	0
T43	402	0	0	0
T75	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1638	0	0
T1	17765	0	0	0
T2	0	27	0	0
T4	5919	24	0	0
T5	460	1	0	0
T6	1976	0	0	0
T7	0	23	0	0
T11	0	11	0	0
T13	0	22	0	0
T25	24867	0	0	0
T28	0	9	0	0
T32	0	8	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	14	0	0
T43	402	0	0	0
T75	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1075	0	0
T1	17765	0	0	0
T5	460	1	0	0
T6	1976	0	0	0
T7	0	23	0	0
T13	0	22	0	0
T18	0	13	0	0
T25	24867	0	0	0
T26	440	0	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	14	0	0
T43	402	0	0	0
T86	0	6	0	0
T93	0	2	0	0
T214	0	16	0	0
T238	0	1	0	0
T239	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1075	0	0
T1	17765	0	0	0
T5	460	1	0	0
T6	1976	0	0	0
T7	0	23	0	0
T13	0	22	0	0
T18	0	13	0	0
T25	24867	0	0	0
T26	440	0	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	14	0	0
T43	402	0	0	0
T86	0	6	0	0
T93	0	2	0	0
T214	0	16	0	0
T238	0	1	0	0
T239	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	111234	0	0
T1	17765	0	0	0
T5	460	33	0	0
T6	1976	0	0	0
T7	0	2755	0	0
T13	0	2096	0	0
T18	0	852	0	0
T25	24867	0	0	0
T26	440	0	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	1051	0	0
T43	402	0	0	0
T86	0	718	0	0
T214	0	393	0	0
T238	0	78	0	0
T239	0	2062	0	0
T240	0	1989	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	917	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	11	0	0
T8	580	0	0	0
T13	0	17	0	0
T18	0	12	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	14	0	0
T43	402	0	0	0
T86	0	4	0	0
T93	0	2	0	0
T214	0	16	0	0
T228	0	24	0	0
T239	0	20	0	0
T240	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T5,T6,T42

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T1,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T42
1	0	Covered	T4,T6,T40
1	1	Covered	T5,T6,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T1,T25
0	1	Covered	T82,T94,T95
1	0	Covered	T84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T1,T25
0	1	Covered	T42,T1,T25
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T1,T25
1	-	Covered	T42,T1,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T6,T42
DetectSt	168	Covered	T42,T1,T25
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T42,T1,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T1,T25
DebounceSt->IdleSt	163	Covered	T5,T6,T13
DetectSt->IdleSt	186	Covered	T82,T94,T95
DetectSt->StableSt	191	Covered	T42,T1,T25
IdleSt->DebounceSt	148	Covered	T5,T6,T42
StableSt->IdleSt	206	Covered	T42,T1,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T6,T42
0	1	Covered	T5,T6,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T1,T25
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T6,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T1,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T6,T13
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T6,T42
DetectSt	-	-	-	-	1	-	-	Covered	T82,T94,T95
DetectSt	-	-	-	-	0	1	-	Covered	T42,T1,T25
DetectSt	-	-	-	-	0	0	-	Covered	T42,T1,T25
StableSt	-	-	-	-	-	-	1	Covered	T42,T1,T25
StableSt	-	-	-	-	-	-	0	Covered	T42,T1,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	947	0	0
CntIncr_A	5957637	45884	0	0
CntNoWrap_A	5957637	5338052	0	0
DetectStDropOut_A	5957637	33	0	0
DetectedOut_A	5957637	20345	0	0
DetectedPulseOut_A	5957637	405	0	0
DisabledIdleSt_A	5957637	4938465	0	0
DisabledNoDetection_A	5957637	4940021	0	0
EnterDebounceSt_A	5957637	506	0	0
EnterDetectSt_A	5957637	442	0	0
EnterStableSt_A	5957637	405	0	0
PulseIsPulse_A	5957637	405	0	0
StayInStableSt	5957637	19890	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	353	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	947	0	0
T1	17765	4	0	0
T5	460	1	0	0
T6	1976	1	0	0
T7	0	24	0	0
T13	0	11	0	0
T14	0	2	0	0
T15	0	5	0	0
T18	0	2	0	0
T25	24867	4	0	0
T26	440	0	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	4	0	0
T43	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	45884	0	0
T1	17765	250	0	0
T5	460	20	0	0
T6	1976	20	0	0
T7	0	648	0	0
T13	0	445	0	0
T14	0	25	0	0
T15	0	70	0	0
T18	0	49	0	0
T25	24867	206	0	0
T26	440	0	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	156	0	0
T43	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338052	0	0
T1	17765	17318	0	0
T4	5919	5518	0	0
T5	460	58	0	0
T6	1976	372	0	0
T25	24867	24398	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11494	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	33	0	0
T19	16760	0	0	0
T66	494	0	0	0
T67	496	0	0	0
T68	499	0	0	0
T82	13940	2	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	5	0	0
T97	0	9	0	0
T98	0	5	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	0	4	0	0
T103	0	3	0	0
T105	623	0	0	0
T106	866	0	0	0
T107	694	0	0	0
T108	504	0	0	0
T109	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	20345	0	0
T1	17765	170	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	710	0	0
T8	580	0	0	0
T13	0	258	0	0
T14	0	3	0	0
T15	0	7	0	0
T18	0	55	0	0
T19	0	53	0	0
T25	24867	70	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	116	0	0
T43	402	0	0	0
T110	0	86	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	405	0	0
T1	17765	2	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	12	0	0
T8	580	0	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T25	24867	2	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	2	0	0
T43	402	0	0	0
T110	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4938465	0	0
T1	17765	12086	0	0
T4	5919	5518	0	0
T5	460	25	0	0
T6	1976	339	0	0
T25	24867	20145	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	10433	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4940021	0	0
T1	17765	12086	0	0
T4	5919	5519	0	0
T5	460	25	0	0
T6	1976	341	0	0
T25	24867	20145	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	10436	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	506	0	0
T1	17765	2	0	0
T5	460	1	0	0
T6	1976	1	0	0
T7	0	12	0	0
T13	0	6	0	0
T14	0	1	0	0
T15	0	3	0	0
T18	0	1	0	0
T25	24867	2	0	0
T26	440	0	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	2	0	0
T43	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	442	0	0
T1	17765	2	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	12	0	0
T8	580	0	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T25	24867	2	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	2	0	0
T43	402	0	0	0
T82	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	405	0	0
T1	17765	2	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	12	0	0
T8	580	0	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T25	24867	2	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	2	0	0
T43	402	0	0	0
T110	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	405	0	0
T1	17765	2	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	12	0	0
T8	580	0	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T25	24867	2	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	2	0	0
T43	402	0	0	0
T110	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	19890	0	0
T1	17765	168	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	698	0	0
T8	580	0	0	0
T13	0	253	0	0
T14	0	2	0	0
T15	0	5	0	0
T18	0	54	0	0
T19	0	51	0	0
T25	24867	68	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	114	0	0
T43	402	0	0	0
T110	0	84	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	353	0	0
T1	17765	2	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	12	0	0
T8	580	0	0	0
T13	0	5	0	0
T14	0	1	0	0
T15	0	2	0	0
T18	0	1	0	0
T19	0	2	0	0
T25	24867	2	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	1	0	0
T43	402	0	0	0
T110	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T42,T2
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T42,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T42,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T42,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T2
1	0	Covered	T4,T42,T2
1	1	Covered	T4,T42,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T42,T2
0	1	Covered	T7,T32,T75
1	0	Covered	T4,T2,T7

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T28,T11
0	1	Covered	T42,T28,T11
1	0	Covered	T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T28,T11
1	-	Covered	T42,T28,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T42,T2
DetectSt	168	Covered	T4,T42,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T42,T28,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T42,T2
DebounceSt->IdleSt	163	Covered	T84,T234,T235
DetectSt->IdleSt	186	Covered	T4,T2,T7
DetectSt->StableSt	191	Covered	T42,T28,T11
IdleSt->DebounceSt	148	Covered	T4,T42,T2
StableSt->IdleSt	206	Covered	T42,T28,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T42,T2
0	1	Covered	T4,T42,T2
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T42,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T42,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T42,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T42,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T234,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T42,T2
DetectSt	-	-	-	-	1	-	-	Covered	T4,T2,T7
DetectSt	-	-	-	-	0	1	-	Covered	T42,T28,T11
DetectSt	-	-	-	-	0	0	-	Covered	T4,T42,T2
StableSt	-	-	-	-	-	-	1	Covered	T42,T28,T11
StableSt	-	-	-	-	-	-	0	Covered	T42,T28,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	2964	0	0
CntIncr_A	5957637	104503	0	0
CntNoWrap_A	5957637	5336035	0	0
DetectStDropOut_A	5957637	413	0	0
DetectedOut_A	5957637	82259	0	0
DetectedPulseOut_A	5957637	862	0	0
DisabledIdleSt_A	5957637	4849516	0	0
DisabledNoDetection_A	5957637	4851600	0	0
EnterDebounceSt_A	5957637	1494	0	0
EnterDetectSt_A	5957637	1473	0	0
EnterStableSt_A	5957637	862	0	0
PulseIsPulse_A	5957637	862	0	0
StayInStableSt	5957637	81277	0	0
gen_high_event_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	741	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	2964	0	0
T1	17765	0	0	0
T2	0	12	0	0
T4	5919	18	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	30	0	0
T11	0	28	0	0
T13	0	44	0	0
T18	0	62	0	0
T25	24867	0	0	0
T28	0	24	0	0
T32	0	10	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	24	0	0
T43	402	0	0	0
T75	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	104503	0	0
T1	17765	0	0	0
T2	0	437	0	0
T4	5919	394	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	841	0	0
T11	0	2926	0	0
T13	0	1342	0	0
T18	0	1767	0	0
T25	24867	0	0	0
T28	0	816	0	0
T32	0	246	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	672	0	0
T43	402	0	0	0
T75	0	1947	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5336035	0	0
T1	17765	17322	0	0
T4	5919	5500	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11474	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	413	0	0
T7	32416	8	0	0
T8	580	0	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	0	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T31	406	0	0	0
T32	5122	5	0	0
T75	0	27	0	0
T86	0	8	0	0
T93	0	25	0	0
T218	0	22	0	0
T236	0	5	0	0
T237	0	17	0	0
T241	0	21	0	0
T242	0	29	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	82259	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	6700	0	0
T13	0	2409	0	0
T18	0	2814	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	1783	0	0
T42	11915	882	0	0
T43	402	0	0	0
T52	0	2679	0	0
T86	0	1	0	0
T125	0	846	0	0
T214	0	2322	0	0
T239	0	580	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	862	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	14	0	0
T13	0	22	0	0
T18	0	31	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	12	0	0
T42	11915	12	0	0
T43	402	0	0	0
T52	0	24	0	0
T86	0	1	0	0
T125	0	14	0	0
T214	0	13	0	0
T239	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4849516	0	0
T1	17765	17322	0	0
T4	5919	3164	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	7061	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4851600	0	0
T1	17765	17328	0	0
T4	5919	3164	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	7061	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1494	0	0
T1	17765	0	0	0
T2	0	6	0	0
T4	5919	9	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	15	0	0
T11	0	14	0	0
T13	0	22	0	0
T18	0	31	0	0
T25	24867	0	0	0
T28	0	12	0	0
T32	0	5	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	12	0	0
T43	402	0	0	0
T75	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1473	0	0
T1	17765	0	0	0
T2	0	6	0	0
T4	5919	9	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	15	0	0
T11	0	14	0	0
T13	0	22	0	0
T18	0	31	0	0
T25	24867	0	0	0
T28	0	12	0	0
T32	0	5	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	12	0	0
T43	402	0	0	0
T75	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	862	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	14	0	0
T13	0	22	0	0
T18	0	31	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	12	0	0
T42	11915	12	0	0
T43	402	0	0	0
T52	0	24	0	0
T86	0	1	0	0
T125	0	14	0	0
T214	0	13	0	0
T239	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	862	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	14	0	0
T13	0	22	0	0
T18	0	31	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	12	0	0
T42	11915	12	0	0
T43	402	0	0	0
T52	0	24	0	0
T86	0	1	0	0
T125	0	14	0	0
T214	0	13	0	0
T239	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	81277	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	6677	0	0
T13	0	2382	0	0
T18	0	2782	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	1769	0	0
T42	11915	868	0	0
T43	402	0	0	0
T52	0	2651	0	0
T125	0	830	0	0
T214	0	2308	0	0
T239	0	570	0	0
T240	0	822	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	741	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	5	0	0
T13	0	17	0	0
T18	0	30	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	10	0	0
T42	11915	10	0	0
T43	402	0	0	0
T52	0	20	0	0
T125	0	12	0	0
T214	0	12	0	0
T239	0	6	0	0
T240	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T42,T25
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T25,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T42,T25,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T25,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T25,T28
1	0	Covered	T4,T6,T40
1	1	Covered	T42,T25,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T25,T28
0	1	Covered	T83,T243,T88
1	0	Covered	T84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T25,T28
0	1	Covered	T25,T11,T13
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T25,T28
1	-	Covered	T25,T11,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T42,T25,T28
DetectSt	168	Covered	T42,T25,T28
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T42,T25,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T25,T28
DebounceSt->IdleSt	163	Covered	T42,T25,T19
DetectSt->IdleSt	186	Covered	T83,T38,T243
DetectSt->StableSt	191	Covered	T42,T25,T28
IdleSt->DebounceSt	148	Covered	T42,T25,T28
StableSt->IdleSt	206	Covered	T42,T25,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T25,T28
0	1	Covered	T42,T25,T28
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T25,T28
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T25,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T25,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T25,T19
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T25,T28
DetectSt	-	-	-	-	1	-	-	Covered	T83,T243,T88
DetectSt	-	-	-	-	0	1	-	Covered	T42,T25,T28
DetectSt	-	-	-	-	0	0	-	Covered	T42,T25,T28
StableSt	-	-	-	-	-	-	1	Covered	T25,T11,T13
StableSt	-	-	-	-	-	-	0	Covered	T42,T25,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	856	0	0
CntIncr_A	5957637	49511	0	0
CntNoWrap_A	5957637	5338143	0	0
DetectStDropOut_A	5957637	57	0	0
DetectedOut_A	5957637	16417	0	0
DetectedPulseOut_A	5957637	345	0	0
DisabledIdleSt_A	5957637	4986227	0	0
DisabledNoDetection_A	5957637	4987900	0	0
EnterDebounceSt_A	5957637	451	0	0
EnterDetectSt_A	5957637	407	0	0
EnterStableSt_A	5957637	345	0	0
PulseIsPulse_A	5957637	345	0	0
StayInStableSt	5957637	16044	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	315	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	856	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	12	0	0
T13	0	10	0	0
T18	0	6	0	0
T19	0	27	0	0
T20	0	7	0	0
T25	24867	19	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	4	0	0
T42	11915	3	0	0
T43	402	0	0	0
T82	0	2	0	0
T110	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	49511	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	1380	0	0
T13	0	365	0	0
T18	0	99	0	0
T19	0	1903	0	0
T20	0	438	0	0
T25	24867	769	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	146	0	0
T42	11915	94	0	0
T43	402	0	0	0
T82	0	110	0	0
T110	0	833	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338143	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24383	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11495	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	57	0	0
T34	9620	0	0	0
T35	1461	0	0	0
T70	492	0	0	0
T83	27038	4	0	0
T85	0	1	0	0
T88	0	2	0	0
T96	0	9	0	0
T120	443	0	0	0
T121	504	0	0	0
T122	422	0	0	0
T123	525	0	0	0
T124	463	0	0	0
T125	12493	0	0	0
T243	0	8	0	0
T244	0	2	0	0
T245	0	13	0	0
T246	0	6	0	0
T247	0	2	0	0
T248	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	16417	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	434	0	0
T13	0	300	0	0
T18	0	216	0	0
T19	0	264	0	0
T20	0	61	0	0
T25	24867	553	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	138	0	0
T42	11915	71	0	0
T43	402	0	0	0
T82	0	24	0	0
T110	0	556	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	345	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	6	0	0
T13	0	5	0	0
T18	0	3	0	0
T19	0	13	0	0
T20	0	3	0	0
T25	24867	9	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	2	0	0
T42	11915	1	0	0
T43	402	0	0	0
T82	0	1	0	0
T110	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4986227	0	0
T1	17765	17322	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	20145	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	10618	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4987900	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	20145	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	10619	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	451	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	6	0	0
T13	0	5	0	0
T18	0	3	0	0
T19	0	14	0	0
T20	0	4	0	0
T25	24867	10	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	2	0	0
T42	11915	2	0	0
T43	402	0	0	0
T82	0	1	0	0
T110	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	407	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	6	0	0
T13	0	5	0	0
T18	0	3	0	0
T19	0	13	0	0
T20	0	3	0	0
T25	24867	9	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	2	0	0
T42	11915	1	0	0
T43	402	0	0	0
T82	0	1	0	0
T110	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	345	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	6	0	0
T13	0	5	0	0
T18	0	3	0	0
T19	0	13	0	0
T20	0	3	0	0
T25	24867	9	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	2	0	0
T42	11915	1	0	0
T43	402	0	0	0
T82	0	1	0	0
T110	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	345	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	6	0	0
T13	0	5	0	0
T18	0	3	0	0
T19	0	13	0	0
T20	0	3	0	0
T25	24867	9	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	2	0	0
T42	11915	1	0	0
T43	402	0	0	0
T82	0	1	0	0
T110	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	16044	0	0
T1	17765	0	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	424	0	0
T13	0	295	0	0
T18	0	213	0	0
T19	0	251	0	0
T20	0	58	0	0
T25	24867	544	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	0	134	0	0
T42	11915	69	0	0
T43	402	0	0	0
T82	0	23	0	0
T110	0	549	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	315	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	0	2	0	0
T13	0	5	0	0
T18	0	3	0	0
T19	0	13	0	0
T20	0	3	0	0
T25	24867	9	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	1	0	0
T82	0	1	0	0
T110	0	7	0	0
T149	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T42,T2
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T42,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T42,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T42,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T2
1	0	Covered	T4,T42,T7
1	1	Covered	T4,T42,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T42,T2
0	1	Covered	T4,T28,T32
1	0	Covered	T4,T7,T28

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T2,T11
0	1	Covered	T42,T2,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T2,T11
1	-	Covered	T42,T2,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T42,T2
DetectSt	168	Covered	T4,T42,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T42,T2,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T42,T2
DebounceSt->IdleSt	163	Covered	T84,T234,T235
DetectSt->IdleSt	186	Covered	T4,T7,T28
DetectSt->StableSt	191	Covered	T42,T2,T11
IdleSt->DebounceSt	148	Covered	T4,T42,T2
StableSt->IdleSt	206	Covered	T42,T2,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T42,T2
0	1	Covered	T4,T42,T2
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T42,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T42,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T42,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T42,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T234,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T42,T2
DetectSt	-	-	-	-	1	-	-	Covered	T4,T7,T28
DetectSt	-	-	-	-	0	1	-	Covered	T42,T2,T11
DetectSt	-	-	-	-	0	0	-	Covered	T4,T42,T2
StableSt	-	-	-	-	-	-	1	Covered	T42,T2,T11
StableSt	-	-	-	-	-	-	0	Covered	T42,T2,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	3024	0	0
CntIncr_A	5957637	101833	0	0
CntNoWrap_A	5957637	5335975	0	0
DetectStDropOut_A	5957637	378	0	0
DetectedOut_A	5957637	92885	0	0
DetectedPulseOut_A	5957637	971	0	0
DisabledIdleSt_A	5957637	4834745	0	0
DisabledNoDetection_A	5957637	4836797	0	0
EnterDebounceSt_A	5957637	1523	0	0
EnterDetectSt_A	5957637	1503	0	0
EnterStableSt_A	5957637	971	0	0
PulseIsPulse_A	5957637	971	0	0
StayInStableSt	5957637	91761	0	0
gen_high_event_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	818	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	3024	0	0
T1	17765	0	0	0
T2	0	30	0	0
T4	5919	50	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	22	0	0
T11	0	22	0	0
T13	0	42	0	0
T18	0	24	0	0
T25	24867	0	0	0
T28	0	26	0	0
T32	0	42	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	24	0	0
T43	402	0	0	0
T75	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	101833	0	0
T1	17765	0	0	0
T2	0	870	0	0
T4	5919	1090	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	623	0	0
T11	0	2607	0	0
T13	0	1512	0	0
T18	0	804	0	0
T25	24867	0	0	0
T28	0	886	0	0
T32	0	1050	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	600	0	0
T43	402	0	0	0
T75	0	499	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5335975	0	0
T1	17765	17322	0	0
T4	5919	5468	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11474	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	378	0	0
T1	17765	0	0	0
T4	5919	11	0	0
T5	460	0	0	0
T6	1976	0	0	0
T25	24867	0	0	0
T28	0	7	0	0
T32	0	21	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	0	0	0
T43	402	0	0	0
T75	0	7	0	0
T93	0	4	0	0
T236	0	14	0	0
T237	0	28	0	0
T239	0	9	0	0
T240	0	3	0	0
T249	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	92885	0	0
T1	17765	0	0	0
T2	7669	1648	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	4258	0	0
T13	0	1321	0	0
T18	0	731	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	954	0	0
T43	402	0	0	0
T52	0	956	0	0
T125	0	1342	0	0
T214	0	474	0	0
T217	0	672	0	0
T218	0	1606	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	971	0	0
T1	17765	0	0	0
T2	7669	15	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	11	0	0
T13	0	21	0	0
T18	0	12	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	12	0	0
T43	402	0	0	0
T52	0	13	0	0
T125	0	23	0	0
T214	0	11	0	0
T217	0	23	0	0
T218	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4834745	0	0
T1	17765	17322	0	0
T4	5919	3164	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	7061	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4836797	0	0
T1	17765	17328	0	0
T4	5919	3164	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	7061	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1523	0	0
T1	17765	0	0	0
T2	0	15	0	0
T4	5919	25	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	11	0	0
T11	0	11	0	0
T13	0	21	0	0
T18	0	12	0	0
T25	24867	0	0	0
T28	0	13	0	0
T32	0	21	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	12	0	0
T43	402	0	0	0
T75	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1503	0	0
T1	17765	0	0	0
T2	0	15	0	0
T4	5919	25	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	11	0	0
T11	0	11	0	0
T13	0	21	0	0
T18	0	12	0	0
T25	24867	0	0	0
T28	0	13	0	0
T32	0	21	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	12	0	0
T43	402	0	0	0
T75	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	971	0	0
T1	17765	0	0	0
T2	7669	15	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	11	0	0
T13	0	21	0	0
T18	0	12	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	12	0	0
T43	402	0	0	0
T52	0	13	0	0
T125	0	23	0	0
T214	0	11	0	0
T217	0	23	0	0
T218	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	971	0	0
T1	17765	0	0	0
T2	7669	15	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	11	0	0
T13	0	21	0	0
T18	0	12	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	12	0	0
T43	402	0	0	0
T52	0	13	0	0
T125	0	23	0	0
T214	0	11	0	0
T217	0	23	0	0
T218	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	91761	0	0
T1	17765	0	0	0
T2	7669	1633	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	4239	0	0
T13	0	1297	0	0
T18	0	718	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	940	0	0
T43	402	0	0	0
T52	0	942	0	0
T125	0	1316	0	0
T214	0	463	0	0
T217	0	648	0	0
T218	0	1596	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	818	0	0
T1	17765	0	0	0
T2	7669	15	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	3	0	0
T13	0	18	0	0
T18	0	11	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	10	0	0
T43	402	0	0	0
T52	0	12	0	0
T125	0	20	0	0
T214	0	11	0	0
T217	0	22	0	0
T218	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T42,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T42,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T1,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T1,T2
1	0	Covered	T4,T6,T40
1	1	Covered	T42,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T42,T1,T2
0	1	Covered	T19,T23,T78
1	0	Covered	T84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T42,T1,T2
0	1	Covered	T1,T2,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T42,T1,T2
1	-	Covered	T1,T2,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T42,T1,T2
DetectSt	168	Covered	T42,T1,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T42,T1,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T42,T1,T2
DebounceSt->IdleSt	163	Covered	T82,T149,T250
DetectSt->IdleSt	186	Covered	T19,T23,T78
DetectSt->StableSt	191	Covered	T42,T1,T2
IdleSt->DebounceSt	148	Covered	T42,T1,T2
StableSt->IdleSt	206	Covered	T42,T1,T2

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T42,T1,T2
0	1	Covered	T42,T1,T2
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T1,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T42,T1,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T42,T1,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T149,T250
DebounceSt	-	0	0	-	-	-	-	Covered	T42,T1,T2
DetectSt	-	-	-	-	1	-	-	Covered	T19,T23,T78
DetectSt	-	-	-	-	0	1	-	Covered	T42,T1,T2
DetectSt	-	-	-	-	0	0	-	Covered	T42,T1,T2
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T11
StableSt	-	-	-	-	-	-	0	Covered	T42,T1,T2
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	924	0	0
CntIncr_A	5957637	50877	0	0
CntNoWrap_A	5957637	5338075	0	0
DetectStDropOut_A	5957637	60	0	0
DetectedOut_A	5957637	21296	0	0
DetectedPulseOut_A	5957637	374	0	0
DisabledIdleSt_A	5957637	4967256	0	0
DisabledNoDetection_A	5957637	4968883	0	0
EnterDebounceSt_A	5957637	487	0	0
EnterDetectSt_A	5957637	438	0	0
EnterStableSt_A	5957637	374	0	0
PulseIsPulse_A	5957637	374	0	0
StayInStableSt	5957637	20891	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	339	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	924	0	0
T1	17765	8	0	0
T2	7669	8	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	14	0	0
T13	0	4	0	0
T18	0	2	0	0
T19	0	8	0	0
T20	0	4	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	4	0	0
T43	402	0	0	0
T82	0	9	0	0
T110	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	50877	0	0
T1	17765	572	0	0
T2	7669	336	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	1512	0	0
T13	0	134	0	0
T18	0	54	0	0
T19	0	635	0	0
T20	0	190	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	152	0	0
T43	402	0	0	0
T82	0	606	0	0
T110	0	870	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338075	0	0
T1	17765	17314	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11494	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	60	0	0
T19	16760	4	0	0
T20	21299	0	0	0
T23	0	3	0	0
T67	496	0	0	0
T68	499	0	0	0
T69	2415	0	0	0
T78	0	2	0	0
T81	0	2	0	0
T97	0	13	0	0
T107	694	0	0	0
T108	504	0	0	0
T109	422	0	0	0
T110	17716	0	0	0
T127	0	1	0	0
T131	404	0	0	0
T245	0	3	0	0
T247	0	3	0	0
T251	0	4	0	0
T252	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	21296	0	0
T1	17765	266	0	0
T2	7669	197	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	614	0	0
T13	0	132	0	0
T18	0	50	0	0
T20	0	85	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	118	0	0
T43	402	0	0	0
T82	0	30	0	0
T110	0	122	0	0
T149	0	831	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	374	0	0
T1	17765	4	0	0
T2	7669	4	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	7	0	0
T13	0	2	0	0
T18	0	1	0	0
T20	0	2	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	2	0	0
T43	402	0	0	0
T82	0	4	0	0
T110	0	5	0	0
T149	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4967256	0	0
T1	17765	12086	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	10546	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4968883	0	0
T1	17765	12086	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	10547	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	487	0	0
T1	17765	4	0	0
T2	7669	4	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	7	0	0
T13	0	2	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	2	0	0
T43	402	0	0	0
T82	0	5	0	0
T110	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	438	0	0
T1	17765	4	0	0
T2	7669	4	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	7	0	0
T13	0	2	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	2	0	0
T43	402	0	0	0
T82	0	4	0	0
T110	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	374	0	0
T1	17765	4	0	0
T2	7669	4	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	7	0	0
T13	0	2	0	0
T18	0	1	0	0
T20	0	2	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	2	0	0
T43	402	0	0	0
T82	0	4	0	0
T110	0	5	0	0
T149	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	374	0	0
T1	17765	4	0	0
T2	7669	4	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	7	0	0
T13	0	2	0	0
T18	0	1	0	0
T20	0	2	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	2	0	0
T43	402	0	0	0
T82	0	4	0	0
T110	0	5	0	0
T149	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	20891	0	0
T1	17765	262	0	0
T2	7669	193	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T11	0	607	0	0
T13	0	130	0	0
T18	0	49	0	0
T20	0	83	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T42	11915	114	0	0
T43	402	0	0	0
T82	0	26	0	0
T110	0	117	0	0
T149	0	819	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	339	0	0
T1	17765	4	0	0
T2	7669	4	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T11	0	7	0	0
T13	0	2	0	0
T18	0	1	0	0
T20	0	2	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	1	0	0
T82	0	4	0	0
T110	0	5	0	0
T149	0	12	0	0