Unified Coverage Report :: Module :: sysrst_ctrl_combo

Module : sysrst_ctrl_combo

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	92.31

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_combo	96.15	100.00	92.31

---

Module Instance : tb.dut.u_sysrst_ctrl_combo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	92.31

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.01	100.00	97.07		100.00	98.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_combo_trigger[0].u_combo_act	99.19	100.00	97.56			100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
gen_combo_trigger[1].u_combo_act	99.19	100.00	97.56			100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
gen_combo_trigger[2].u_combo_act	99.19	100.00	97.56			100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
gen_combo_trigger[3].u_combo_act	99.19	100.00	97.56			100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_combo

	Line No.	Total	Covered	Percent
TOTAL		30	30	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	165	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_combo.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
56	4	4
68	4	4
72	4	4
94	4	4
108	4	4
113	4	4
153	1	1
156	1	1
157	1	1
160	1	1
165	1	1

---

Cond Coverage for Module : sysrst_ctrl_combo

	Total	Covered	Percent
Conditions	52	48	92.31
Logical	52	48	92.31
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_pre) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T42,T2
1	Covered	T4,T5,T6

 LINE       72
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_pre) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T42,T2
1	Covered	T4,T5,T6

 LINE       72
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_pre) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T42,T2
1	Covered	T4,T5,T6

 LINE       72
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_pre) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T42,T2
1	Covered	T4,T5,T6

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[0].cfg_in_sel)) && 
      2  ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en))))

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T42
1	1	Covered	T5,T6,T42

 LINE       108
 SUB-EXPRESSION ((gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en) || ((!gen_combo_trigger[0].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T42
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T42,T7

 LINE       108
 SUB-EXPRESSION (gen_combo_trigger[0].precond_valid && gen_combo_trigger[0].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T42
1	0	Not Covered
1	1	Covered	T5,T42,T7

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[1].cfg_in_sel)) && 
      2  ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en))))

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T42,T2
1	1	Covered	T42,T25,T28

 LINE       108
 SUB-EXPRESSION ((gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en) || ((!gen_combo_trigger[1].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T42,T2
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T28,T11

 LINE       108
 SUB-EXPRESSION (gen_combo_trigger[1].precond_valid && gen_combo_trigger[1].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T2
1	0	Not Covered
1	1	Covered	T42,T28,T11

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[2].cfg_in_sel)) && 
      2  ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en))))

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T42,T2
1	1	Covered	T42,T1,T2

 LINE       108
 SUB-EXPRESSION ((gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en) || ((!gen_combo_trigger[2].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T42,T2
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T2,T11

 LINE       108
 SUB-EXPRESSION (gen_combo_trigger[2].precond_valid && gen_combo_trigger[2].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T2
1	0	Not Covered
1	1	Covered	T42,T2,T11

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((|gen_combo_trigger[3].cfg_in_sel)) && 
      2  ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en))))

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T42,T2
1	1	Covered	T4,T42,T1

 LINE       108
 SUB-EXPRESSION ((gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en) || ((!gen_combo_trigger[3].cfg_combo_pre_en)))
                 --------------------------------------1--------------------------------------    ---------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T42,T2
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T42,T28

 LINE       108
 SUB-EXPRESSION (gen_combo_trigger[3].precond_valid && gen_combo_trigger[3].cfg_combo_pre_en)
                 -----------------1----------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T2
1	0	Not Covered
1	1	Covered	T4,T42,T28

 LINE       113
 EXPRESSION ((in & gen_combo_trigger[0].cfg_in_sel) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION ((in & gen_combo_trigger[1].cfg_in_sel) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T42,T25
1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION ((in & gen_combo_trigger[2].cfg_in_sel) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T42,T1
1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION ((in & gen_combo_trigger[3].cfg_in_sel) == '0)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T4,T42,T1
1	Covered	T4,T5,T6