Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T42,T2
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T42,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T42,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T42,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T2
1	0	Covered	T42,T2,T7
1	1	Covered	T4,T42,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T42,T2
0	1	Covered	T2,T7,T11
1	0	Covered	T2,T7,T11

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T42,T28
0	1	Covered	T4,T42,T28
1	0	Covered	T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T42,T28
1	-	Covered	T4,T42,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T42,T2
DetectSt	168	Covered	T4,T42,T2
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T42,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T42,T2
DebounceSt->IdleSt	163	Covered	T84,T234,T235
DetectSt->IdleSt	186	Covered	T2,T7,T11
DetectSt->StableSt	191	Covered	T4,T42,T28
IdleSt->DebounceSt	148	Covered	T4,T42,T2
StableSt->IdleSt	206	Covered	T4,T42,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T42,T2
0	1	Covered	T4,T42,T2
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T42,T2
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T42,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T42,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T42,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T234,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T42,T2
DetectSt	-	-	-	-	1	-	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	0	1	-	Covered	T4,T42,T28
DetectSt	-	-	-	-	0	0	-	Covered	T4,T42,T2
StableSt	-	-	-	-	-	-	1	Covered	T4,T42,T28
StableSt	-	-	-	-	-	-	0	Covered	T4,T42,T28
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	3118	0	0
CntIncr_A	5957637	113434	0	0
CntNoWrap_A	5957637	5335881	0	0
DetectStDropOut_A	5957637	409	0	0
DetectedOut_A	5957637	85959	0	0
DetectedPulseOut_A	5957637	920	0	0
DisabledIdleSt_A	5957637	4845180	0	0
DisabledNoDetection_A	5957637	4847248	0	0
EnterDebounceSt_A	5957637	1574	0	0
EnterDetectSt_A	5957637	1547	0	0
EnterStableSt_A	5957637	920	0	0
PulseIsPulse_A	5957637	920	0	0
StayInStableSt	5957637	84903	0	0
gen_high_event_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	783	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	3118	0	0
T1	17765	0	0	0
T2	0	54	0	0
T4	5919	46	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	46	0	0
T11	0	48	0	0
T13	0	20	0	0
T18	0	40	0	0
T25	24867	0	0	0
T28	0	26	0	0
T32	0	60	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	14	0	0
T43	402	0	0	0
T75	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	113434	0	0
T1	17765	0	0	0
T2	0	1950	0	0
T4	5919	736	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	1296	0	0
T11	0	7404	0	0
T13	0	500	0	0
T18	0	1140	0	0
T25	24867	0	0	0
T28	0	871	0	0
T32	0	1498	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	371	0	0
T43	402	0	0	0
T75	0	501	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5335881	0	0
T1	17765	17322	0	0
T4	5919	5472	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11484	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	409	0	0
T2	7669	18	0	0
T3	1152	0	0	0
T7	32416	12	0	0
T8	580	0	0	0
T9	685	0	0	0
T10	638	0	0	0
T11	46616	15	0	0
T28	11874	0	0	0
T29	507	0	0	0
T30	506	0	0	0
T32	0	30	0	0
T75	0	7	0	0
T93	0	15	0	0
T218	0	20	0	0
T236	0	20	0	0
T237	0	11	0	0
T240	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	85959	0	0
T1	17765	0	0	0
T4	5919	1391	0	0
T5	460	0	0	0
T6	1976	0	0	0
T13	0	934	0	0
T18	0	1273	0	0
T25	24867	0	0	0
T28	0	190	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	272	0	0
T43	402	0	0	0
T52	0	5195	0	0
T86	0	1690	0	0
T214	0	1250	0	0
T217	0	1684	0	0
T239	0	388	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	920	0	0
T1	17765	0	0	0
T4	5919	23	0	0
T5	460	0	0	0
T6	1976	0	0	0
T13	0	10	0	0
T18	0	20	0	0
T25	24867	0	0	0
T28	0	13	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	7	0	0
T43	402	0	0	0
T52	0	22	0	0
T86	0	11	0	0
T214	0	22	0	0
T217	0	27	0	0
T239	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4845180	0	0
T1	17765	17322	0	0
T4	5919	2015	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24402	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	7628	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4847248	0	0
T1	17765	17328	0	0
T4	5919	2015	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	7629	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1574	0	0
T1	17765	0	0	0
T2	0	27	0	0
T4	5919	23	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	23	0	0
T11	0	24	0	0
T13	0	10	0	0
T18	0	20	0	0
T25	24867	0	0	0
T28	0	13	0	0
T32	0	30	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	7	0	0
T43	402	0	0	0
T75	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	1547	0	0
T1	17765	0	0	0
T2	0	27	0	0
T4	5919	23	0	0
T5	460	0	0	0
T6	1976	0	0	0
T7	0	23	0	0
T11	0	24	0	0
T13	0	10	0	0
T18	0	20	0	0
T25	24867	0	0	0
T28	0	13	0	0
T32	0	30	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	7	0	0
T43	402	0	0	0
T75	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	920	0	0
T1	17765	0	0	0
T4	5919	23	0	0
T5	460	0	0	0
T6	1976	0	0	0
T13	0	10	0	0
T18	0	20	0	0
T25	24867	0	0	0
T28	0	13	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	7	0	0
T43	402	0	0	0
T52	0	22	0	0
T86	0	11	0	0
T214	0	22	0	0
T217	0	27	0	0
T239	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	920	0	0
T1	17765	0	0	0
T4	5919	23	0	0
T5	460	0	0	0
T6	1976	0	0	0
T13	0	10	0	0
T18	0	20	0	0
T25	24867	0	0	0
T28	0	13	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	7	0	0
T43	402	0	0	0
T52	0	22	0	0
T86	0	11	0	0
T214	0	22	0	0
T217	0	27	0	0
T239	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	84903	0	0
T1	17765	0	0	0
T4	5919	1368	0	0
T5	460	0	0	0
T6	1976	0	0	0
T13	0	922	0	0
T18	0	1252	0	0
T25	24867	0	0	0
T28	0	177	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	264	0	0
T43	402	0	0	0
T52	0	5166	0	0
T86	0	1674	0	0
T214	0	1227	0	0
T217	0	1656	0	0
T239	0	379	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	783	0	0
T1	17765	0	0	0
T4	5919	23	0	0
T5	460	0	0	0
T6	1976	0	0	0
T13	0	8	0	0
T18	0	19	0	0
T25	24867	0	0	0
T28	0	13	0	0
T39	524	0	0	0
T40	2405	0	0	0
T41	503	0	0	0
T42	11915	6	0	0
T43	402	0	0	0
T52	0	15	0	0
T86	0	6	0	0
T214	0	21	0	0
T217	0	26	0	0
T239	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T42,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T25,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T25,T13

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T25,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T42,T1
1	0	Covered	T4,T6,T40
1	1	Covered	T1,T25,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T25,T13
0	1	Covered	T25,T20,T225
1	0	Covered	T84,T85

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T18
0	1	Covered	T1,T13,T18
1	0	Covered	T84

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T13,T18
1	-	Covered	T1,T13,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T25,T13
DetectSt	168	Covered	T1,T25,T13
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T13,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T25,T13
DebounceSt->IdleSt	163	Covered	T1,T25,T149
DetectSt->IdleSt	186	Covered	T25,T20,T225
DetectSt->StableSt	191	Covered	T1,T13,T18
IdleSt->DebounceSt	148	Covered	T1,T25,T13
StableSt->IdleSt	206	Covered	T1,T13,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T25,T13
0	1	Covered	T1,T25,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T25,T13
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T25,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T85
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T25,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T25,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T25,T13
DetectSt	-	-	-	-	1	-	-	Covered	T25,T20,T225
DetectSt	-	-	-	-	0	1	-	Covered	T1,T13,T18
DetectSt	-	-	-	-	0	0	-	Covered	T1,T25,T13
StableSt	-	-	-	-	-	-	1	Covered	T1,T13,T18
StableSt	-	-	-	-	-	-	0	Covered	T1,T13,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5957637	794	0	0
CntIncr_A	5957637	44896	0	0
CntNoWrap_A	5957637	5338205	0	0
DetectStDropOut_A	5957637	51	0	0
DetectedOut_A	5957637	16442	0	0
DetectedPulseOut_A	5957637	324	0	0
DisabledIdleSt_A	5957637	4964584	0	0
DisabledNoDetection_A	5957637	4966209	0	0
EnterDebounceSt_A	5957637	416	0	0
EnterDetectSt_A	5957637	378	0	0
EnterStableSt_A	5957637	324	0	0
PulseIsPulse_A	5957637	324	0	0
StayInStableSt	5957637	16097	0	0
gen_high_level_sva.HighLevelEvent_A	5957637	5341296	0	0
gen_not_sticky_sva.StableStDropOut_A	5957637	302	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	794	0	0
T1	17765	11	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	4	0	0
T18	0	2	0	0
T19	0	8	0	0
T20	0	4	0	0
T25	24867	31	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	14	0	0
T82	0	2	0	0
T83	0	8	0	0
T149	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	44896	0	0
T1	17765	726	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	176	0	0
T18	0	36	0	0
T19	0	608	0	0
T20	0	213	0	0
T25	24867	2154	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	525	0	0
T82	0	110	0	0
T83	0	460	0	0
T149	0	2206	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5338205	0	0
T1	17765	17311	0	0
T4	5919	5518	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	24371	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11498	0	0
T43	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	51	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T10	638	0	0	0
T20	0	1	0	0
T25	24867	15	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T81	0	3	0	0
T84	0	1	0	0
T88	0	7	0	0
T96	0	4	0	0
T225	0	2	0	0
T253	0	3	0	0
T254	0	2	0	0
T255	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	16442	0	0
T1	17765	419	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	89	0	0
T18	0	68	0	0
T19	0	27	0	0
T20	0	62	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	1142	0	0
T82	0	24	0	0
T83	0	166	0	0
T149	0	555	0	0
T256	0	709	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	324	0	0
T1	17765	5	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	2	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	7	0	0
T82	0	1	0	0
T83	0	4	0	0
T149	0	12	0	0
T256	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4964584	0	0
T1	17765	12086	0	0
T4	5919	4127	0	0
T5	460	59	0	0
T6	1976	373	0	0
T25	24867	20145	0	0
T39	524	123	0	0
T40	2405	802	0	0
T41	503	102	0	0
T42	11915	11227	0	0
T43	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	4966209	0	0
T1	17765	12086	0	0
T4	5919	4128	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	20145	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11229	0	0
T43	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	416	0	0
T1	17765	6	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	2	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T25	24867	16	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	7	0	0
T82	0	1	0	0
T83	0	4	0	0
T149	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	378	0	0
T1	17765	5	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	2	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	2	0	0
T25	24867	15	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	7	0	0
T82	0	1	0	0
T83	0	4	0	0
T149	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	324	0	0
T1	17765	5	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	2	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	7	0	0
T82	0	1	0	0
T83	0	4	0	0
T149	0	12	0	0
T256	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	324	0	0
T1	17765	5	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	2	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	7	0	0
T82	0	1	0	0
T83	0	4	0	0
T149	0	12	0	0
T256	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	16097	0	0
T1	17765	414	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	86	0	0
T18	0	67	0	0
T19	0	23	0	0
T20	0	61	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	1135	0	0
T82	0	23	0	0
T83	0	162	0	0
T149	0	543	0	0
T256	0	701	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	5341296	0	0
T1	17765	17328	0	0
T4	5919	5519	0	0
T5	460	60	0	0
T6	1976	376	0	0
T25	24867	24412	0	0
T39	524	124	0	0
T40	2405	805	0	0
T41	503	103	0	0
T42	11915	11501	0	0
T43	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5957637	302	0	0
T1	17765	5	0	0
T2	7669	0	0	0
T3	1152	0	0	0
T7	32416	0	0	0
T8	580	0	0	0
T9	685	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T19	0	4	0	0
T20	0	1	0	0
T25	24867	0	0	0
T26	440	0	0	0
T27	411	0	0	0
T28	11874	0	0	0
T52	0	7	0	0
T82	0	1	0	0
T83	0	4	0	0
T149	0	12	0	0
T256	0	8	0	0