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Module Instance : tb.dut.u_reg.u_key_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.76 100.00 88.73 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.61 100.00 94.44 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

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Module Instances:
tb.dut.u_reg.u_key_intr_status_cdc
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T4,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T10
10CoveredT2,T4,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T4,T10
11CoveredT2,T4,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T10

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T4,T10
0 0 1 Covered T2,T4,T10
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T4,T10
0 0 1 Covered T2,T4,T10
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1257058637 698694 0 0
DstReqKnown_A 8078283 7247597 0 0
SrcAckBusyChk_A 1257058637 725 0 0
SrcBusyKnown_A 1257058637 1255219153 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257058637 698694 0 0
T2 215955 1938 0 0
T3 219069 0 0 0
T4 122300 1635 0 0
T5 247459 0 0 0
T10 0 828 0 0
T11 0 2870 0 0
T15 0 1685 0 0
T16 0 370 0 0
T17 0 442 0 0
T18 0 4984 0 0
T19 0 1954 0 0
T20 0 1675 0 0
T22 397766 0 0 0
T23 50980 0 0 0
T24 159223 0 0 0
T25 73353 0 0 0
T26 250163 0 0 0
T27 10807 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 8078283 7247597 0 0
T1 25224 24771 0 0
T2 579 179 0 0
T3 9127 8708 0 0
T4 270392 261857 0 0
T5 20621 20175 0 0
T22 4419 19 0 0
T23 425 25 0 0
T24 18732 18296 0 0
T25 845 445 0 0
T26 5266 4866 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257058637 725 0 0
T2 215955 1 0 0
T3 219069 0 0 0
T4 122300 2 0 0
T5 247459 0 0 0
T10 0 2 0 0
T11 0 2 0 0
T15 0 2 0 0
T16 0 2 0 0
T17 0 1 0 0
T18 0 3 0 0
T19 0 1 0 0
T20 0 1 0 0
T22 397766 0 0 0
T23 50980 0 0 0
T24 159223 0 0 0
T25 73353 0 0 0
T26 250163 0 0 0
T27 10807 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257058637 1255219153 0 0
T1 302690 302048 0 0
T2 215955 215864 0 0
T3 219069 218607 0 0
T4 122300 122084 0 0
T5 247459 246901 0 0
T22 397766 396896 0 0
T23 50980 50903 0 0
T24 159223 158910 0 0
T25 73353 73279 0 0
T26 250163 250154 0 0

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