Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_ec_rst_ctl_cdc

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	88.73			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T44

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T44
1	1	Covered	T4,T5,T44

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T44

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T44
1	1	Covered	T4,T5,T44

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T44
0	0	1	Covered	T4,T5,T44
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T44
0	0	1	Covered	T4,T5,T44
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1831100	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	2109	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1831100	0	0
T1	0	6225	0	0
T3	0	5879	0	0
T4	28575	192	0	0
T5	445888	1481	0	0
T6	221684	0	0	0
T26	0	5961	0	0
T32	0	345	0	0
T33	0	1457	0	0
T42	51271	0	0	0
T43	25919	0	0	0
T44	273308	1918	0	0
T45	78487	0	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	0	1460	0	0
T71	0	1995	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	2109	0	0
T1	0	7	0	0
T3	0	4	0	0
T4	28575	1	0	0
T5	445888	1	0	0
T6	221684	0	0	0
T26	0	7	0	0
T32	0	1	0	0
T33	0	1	0	0
T42	51271	0	0	0
T43	25919	0	0	0
T44	273308	1	0	0
T45	78487	0	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	0	1	0	0
T71	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T45,T32,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T45,T32,T7
1	1	Covered	T45,T32,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T45,T32,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T45,T32,T7
1	1	Covered	T45,T32,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T45,T32,T7
0	0	1	Covered	T45,T32,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T45,T32,T7
0	0	1	Covered	T45,T32,T7
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	949961	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1145	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	949961	0	0
T7	0	4405	0	0
T8	0	372	0	0
T9	0	955	0	0
T12	0	320	0	0
T17	0	1480	0	0
T19	0	944	0	0
T20	0	3327	0	0
T32	0	345	0	0
T34	0	500	0	0
T45	78487	757	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1145	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	0	3	0	0
T17	0	1	0	0
T19	0	1	0	0
T20	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T45	78487	1	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T45,T32,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T45,T32,T7
1	1	Covered	T45,T32,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T45,T32,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T45,T32,T7
1	1	Covered	T45,T32,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T45,T32,T7
0	0	1	Covered	T45,T32,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T45,T32,T7
0	0	1	Covered	T45,T32,T7
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	927421	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1112	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	927421	0	0
T7	0	4399	0	0
T8	0	370	0	0
T9	0	953	0	0
T12	0	293	0	0
T17	0	1472	0	0
T19	0	933	0	0
T20	0	3311	0	0
T32	0	343	0	0
T34	0	498	0	0
T45	78487	755	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1112	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	0	3	0	0
T17	0	1	0	0
T19	0	1	0	0
T20	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T45	78487	1	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T45,T32,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T45,T32,T7
1	1	Covered	T45,T32,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T45,T32,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T45,T32,T7
1	1	Covered	T45,T32,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T45,T32,T7
0	0	1	Covered	T45,T32,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T45,T32,T7
0	0	1	Covered	T45,T32,T7
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	937562	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1129	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	937562	0	0
T7	0	4393	0	0
T8	0	368	0	0
T9	0	951	0	0
T12	0	292	0	0
T17	0	1460	0	0
T19	0	923	0	0
T20	0	3294	0	0
T32	0	341	0	0
T34	0	496	0	0
T45	78487	753	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1129	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	0	3	0	0
T17	0	1	0	0
T19	0	1	0	0
T20	0	2	0	0
T32	0	1	0	0
T34	0	1	0	0
T45	78487	1	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T32,T7,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T32,T7,T8
1	1	Covered	T32,T7,T8

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T32,T7,T8
1	-	Covered	T32,T7,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T32,T7,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T32,T7,T8
1	1	Covered	T32,T7,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T32,T7,T8
0	0	1	Covered	T32,T7,T8
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T32,T7,T8
0	0	1	Covered	T32,T7,T8
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	950125	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1102	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	950125	0	0
T7	246334	6366	0	0
T8	342864	873	0	0
T9	590258	1916	0	0
T10	411727	0	0	0
T12	0	219	0	0
T19	0	2274	0	0
T20	0	3330	0	0
T24	0	2822	0	0
T32	783443	1371	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T35	121032	0	0	0
T36	125736	0	0	0
T37	121770	0	0	0
T39	0	1295	0	0
T60	0	5956	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1102	0	0
T7	246334	4	0	0
T8	342864	2	0	0
T9	590258	2	0	0
T10	411727	0	0	0
T12	0	2	0	0
T19	0	2	0	0
T20	0	2	0	0
T24	0	2	0	0
T32	783443	4	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T35	121032	0	0	0
T36	125736	0	0	0
T37	121770	0	0	0
T39	0	2	0	0
T60	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T49,T50,T51
1	-	Covered	T7,T8,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	446379	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	564	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	446379	0	0
T7	246334	2929	0	0
T8	342864	370	0	0
T9	590258	955	0	0
T10	411727	0	0	0
T12	0	111	0	0
T19	0	962	0	0
T20	0	1888	0	0
T24	0	1406	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T35	121032	0	0	0
T36	125736	0	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T39	0	625	0	0
T40	0	989	0	0
T41	0	370	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	564	0	0
T7	246334	2	0	0
T8	342864	1	0	0
T9	590258	1	0	0
T10	411727	0	0	0
T12	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T24	0	1	0	0
T33	241200	0	0	0
T34	51182	0	0	0
T35	121032	0	0	0
T36	125736	0	0	0
T37	121770	0	0	0
T38	147502	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T17,T60,T62
1	-	Covered	T1,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T3,T7
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T3,T7
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1003625	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1152	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1003625	0	0
T1	507551	5730	0	0
T2	53108	0	0	0
T3	608422	5200	0	0
T7	0	2933	0	0
T8	0	2977	0	0
T9	0	3587	0	0
T11	0	9645	0	0
T12	0	119	0	0
T13	0	354	0	0
T15	0	337	0	0
T16	0	14471	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1152	0	0
T1	507551	6	0	0
T2	53108	0	0	0
T3	608422	3	0	0
T7	0	2	0	0
T8	0	7	0	0
T9	0	4	0	0
T11	0	6	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	8	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T46,T55,T27

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T46,T55,T27
1	1	Covered	T46,T55,T27

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T46,T55,T27

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T46,T55,T27
1	1	Covered	T46,T55,T27

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T46,T55,T27
0	0	1	Covered	T46,T55,T27
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T46,T55,T27
0	0	1	Covered	T46,T55,T27
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	2840433	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	3224	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	2840433	0	0
T1	507551	0	0	0
T9	0	51615	0	0
T10	0	32541	0	0
T11	0	62952	0	0
T13	0	8614	0	0
T18	0	32978	0	0
T27	0	9014	0	0
T28	0	35506	0	0
T35	0	17152	0	0
T46	272042	9007	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	238297	0	0	0
T55	59819	8426	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	3224	0	0
T1	507551	0	0	0
T9	0	60	0	0
T10	0	20	0	0
T11	0	40	0	0
T13	0	20	0	0
T18	0	20	0	0
T27	0	20	0	0
T28	0	20	0	0
T35	0	20	0	0
T46	272042	20	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	238297	0	0	0
T55	59819	20	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T71	358065	0	0	0
T72	118199	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T46,T55

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T46,T55
1	1	Covered	T6,T46,T55

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T46,T55

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T46,T55
1	1	Covered	T6,T46,T55

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T46,T55
0	0	1	Covered	T6,T46,T55
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T46,T55
0	0	1	Covered	T6,T46,T55
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	5692062	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	6647	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	5692062	0	0
T6	221684	30104	0	0
T8	0	26412	0	0
T27	0	487	0	0
T28	0	1998	0	0
T29	0	33931	0	0
T30	0	2441	0	0
T35	0	975	0	0
T42	51271	0	0	0
T43	25919	0	0	0
T44	273308	0	0	0
T45	78487	0	0	0
T46	272042	372	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T55	59819	333	0	0
T56	0	17817	0	0
T71	358065	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6647	0	0
T6	221684	20	0	0
T8	0	60	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	20	0	0
T30	0	20	0	0
T35	0	1	0	0
T42	51271	0	0	0
T43	25919	0	0	0
T44	273308	0	0	0
T45	78487	0	0	0
T46	272042	1	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T55	59819	1	0	0
T56	0	20	0	0
T71	358065	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T4,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	6904886	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	7876	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6904886	0	0
T1	0	6486	0	0
T4	28575	200	0	0
T5	445888	1488	0	0
T6	221684	30184	0	0
T42	51271	0	0	0
T43	25919	0	0	0
T44	273308	1920	0	0
T45	78487	0	0	0
T46	272042	374	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	0	1499	0	0
T55	0	338	0	0
T56	0	17897	0	0
T71	0	1997	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7876	0	0
T1	0	7	0	0
T4	28575	1	0	0
T5	445888	1	0	0
T6	221684	20	0	0
T42	51271	0	0	0
T43	25919	0	0	0
T44	273308	1	0	0
T45	78487	0	0	0
T46	272042	1	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	20	0	0
T71	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T56,T29

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T56,T29
1	1	Covered	T6,T56,T29

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T6,T56,T29

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T56,T29
1	1	Covered	T6,T56,T29

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T56,T29
0	0	1	Covered	T6,T56,T29
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T6,T56,T29
0	0	1	Covered	T6,T56,T29
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	5658542	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	6560	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	5658542	0	0
T6	221684	30144	0	0
T8	0	26532	0	0
T9	0	79253	0	0
T13	0	50312	0	0
T29	0	34130	0	0
T30	0	2587	0	0
T36	0	16277	0	0
T42	51271	0	0	0
T43	25919	0	0	0
T44	273308	0	0	0
T45	78487	0	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T55	59819	0	0	0
T56	0	17857	0	0
T67	0	15938	0	0
T71	358065	0	0	0
T73	0	34171	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6560	0	0
T6	221684	20	0	0
T8	0	60	0	0
T9	0	95	0	0
T13	0	120	0	0
T29	0	20	0	0
T30	0	20	0	0
T36	0	20	0	0
T42	51271	0	0	0
T43	25919	0	0	0
T44	273308	0	0	0
T45	78487	0	0	0
T46	272042	0	0	0
T47	80555	0	0	0
T48	292193	0	0	0
T55	59819	0	0	0
T56	0	20	0	0
T67	0	20	0	0
T71	358065	0	0	0
T73	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T32,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T32,T8
1	1	Covered	T2,T32,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T2,T32,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T32,T8
1	1	Covered	T2,T32,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T2,T32,T8
0	0	1	Covered	T2,T32,T8
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T2,T32,T8
0	0	1	Covered	T2,T32,T8
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	988278	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1155	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	988278	0	0
T2	53108	356	0	0
T3	608422	0	0	0
T7	246334	0	0	0
T8	0	371	0	0
T9	0	1914	0	0
T13	0	1218	0	0
T14	0	80	0	0
T18	0	1429	0	0
T19	0	979	0	0
T21	0	1454	0	0
T22	0	1406	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	10880	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1155	0	0
T2	53108	1	0	0
T3	608422	0	0	0
T7	246334	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T13	0	3	0	0
T14	0	1	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T22	0	1	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T32	783443	28	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T2
1	1	Covered	T54,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T2
1	1	Covered	T54,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T2
0	0	1	Covered	T54,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T2
0	0	1	Covered	T54,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1863383	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	2155	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1863383	0	0
T1	507551	6211	0	0
T2	53108	354	0	0
T3	608422	5835	0	0
T8	0	3190	0	0
T9	0	3992	0	0
T10	0	3200	0	0
T25	209071	0	0	0
T26	433054	5947	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	678	0	0
T38	0	1326	0	0
T54	238297	1458	0	0
T56	128107	0	0	0
T57	89458	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	2155	0	0
T1	507551	7	0	0
T2	53108	1	0	0
T3	608422	4	0	0
T8	0	8	0	0
T9	0	5	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	2	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T48,T57,T32

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T48,T57,T32
1	1	Covered	T48,T57,T32

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T48,T57,T32

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T48,T57,T32
1	1	Covered	T48,T57,T32

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T48,T57,T32
0	0	1	Covered	T48,T57,T32
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T48,T57,T32
0	0	1	Covered	T48,T57,T32
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1198570	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1444	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1198570	0	0
T1	507551	0	0	0
T2	53108	0	0	0
T9	0	3837	0	0
T10	0	11362	0	0
T13	0	1976	0	0
T19	0	5927	0	0
T25	209071	0	0	0
T32	0	690	0	0
T48	292193	6226	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	1437	0	0
T67	0	3963	0	0
T68	0	1871	0	0
T70	0	1437	0	0
T71	358065	0	0	0
T72	118199	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1444	0	0
T1	507551	0	0	0
T2	53108	0	0	0
T9	0	4	0	0
T10	0	7	0	0
T13	0	5	0	0
T19	0	5	0	0
T25	209071	0	0	0
T32	0	2	0	0
T48	292193	4	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	3	0	0
T67	0	5	0	0
T68	0	4	0	0
T70	0	4	0	0
T71	358065	0	0	0
T72	118199	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T48,T57,T32

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T48,T57,T32
1	1	Covered	T48,T57,T32

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T48,T57,T32

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T48,T57,T32
1	1	Covered	T48,T57,T32

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T48,T57,T32
0	0	1	Covered	T48,T57,T32
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T48,T57,T32
0	0	1	Covered	T48,T57,T32
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1069392	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1287	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1069392	0	0
T1	507551	0	0	0
T2	53108	0	0	0
T9	0	2870	0	0
T10	0	9327	0	0
T13	0	1204	0	0
T19	0	3593	0	0
T25	209071	0	0	0
T32	0	345	0	0
T48	292193	4761	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	1429	0	0
T67	0	2303	0	0
T68	0	1364	0	0
T70	0	1072	0	0
T71	358065	0	0	0
T72	118199	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1287	0	0
T1	507551	0	0	0
T2	53108	0	0	0
T9	0	3	0	0
T10	0	6	0	0
T13	0	3	0	0
T19	0	3	0	0
T25	209071	0	0	0
T32	0	1	0	0
T48	292193	3	0	0
T54	238297	0	0	0
T55	59819	0	0	0
T56	128107	0	0	0
T57	89458	3	0	0
T67	0	3	0	0
T68	0	3	0	0
T70	0	3	0	0
T71	358065	0	0	0
T72	118199	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	6656246	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	7075	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6656246	0	0
T1	507551	50083	0	0
T2	53108	0	0	0
T3	608422	107212	0	0
T15	0	21934	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3893	0	0
T38	0	28072	0	0
T54	238297	90428	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	12689	0	0
T65	0	15631	0	0
T66	0	51217	0	0
T69	0	141377	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7075	0	0
T1	507551	57	0	0
T2	53108	0	0	0
T3	608422	64	0	0
T15	0	74	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	11	0	0
T38	0	76	0	0
T54	238297	51	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	51	0	0
T65	0	51	0	0
T66	0	51	0	0
T69	0	84	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	6631216	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	6962	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6631216	0	0
T1	507551	57298	0	0
T2	53108	0	0	0
T3	608422	88892	0	0
T15	0	15374	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3887	0	0
T38	0	26317	0	0
T54	238297	90218	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	11960	0	0
T65	0	14532	0	0
T66	0	51007	0	0
T69	0	141005	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6962	0	0
T1	507551	66	0	0
T2	53108	0	0	0
T3	608422	54	0	0
T15	0	52	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	11	0	0
T38	0	76	0	0
T54	238297	51	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	51	0	0
T65	0	51	0	0
T66	0	51	0	0
T69	0	84	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	6551485	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	6917	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6551485	0	0
T1	507551	56992	0	0
T2	53108	0	0	0
T3	608422	99356	0	0
T15	0	21406	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3887	0	0
T38	0	24951	0	0
T54	238297	90008	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	11328	0	0
T65	0	13498	0	0
T66	0	50797	0	0
T69	0	92908	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6917	0	0
T1	507551	66	0	0
T2	53108	0	0	0
T3	608422	61	0	0
T15	0	74	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	11	0	0
T38	0	76	0	0
T54	238297	51	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	51	0	0
T65	0	51	0	0
T66	0	51	0	0
T69	0	56	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	6519094	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	6927	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6519094	0	0
T1	507551	56686	0	0
T2	53108	0	0	0
T3	608422	103159	0	0
T15	0	14934	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3888	0	0
T38	0	17058	0	0
T54	238297	89798	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	10743	0	0
T65	0	13592	0	0
T66	0	50587	0	0
T69	0	120347	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	6927	0	0
T1	507551	66	0	0
T2	53108	0	0	0
T3	608422	64	0	0
T15	0	52	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	11	0	0
T38	0	54	0	0
T54	238297	51	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	51	0	0
T65	0	51	0	0
T66	0	51	0	0
T69	0	72	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1230145	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1405	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1230145	0	0
T1	507551	6491	0	0
T2	53108	0	0	0
T3	608422	6663	0	0
T15	0	592	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3185	0	0
T38	0	1490	0	0
T54	238297	1498	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	215	0	0
T65	0	341	0	0
T66	0	898	0	0
T69	0	9590	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1405	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T15	0	2	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T69	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1203416	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1363	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1203416	0	0
T1	507551	6421	0	0
T2	53108	0	0	0
T3	608422	6472	0	0
T15	0	572	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3179	0	0
T38	0	1289	0	0
T54	238297	1488	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	180	0	0
T65	0	284	0	0
T66	0	888	0	0
T69	0	9530	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1363	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T15	0	2	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T69	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1194400	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1385	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1194400	0	0
T1	507551	6351	0	0
T2	53108	0	0	0
T3	608422	6232	0	0
T15	0	552	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3179	0	0
T38	0	1307	0	0
T54	238297	1478	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	215	0	0
T65	0	318	0	0
T66	0	878	0	0
T69	0	9470	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1385	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T15	0	2	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T69	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T3
1	1	Covered	T54,T1,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T3
0	0	1	Covered	T54,T1,T3
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1218450	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1386	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1218450	0	0
T1	507551	6281	0	0
T2	53108	0	0	0
T3	608422	6038	0	0
T15	0	532	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3180	0	0
T38	0	1314	0	0
T54	238297	1468	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	180	0	0
T65	0	344	0	0
T66	0	868	0	0
T69	0	9410	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1386	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T15	0	2	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T69	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	7205174	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	7653	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7205174	0	0
T1	507551	50155	0	0
T2	53108	0	0	0
T3	608422	107731	0	0
T8	0	3003	0	0
T9	0	2642	0	0
T10	0	3462	0	0
T25	209071	0	0	0
T26	433054	6129	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3857	0	0
T38	0	28790	0	0
T54	238297	90524	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	51313	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7653	0	0
T1	507551	57	0	0
T2	53108	0	0	0
T3	608422	64	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	11	0	0
T38	0	76	0	0
T54	238297	51	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	7130252	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	7488	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7130252	0	0
T1	507551	57388	0	0
T2	53108	0	0	0
T3	608422	89283	0	0
T8	0	2989	0	0
T9	0	2636	0	0
T10	0	3438	0	0
T25	209071	0	0	0
T26	433054	6115	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3851	0	0
T38	0	27031	0	0
T54	238297	90314	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	51103	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7488	0	0
T1	507551	66	0	0
T2	53108	0	0	0
T3	608422	54	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	11	0	0
T38	0	76	0	0
T54	238297	51	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	7096923	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	7504	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7096923	0	0
T1	507551	57082	0	0
T2	53108	0	0	0
T3	608422	99839	0	0
T8	0	2975	0	0
T9	0	2630	0	0
T10	0	3415	0	0
T25	209071	0	0	0
T26	433054	6101	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3851	0	0
T38	0	25703	0	0
T54	238297	90104	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	50893	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7504	0	0
T1	507551	66	0	0
T2	53108	0	0	0
T3	608422	61	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	11	0	0
T38	0	76	0	0
T54	238297	51	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	7040386	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	7461	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7040386	0	0
T1	507551	56776	0	0
T2	53108	0	0	0
T3	608422	103723	0	0
T8	0	2961	0	0
T9	0	2624	0	0
T10	0	3395	0	0
T25	209071	0	0	0
T26	433054	6087	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3852	0	0
T38	0	17493	0	0
T54	238297	89894	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	50683	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	7461	0	0
T1	507551	66	0	0
T2	53108	0	0	0
T3	608422	64	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	11	0	0
T38	0	54	0	0
T54	238297	51	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1745911	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1990	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1745911	0	0
T1	507551	6463	0	0
T2	53108	0	0	0
T3	608422	6589	0	0
T8	0	2947	0	0
T9	0	2618	0	0
T10	0	3376	0	0
T25	209071	0	0	0
T26	433054	6073	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3149	0	0
T38	0	1409	0	0
T54	238297	1494	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	894	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1990	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1690306	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1927	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1690306	0	0
T1	507551	6393	0	0
T2	53108	0	0	0
T3	608422	6367	0	0
T8	0	2933	0	0
T9	0	2612	0	0
T10	0	3368	0	0
T25	209071	0	0	0
T26	433054	6059	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3143	0	0
T38	0	1211	0	0
T54	238297	1484	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	884	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1927	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1720121	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1951	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1720121	0	0
T1	507551	6323	0	0
T2	53108	0	0	0
T3	608422	6155	0	0
T8	0	2919	0	0
T9	0	2606	0	0
T10	0	3355	0	0
T25	209071	0	0	0
T26	433054	6045	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3143	0	0
T38	0	1444	0	0
T54	238297	1474	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	874	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1951	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1695336	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1949	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1695336	0	0
T1	507551	6253	0	0
T2	53108	0	0	0
T3	608422	5965	0	0
T8	0	2905	0	0
T9	0	2600	0	0
T10	0	3329	0	0
T25	209071	0	0	0
T26	433054	6031	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3144	0	0
T38	0	1224	0	0
T54	238297	1464	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	864	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1949	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1775715	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	2017	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1775715	0	0
T1	507551	6449	0	0
T2	53108	0	0	0
T3	608422	6552	0	0
T8	0	2891	0	0
T9	0	2594	0	0
T10	0	3297	0	0
T25	209071	0	0	0
T26	433054	6017	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3131	0	0
T38	0	1387	0	0
T54	238297	1492	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	892	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	2017	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1725407	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1967	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1725407	0	0
T1	507551	6379	0	0
T2	53108	0	0	0
T3	608422	6320	0	0
T8	0	2877	0	0
T9	0	2588	0	0
T10	0	3289	0	0
T25	209071	0	0	0
T26	433054	6003	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3125	0	0
T38	0	1272	0	0
T54	238297	1482	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	882	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1967	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1715443	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1956	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1715443	0	0
T1	507551	6309	0	0
T2	53108	0	0	0
T3	608422	6122	0	0
T8	0	2863	0	0
T9	0	2582	0	0
T10	0	3263	0	0
T25	209071	0	0	0
T26	433054	5989	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3125	0	0
T38	0	1408	0	0
T54	238297	1472	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	872	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1956	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T54,T1,T26
1	1	Covered	T54,T1,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T54,T1,T26
0	0	1	Covered	T54,T1,T26
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	1679580	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1947	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1679580	0	0
T1	507551	6239	0	0
T2	53108	0	0	0
T3	608422	5911	0	0
T8	0	2849	0	0
T9	0	2576	0	0
T10	0	3248	0	0
T25	209071	0	0	0
T26	433054	5975	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	3126	0	0
T38	0	1283	0	0
T54	238297	1462	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	862	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1947	0	0
T1	507551	7	0	0
T2	53108	0	0	0
T3	608422	4	0	0
T8	0	7	0	0
T9	0	3	0	0
T10	0	2	0	0
T25	209071	0	0	0
T26	433054	7	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T32	0	9	0	0
T38	0	4	0	0
T54	238297	1	0	0
T56	128107	0	0	0
T57	89458	0	0	0
T66	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T3,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T3,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T8
1	1	Covered	T1,T3,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T3,T8
0	0	1	Covered	T1,T3,T8
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1253150054	930363	0	0
DstReqKnown_A	8137556	7264050	0	0
SrcAckBusyChk_A	1253150054	1100	0	0
SrcBusyKnown_A	1253150054	1251307761	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	930363	0	0
T1	507551	5718	0	0
T2	53108	0	0	0
T3	608422	5179	0	0
T8	0	2468	0	0
T9	0	2864	0	0
T11	0	9573	0	0
T13	0	338	0	0
T15	0	334	0	0
T16	0	14455	0	0
T17	0	1468	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T69	0	13876	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8137556	7264050	0	0
T4	571	171	0	0
T5	891	491	0	0
T6	522	122	0	0
T42	427	27	0	0
T43	431	31	0	0
T44	569	169	0	0
T45	1016	616	0	0
T46	2176	176	0	0
T47	423	23	0	0
T48	608	208	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1100	0	0
T1	507551	6	0	0
T2	53108	0	0	0
T3	608422	3	0	0
T8	0	6	0	0
T9	0	3	0	0
T11	0	6	0	0
T13	0	1	0	0
T15	0	1	0	0
T16	0	8	0	0
T17	0	1	0	0
T25	209071	0	0	0
T26	433054	0	0	0
T27	62413	0	0	0
T28	647492	0	0	0
T29	261336	0	0	0
T30	21305	0	0	0
T31	30667	0	0	0
T69	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253150054	1251307761	0	0
T4	28575	28503	0	0
T5	445888	445806	0	0
T6	221684	221585	0	0
T42	51271	51204	0	0
T43	25919	25830	0	0
T44	273308	273243	0	0
T45	78487	78419	0	0
T46	272042	271632	0	0
T47	80555	80477	0	0
T48	292193	292136	0	0