ASSERT | PROPERTIES | SEQUENCES | |
Total | 1058 | 0 | 10 |
Category 0 | 1058 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 1058 | 0 | 10 |
Severity 0 | 1058 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 1058 | 100.00 |
Uncovered | 6 | 0.57 |
Success | 1052 | 99.43 |
Failure | 0 | 0.00 |
Incomplete | 4 | 0.38 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_reg.u_combo_intr_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 7166523 | 563 | 0 | 912 | |
tb.dut.u_reg.u_key_intr_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 7166523 | 287 | 0 | 912 | |
tb.dut.u_reg.u_ulp_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 7166523 | 70 | 0 | 912 | |
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 7166523 | 668 | 0 | 912 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1193246347 | 594953 | 594953 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1193246347 | 2790 | 2790 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1193246347 | 6876 | 6876 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1193246347 | 5092 | 5092 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1193246347 | 6371 | 6371 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1193246347 | 4052 | 4052 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1193246347 | 2153 | 2153 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1193246347 | 5317 | 5317 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1193246347 | 14940 | 14940 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1193246347 | 88655 | 88655 | 849 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1193246347 | 594953 | 594953 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1193246347 | 2790 | 2790 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1193246347 | 6876 | 6876 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1193246347 | 5092 | 5092 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1193246347 | 6371 | 6371 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 1193246347 | 4052 | 4052 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 1193246347 | 2153 | 2153 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 1193246347 | 5317 | 5317 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 1193246347 | 14940 | 14940 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 1193246347 | 88655 | 88655 | 849 |