Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T24,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T24,T2
1	1	Covered	T1,T24,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T11,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T11,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T18,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T18
1	0	Covered	T1,T24,T6
1	1	Covered	T2,T11,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T56
0	1	Covered	T192,T209
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T56
0	1	Covered	T56,T65,T57
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T18,T56
1	-	Covered	T56,T65,T57

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T11,T18
DetectSt	168	Covered	T2,T18,T56
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T18,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T18,T56
DebounceSt->IdleSt	163	Covered	T11,T42,T210
DetectSt->IdleSt	186	Covered	T192,T209
DetectSt->StableSt	191	Covered	T2,T18,T56
IdleSt->DebounceSt	148	Covered	T2,T11,T18
StableSt->IdleSt	206	Covered	T18,T56,T65

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T11,T18
0	1	Covered	T2,T11,T18
0	0	Excluded	T4,T5,T1	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T18,T56
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T11,T18
IdleSt	0	-	-	-	-	-	-	Covered	T1,T24,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T18,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T42,T210
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T11,T18
DetectSt	-	-	-	-	1	-	-	Covered	T192,T209
DetectSt	-	-	-	-	0	1	-	Covered	T2,T18,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T56,T65,T57
StableSt	-	-	-	-	-	-	0	Covered	T2,T18,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	119	0	0
CntIncr_A	6890910	59835	0	0
CntNoWrap_A	6890910	6236413	0	0
DetectStDropOut_A	6890910	2	0	0
DetectedOut_A	6890910	7140	0	0
DetectedPulseOut_A	6890910	53	0	0
DisabledIdleSt_A	6890910	5980825	0	0
DisabledNoDetection_A	6890910	5983010	0	0
EnterDebounceSt_A	6890910	64	0	0
EnterDetectSt_A	6890910	55	0	0
EnterStableSt_A	6890910	53	0	0
PulseIsPulse_A	6890910	53	0	0
StayInStableSt	6890910	7062	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	26	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6890910	119
T2	915	2
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T11	0	1
T18	0	2
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T39	0	2
T42	0	1
T54	0	8
T56	0	4
T57	0	4
T65	0	6
T156	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6890910	59835
T2	915	92
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T11	0	71
T18	0	84
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T39	0	42
T42	0	51
T54	0	230
T56	0	172
T57	0	96
T65	0	192
T156	0	78

CntNoWrap_A

Name	Attempts	Real Successes
Total	6890910	6236413
T1	678	277
T2	915	512
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6890910	2
T192	705	1
T209	0	1
T211	1754	0
T212	498	0
T213	731	0
T214	17418	0
T215	422	0
T216	504	0
T217	6861	0
T218	406	0
T219	402	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6890910	7140
T2	915	275
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T18	0	167
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T39	0	177
T54	0	396
T56	0	170
T57	0	177
T65	0	249
T154	0	370
T156	0	40
T193	0	109

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6890910	53
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T39	0	1
T54	0	4
T56	0	2
T57	0	2
T65	0	3
T154	0	2
T156	0	1
T193	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6890910	5980825
T1	678	277
T2	915	4
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6890910	5983010
T1	678	278
T2	915	4
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6890910	64
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T11	0	1
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T39	0	1
T42	0	1
T54	0	4
T56	0	2
T57	0	2
T65	0	3
T156	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6890910	55
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T39	0	1
T54	0	4
T56	0	2
T57	0	2
T65	0	3
T154	0	2
T156	0	1
T193	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6890910	53
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T39	0	1
T54	0	4
T56	0	2
T57	0	2
T65	0	3
T154	0	2
T156	0	1
T193	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6890910	53
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T39	0	1
T54	0	4
T56	0	2
T57	0	2
T65	0	3
T154	0	2
T156	0	1
T193	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6890910	7062
T2	915	273
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T18	0	165
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T39	0	175
T54	0	391
T56	0	167
T57	0	174
T65	0	245
T154	0	367
T156	0	38
T193	0	108

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6890910	6238768
T1	678	278
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6890910	26
T23	4912	0
T36	9124	0
T37	245583	0
T38	899	0
T54	0	3
T56	904	1
T57	738	1
T63	722	0
T65	3466	2
T67	489	0
T68	496	0
T91	0	2
T154	0	1
T159	0	3
T180	0	1
T193	0	1
T194	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T24,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T13,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T11,T13,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T13,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T14
1	0	Covered	T24,T6,T3
1	1	Covered	T11,T13,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T15
0	1	Covered	T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T13,T15
0	1	Covered	T56,T65,T188
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T13,T15
1	-	Covered	T56,T65,T188

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T13,T15
DetectSt	168	Covered	T11,T13,T15
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T13,T15

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T13,T15
DebounceSt->IdleSt	163	Covered	T159,T189,T205
DetectSt->IdleSt	186	Covered	T91
DetectSt->StableSt	191	Covered	T11,T13,T15
IdleSt->DebounceSt	148	Covered	T11,T13,T15
StableSt->IdleSt	206	Covered	T56,T65,T36

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T13,T15
0	1	Covered	T11,T13,T15
0	0	Excluded	T4,T5,T1	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T11,T13,T15
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T13,T15
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T13,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T159,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T13,T15
DetectSt	-	-	-	-	1	-	-	Covered	T91
DetectSt	-	-	-	-	0	1	-	Covered	T11,T13,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T56,T65,T188
StableSt	-	-	-	-	-	-	0	Covered	T11,T13,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	92	0	0
CntIncr_A	6890910	14970	0	0
CntNoWrap_A	6890910	6236440	0	0
DetectStDropOut_A	6890910	1	0	0
DetectedOut_A	6890910	3470	0	0
DetectedPulseOut_A	6890910	44	0	0
DisabledIdleSt_A	6890910	6057666	0	0
DisabledNoDetection_A	6890910	6059843	0	0
EnterDebounceSt_A	6890910	48	0	0
EnterDetectSt_A	6890910	45	0	0
EnterStableSt_A	6890910	44	0	0
PulseIsPulse_A	6890910	44	0	0
StayInStableSt	6890910	3400	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6890910	6151	0	0
gen_low_level_sva.LowLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	16	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6890910	92
T11	544	2
T12	39331	0
T13	604	2
T14	104160	0
T15	871	2
T17	0	2
T36	0	2
T42	0	4
T54	0	2
T56	0	2
T62	654	0
T65	0	4
T69	585	0
T70	420	0
T71	523	0
T188	0	2
T220	589	0

CntIncr_A

Name	Attempts	Real Successes
Total	6890910	14970
T11	544	71
T12	39331	0
T13	604	59
T14	104160	0
T15	871	81
T17	0	85
T36	0	64
T42	0	98
T54	0	48
T56	0	86
T62	654	0
T65	0	128
T69	585	0
T70	420	0
T71	523	0
T188	0	73
T220	589	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	6890910	6236440
T1	678	277
T2	915	514
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6890910	1
T88	6976	0
T91	26836	1
T146	60254	0
T147	8453	0
T148	25439	0
T149	914	0
T150	407	0
T151	27206	0
T152	623	0
T153	19836	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6890910	3470
T11	544	39
T12	39331	0
T13	604	43
T14	104160	0
T15	871	158
T17	0	113
T36	0	40
T42	0	136
T54	0	222
T56	0	64
T62	654	0
T65	0	42
T69	585	0
T70	420	0
T71	523	0
T188	0	101
T220	589	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6890910	44
T11	544	1
T12	39331	0
T13	604	1
T14	104160	0
T15	871	1
T17	0	1
T36	0	1
T42	0	2
T54	0	1
T56	0	1
T62	654	0
T65	0	2
T69	585	0
T70	420	0
T71	523	0
T188	0	1
T220	589	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6890910	6057666
T1	678	277
T2	915	514
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6890910	6059843
T1	678	278
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6890910	48
T11	544	1
T12	39331	0
T13	604	1
T14	104160	0
T15	871	1
T17	0	1
T36	0	1
T42	0	2
T54	0	1
T56	0	1
T62	654	0
T65	0	2
T69	585	0
T70	420	0
T71	523	0
T188	0	1
T220	589	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6890910	45
T11	544	1
T12	39331	0
T13	604	1
T14	104160	0
T15	871	1
T17	0	1
T36	0	1
T42	0	2
T54	0	1
T56	0	1
T62	654	0
T65	0	2
T69	585	0
T70	420	0
T71	523	0
T188	0	1
T220	589	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	6890910	44
T11	544	1
T12	39331	0
T13	604	1
T14	104160	0
T15	871	1
T17	0	1
T36	0	1
T42	0	2
T54	0	1
T56	0	1
T62	654	0
T65	0	2
T69	585	0
T70	420	0
T71	523	0
T188	0	1
T220	589	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6890910	44
T11	544	1
T12	39331	0
T13	604	1
T14	104160	0
T15	871	1
T17	0	1
T36	0	1
T42	0	2
T54	0	1
T56	0	1
T62	654	0
T65	0	2
T69	585	0
T70	420	0
T71	523	0
T188	0	1
T220	589	0

StayInStableSt

Name	Attempts	Real Successes
Total	6890910	3400
T11	544	37
T12	39331	0
T13	604	41
T14	104160	0
T15	871	156
T17	0	111
T36	0	38
T42	0	132
T54	0	220
T56	0	63
T62	654	0
T65	0	40
T69	585	0
T70	420	0
T71	523	0
T188	0	100
T220	589	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	6890910	6151
T2	915	0
T3	25438	29
T6	505	1
T7	21449	29
T8	23338	16
T9	488	1
T24	9167	30
T25	238296	0
T26	438	7
T27	708	0
T29	0	4
T30	0	23
T51	0	7

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	6890910	6238768
T1	678	278
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6890910	16
T23	4912	0
T36	9124	0
T37	245583	0
T38	899	0
T56	904	1
T57	738	0
T58	0	1
T63	722	0
T65	3466	2
T67	489	0
T68	496	0
T102	0	1
T156	0	1
T159	0	1
T182	0	1
T188	0	1
T207	0	1
T221	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T24,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T24,T2
1	1	Covered	T1,T24,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T20,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T15,T20,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T20,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T20
1	0	Covered	T1,T24,T2
1	1	Covered	T15,T20,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T56
0	1	Covered	T56
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T20,T56
0	1	Covered	T15,T56,T65
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T20,T56
1	-	Covered	T15,T56,T65

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T20,T56
DetectSt	168	Covered	T15,T20,T56
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T15,T20,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T20,T56
DebounceSt->IdleSt	163	Covered	T188,T159,T171
DetectSt->IdleSt	186	Covered	T56
DetectSt->StableSt	191	Covered	T15,T20,T56
IdleSt->DebounceSt	148	Covered	T15,T20,T56
StableSt->IdleSt	206	Covered	T15,T20,T56

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T20,T56
0	1	Covered	T15,T20,T56
0	0	Excluded	T4,T5,T1	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T15,T20,T56
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T20,T56
IdleSt	0	-	-	-	-	-	-	Covered	T1,T24,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T20,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T188,T159,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T20,T56
DetectSt	-	-	-	-	1	-	-	Covered	T56
DetectSt	-	-	-	-	0	1	-	Covered	T15,T20,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T56,T65
StableSt	-	-	-	-	-	-	0	Covered	T15,T20,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	101	0	0
CntIncr_A	6890910	116924	0	0
CntNoWrap_A	6890910	6236431	0	0
DetectStDropOut_A	6890910	1	0	0
DetectedOut_A	6890910	66261	0	0
DetectedPulseOut_A	6890910	48	0	0
DisabledIdleSt_A	6890910	5968368	0	0
DisabledNoDetection_A	6890910	5970559	0	0
EnterDebounceSt_A	6890910	54	0	0
EnterDetectSt_A	6890910	49	0	0
EnterStableSt_A	6890910	48	0	0
PulseIsPulse_A	6890910	48	0	0
StayInStableSt	6890910	66198	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	31	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6890910	101
T15	871	4
T16	1184	0
T17	53846	0
T18	11510	0
T20	0	2
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	2
T39	0	6
T42	0	2
T43	714	0
T44	1292	0
T54	0	2
T56	0	4
T57	0	2
T65	0	4
T188	0	1

CntIncr_A

Name	Attempts	Real Successes
Total	6890910	116924
T15	871	162
T16	1184	0
T17	53846	0
T18	11510	0
T20	0	10
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	64
T39	0	208
T42	0	47
T43	714	0
T44	1292	0
T54	0	38
T56	0	172
T57	0	48
T65	0	128
T188	0	73

CntNoWrap_A

Name	Attempts	Real Successes
Total	6890910	6236431
T1	678	277
T2	915	514
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6890910	1
T23	4912	0
T36	9124	0
T37	245583	0
T38	899	0
T56	904	1
T57	738	0
T63	722	0
T65	3466	0
T67	489	0
T68	496	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6890910	66261
T15	871	58
T16	1184	0
T17	53846	0
T18	11510	0
T20	0	44
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	40
T39	0	14
T42	0	136
T43	714	0
T44	1292	0
T54	0	135
T56	0	64
T57	0	98
T65	0	104
T156	0	43

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6890910	48
T15	871	2
T16	1184	0
T17	53846	0
T18	11510	0
T20	0	1
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	3
T42	0	1
T43	714	0
T44	1292	0
T54	0	1
T56	0	1
T57	0	1
T65	0	2
T156	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6890910	5968368
T1	678	277
T2	915	514
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6890910	5970559
T1	678	278
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6890910	54
T15	871	2
T16	1184	0
T17	53846	0
T18	11510	0
T20	0	1
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	3
T42	0	1
T43	714	0
T44	1292	0
T54	0	1
T56	0	2
T57	0	1
T65	0	2
T188	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6890910	49
T15	871	2
T16	1184	0
T17	53846	0
T18	11510	0
T20	0	1
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	3
T42	0	1
T43	714	0
T44	1292	0
T54	0	1
T56	0	2
T57	0	1
T65	0	2
T156	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6890910	48
T15	871	2
T16	1184	0
T17	53846	0
T18	11510	0
T20	0	1
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	3
T42	0	1
T43	714	0
T44	1292	0
T54	0	1
T56	0	1
T57	0	1
T65	0	2
T156	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6890910	48
T15	871	2
T16	1184	0
T17	53846	0
T18	11510	0
T20	0	1
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	3
T42	0	1
T43	714	0
T44	1292	0
T54	0	1
T56	0	1
T57	0	1
T65	0	2
T156	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6890910	66198
T15	871	55
T16	1184	0
T17	53846	0
T18	11510	0
T20	0	42
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	39
T39	0	11
T42	0	135
T43	714	0
T44	1292	0
T54	0	133
T56	0	63
T57	0	97
T65	0	102
T156	0	42

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6890910	6238768
T1	678	278
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6890910	31
T15	871	1
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	3
T42	0	1
T43	714	0
T44	1292	0
T56	0	1
T57	0	1
T65	0	2
T90	0	1
T154	0	1
T156	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T24,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T57,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T15,T57,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T57,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T15,T17
1	0	Covered	T24,T3,T7
1	1	Covered	T15,T57,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T57,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T57,T36
0	1	Covered	T15,T58,T193
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T57,T36
1	-	Covered	T15,T58,T193

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T57,T36
DetectSt	168	Covered	T15,T57,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T15,T57,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T57,T36
DebounceSt->IdleSt	163	Covered	T206,T187
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T15,T57,T36
IdleSt->DebounceSt	148	Covered	T15,T57,T36
StableSt->IdleSt	206	Covered	T15,T36,T39

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T57,T36
0	1	Covered	T15,T57,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T15,T57,T36
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T57,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T57,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T206,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T57,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T15,T57,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T58,T193
StableSt	-	-	-	-	-	-	0	Covered	T15,T57,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	78	0	0
CntIncr_A	6890910	116025	0	0
CntNoWrap_A	6890910	6236454	0	0
DetectStDropOut_A	6890910	0	0	0
DetectedOut_A	6890910	3376	0	0
DetectedPulseOut_A	6890910	38	0	0
DisabledIdleSt_A	6890910	5865144	0	0
DisabledNoDetection_A	6890910	5867327	0	0
EnterDebounceSt_A	6890910	40	0	0
EnterDetectSt_A	6890910	38	0	0
EnterStableSt_A	6890910	38	0	0
PulseIsPulse_A	6890910	38	0	0
StayInStableSt	6890910	3317	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6890910	6176	0	0
gen_low_level_sva.LowLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	15	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6890910	78
T15	871	2
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	2
T39	0	4
T43	714	0
T44	1292	0
T57	0	2
T58	0	6
T93	0	2
T156	0	4
T193	0	2
T204	0	2
T206	0	3

CntIncr_A

Name	Attempts	Real Successes
Total	6890910	116025
T15	871	81
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	64
T39	0	96
T43	714	0
T44	1292	0
T57	0	48
T58	0	177
T93	0	34
T156	0	145
T193	0	23
T204	0	64387
T206	0	46

CntNoWrap_A

Name	Attempts	Real Successes
Total	6890910	6236454
T1	678	277
T2	915	514
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6890910	3376
T15	871	159
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	153
T39	0	76
T43	714	0
T44	1292	0
T57	0	42
T58	0	126
T93	0	147
T156	0	168
T193	0	43
T204	0	40
T206	0	19

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6890910	38
T15	871	1
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	2
T43	714	0
T44	1292	0
T57	0	1
T58	0	3
T93	0	1
T156	0	2
T193	0	1
T204	0	1
T206	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6890910	5865144
T1	678	277
T2	915	514
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6890910	5867327
T1	678	278
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6890910	40
T15	871	1
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	2
T43	714	0
T44	1292	0
T57	0	1
T58	0	3
T93	0	1
T156	0	2
T193	0	1
T204	0	1
T206	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6890910	38
T15	871	1
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	2
T43	714	0
T44	1292	0
T57	0	1
T58	0	3
T93	0	1
T156	0	2
T193	0	1
T204	0	1
T206	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6890910	38
T15	871	1
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	2
T43	714	0
T44	1292	0
T57	0	1
T58	0	3
T93	0	1
T156	0	2
T193	0	1
T204	0	1
T206	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6890910	38
T15	871	1
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	1
T39	0	2
T43	714	0
T44	1292	0
T57	0	1
T58	0	3
T93	0	1
T156	0	2
T193	0	1
T204	0	1
T206	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6890910	3317
T15	871	158
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T36	0	151
T39	0	72
T43	714	0
T44	1292	0
T57	0	40
T58	0	122
T93	0	145
T156	0	164
T193	0	42
T204	0	38
T206	0	18

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	6890910	6176
T2	915	0
T3	25438	27
T6	505	0
T7	21449	35
T8	23338	11
T9	488	1
T10	0	12
T24	9167	27
T25	238296	0
T26	438	3
T27	708	0
T29	0	5
T30	0	21
T51	0	7

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	6890910	6238768
T1	678	278
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6890910	15
T15	871	1
T16	1184	0
T17	53846	0
T18	11510	0
T32	663	0
T33	402	0
T34	8402	0
T35	698	0
T43	714	0
T44	1292	0
T58	0	2
T159	0	1
T165	0	1
T174	0	1
T192	0	1
T193	0	1
T206	0	1
T222	0	1
T223	0	1

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T13,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T13,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T13,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T13,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T14
0	1	Covered	T94,T154,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T14
0	1	Covered	T13,T36,T54
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T14
1	-	Covered	T13,T36,T54

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T14
DetectSt	168	Covered	T2,T13,T14
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T13,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T14
DebounceSt->IdleSt	163	Covered	T94,T224,T225
DetectSt->IdleSt	186	Covered	T94,T154,T196
DetectSt->StableSt	191	Covered	T2,T13,T14
IdleSt->DebounceSt	148	Covered	T2,T13,T14
StableSt->IdleSt	206	Covered	T13,T18,T65

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T13,T14
0	1	Covered	T2,T13,T14
0	0	Excluded	T4,T5,T1	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T14
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T14
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T224,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T14
DetectSt	-	-	-	-	1	-	-	Covered	T94,T154,T196
DetectSt	-	-	-	-	0	1	-	Covered	T2,T13,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T36,T54
StableSt	-	-	-	-	-	-	0	Covered	T2,T13,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	148	0	0
CntIncr_A	6890910	155783	0	0
CntNoWrap_A	6890910	6236384	0	0
DetectStDropOut_A	6890910	3	0	0
DetectedOut_A	6890910	59588	0	0
DetectedPulseOut_A	6890910	69	0	0
DisabledIdleSt_A	6890910	5789802	0	0
DisabledNoDetection_A	6890910	5791980	0	0
EnterDebounceSt_A	6890910	77	0	0
EnterDetectSt_A	6890910	72	0	0
EnterStableSt_A	6890910	69	0	0
PulseIsPulse_A	6890910	69	0	0
StayInStableSt	6890910	59485	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	33	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6890910	148
T2	915	2
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T13	0	2
T14	0	2
T18	0	2
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T36	0	4
T39	0	4
T54	0	8
T65	0	2
T93	0	4
T188	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	6890910	155783
T2	915	92
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T13	0	59
T14	0	46185
T18	0	84
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T36	0	128
T39	0	118
T54	0	172
T65	0	64
T93	0	68
T188	0	73

CntNoWrap_A

Name	Attempts	Real Successes
Total	6890910	6236384
T1	678	277
T2	915	512
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DetectStDropOut_A

Name	Attempts	Real Successes
Total	6890910	3
T41	1717	0
T42	9501	0
T94	563	1
T136	494	0
T137	493	0
T138	526	0
T154	0	1
T196	0	1
T226	504	0
T227	526	0
T228	523	0
T229	521	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6890910	59588
T2	915	43
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T13	0	32
T14	0	41
T18	0	41
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T36	0	208
T39	0	346
T54	0	239
T65	0	39
T93	0	213
T188	0	159

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6890910	69
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T13	0	1
T14	0	1
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T36	0	2
T39	0	2
T54	0	4
T65	0	1
T93	0	2
T188	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6890910	5789802
T1	678	277
T2	915	4
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	3
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6890910	5791980
T1	678	278
T2	915	4
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	3
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6890910	77
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T13	0	1
T14	0	1
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T36	0	2
T39	0	2
T54	0	4
T65	0	1
T93	0	2
T188	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6890910	72
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T13	0	1
T14	0	1
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T36	0	2
T39	0	2
T54	0	4
T65	0	1
T93	0	2
T188	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	6890910	69
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T13	0	1
T14	0	1
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T36	0	2
T39	0	2
T54	0	4
T65	0	1
T93	0	2
T188	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6890910	69
T2	915	1
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T13	0	1
T14	0	1
T18	0	1
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T36	0	2
T39	0	2
T54	0	4
T65	0	1
T93	0	2
T188	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	6890910	59485
T2	915	41
T3	25438	0
T6	505	0
T7	21449	0
T8	23338	0
T9	488	0
T13	0	31
T14	0	39
T18	0	39
T25	238296	0
T26	438	0
T27	708	0
T28	1461	0
T36	0	205
T39	0	342
T54	0	233
T65	0	37
T93	0	210
T188	0	158

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	6890910	6238768
T1	678	278
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6890910	33
T13	604	1
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	0
T32	663	0
T33	402	0
T34	8402	0
T36	0	1
T54	0	2
T71	523	0
T90	0	1
T93	0	1
T114	0	1
T154	0	1
T157	0	1
T188	0	1
T193	0	2
T220	589	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T56,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T13,T17,T56

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T56,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T13
1	0	Covered	T4,T5,T24
1	1	Covered	T13,T17,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T56,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T56,T36
0	1	Covered	T36,T54,T93
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T56,T36
1	-	Covered	T36,T54,T93

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T17,T56
DetectSt	168	Covered	T13,T56,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T13,T56,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T56,T36
DebounceSt->IdleSt	163	Covered	T17,T39,T189
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T13,T56,T36
IdleSt->DebounceSt	148	Covered	T13,T17,T56
StableSt->IdleSt	206	Covered	T36,T54,T93

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T56,T36
0	1	Covered	T13,T17,T56
0	0	Excluded	T4,T5,T1	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T13,T56,T36
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T17,T56
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T56,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T17,T56
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T56,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T54,T93
StableSt	-	-	-	-	-	-	0	Covered	T13,T56,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	88	0	0
CntIncr_A	6890910	53021	0	0
CntNoWrap_A	6890910	6236444	0	0
DetectStDropOut_A	6890910	0	0	0
DetectedOut_A	6890910	65026	0	0
DetectedPulseOut_A	6890910	43	0	0
DisabledIdleSt_A	6890910	5821311	0	0
DisabledNoDetection_A	6890910	5823491	0	0
EnterDebounceSt_A	6890910	46	0	0
EnterDetectSt_A	6890910	43	0	0
EnterStableSt_A	6890910	43	0	0
PulseIsPulse_A	6890910	43	0	0
StayInStableSt	6890910	64964	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6890910	6782	0	0
gen_low_level_sva.LowLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	22	0	0

CntClr_A

Name	Attempts	Real Successes
Total	6890910	88
T13	604	2
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	0
T32	663	0
T33	402	0
T34	8402	0
T36	0	2
T39	0	1
T54	0	4
T56	0	2
T71	523	0
T93	0	2
T94	0	4
T154	0	4
T156	0	2
T193	0	4
T220	589	0

CntIncr_A

Name	Attempts	Real Successes
Total	6890910	53021
T13	604	59
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	1019
T32	663	0
T33	402	0
T34	8402	0
T36	0	64
T39	0	42
T54	0	110
T56	0	86
T71	523	0
T93	0	34
T94	0	38
T154	0	168
T156	0	78
T220	589	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	6890910	6236444
T1	678	277
T2	915	514
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	104
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	6890910	65026
T13	604	43
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	0
T32	663	0
T33	402	0
T34	8402	0
T36	0	40
T54	0	39
T56	0	40
T71	523	0
T93	0	40
T94	0	89
T154	0	182
T156	0	40
T157	0	61
T193	0	83
T220	589	0

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	6890910	43
T13	604	1
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	0
T32	663	0
T33	402	0
T34	8402	0
T36	0	1
T54	0	2
T56	0	1
T71	523	0
T93	0	1
T94	0	2
T154	0	2
T156	0	1
T157	0	1
T193	0	2
T220	589	0

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	6890910	5821311
T1	678	3
T2	915	514
T3	25438	24982
T4	748	347
T5	254446	254045
T6	505	3
T7	21449	19005
T8	23338	22875
T24	9167	8766
T25	238296	237895

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	6890910	5823491
T1	678	3
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	3
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	6890910	46
T13	604	1
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	1
T32	663	0
T33	402	0
T34	8402	0
T36	0	1
T39	0	1
T54	0	2
T56	0	1
T71	523	0
T93	0	1
T94	0	2
T154	0	2
T156	0	1
T220	589	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	6890910	43
T13	604	1
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	0
T32	663	0
T33	402	0
T34	8402	0
T36	0	1
T54	0	2
T56	0	1
T71	523	0
T93	0	1
T94	0	2
T154	0	2
T156	0	1
T157	0	1
T193	0	2
T220	589	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	6890910	43
T13	604	1
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	0
T32	663	0
T33	402	0
T34	8402	0
T36	0	1
T54	0	2
T56	0	1
T71	523	0
T93	0	1
T94	0	2
T154	0	2
T156	0	1
T157	0	1
T193	0	2
T220	589	0

PulseIsPulse_A

Name	Attempts	Real Successes
Total	6890910	43
T13	604	1
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	0
T32	663	0
T33	402	0
T34	8402	0
T36	0	1
T54	0	2
T56	0	1
T71	523	0
T93	0	1
T94	0	2
T154	0	2
T156	0	1
T157	0	1
T193	0	2
T220	589	0

StayInStableSt

Name	Attempts	Real Successes
Total	6890910	64964
T13	604	41
T14	104160	0
T15	871	0
T16	1184	0
T17	53846	0
T32	663	0
T33	402	0
T34	8402	0
T36	0	39
T54	0	37
T56	0	38
T71	523	0
T93	0	39
T94	0	86
T154	0	180
T156	0	38
T157	0	59
T193	0	80
T220	589	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	6890910	6782
T1	678	0
T2	915	0
T3	25438	30
T4	748	3
T5	254446	6
T6	505	0
T7	21449	34
T8	23338	9
T24	9167	28
T25	238296	0
T26	0	4
T27	0	3
T28	0	3
T29	0	5

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	6890910	6238768
T1	678	278
T2	915	515
T3	25438	24991
T4	748	348
T5	254446	254046
T6	505	105
T7	21449	19016
T8	23338	22884
T24	9167	8767
T25	238296	237896

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	6890910	22
T36	9124	1
T37	245583	0
T38	899	0
T54	0	2
T55	13197	0
T63	722	0
T67	489	0
T68	496	0
T93	0	1
T94	0	1
T102	0	1
T140	447	0
T141	441	0
T142	422	0
T154	0	2
T159	0	1
T179	0	1
T193	0	1
T206	0	1

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children