Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T4,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T27,T28
1	0	Covered	T4,T5,T24
1	1	Covered	T4,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T27,T28
0	1	Covered	T90
1	0	Covered	T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T27,T28
0	1	Covered	T4,T27,T28
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T27,T28
1	-	Covered	T4,T27,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T27,T28
DetectSt	168	Covered	T4,T27,T28
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T27,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T27,T28
DebounceSt->IdleSt	163	Covered	T31,T62,T32
DetectSt->IdleSt	186	Covered	T90,T88
DetectSt->StableSt	191	Covered	T4,T27,T28
IdleSt->DebounceSt	148	Covered	T4,T27,T28
StableSt->IdleSt	206	Covered	T4,T27,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T27,T28
0	1	Covered	T4,T27,T28
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T27,T28
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T89
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T62,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T90,T88
DetectSt	-	-	-	-	0	1	-	Covered	T4,T27,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T27,T28
StableSt	-	-	-	-	-	-	0	Covered	T4,T27,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	265	0	0
CntIncr_A	6890910	327012	0	0
CntNoWrap_A	6890910	6236267	0	0
DetectStDropOut_A	6890910	1	0	0
DetectedOut_A	6890910	847	0	0
DetectedPulseOut_A	6890910	117	0	0
DisabledIdleSt_A	6890910	5903276	0	0
DisabledNoDetection_A	6890910	5905453	0	0
EnterDebounceSt_A	6890910	148	0	0
EnterDetectSt_A	6890910	119	0	0
EnterStableSt_A	6890910	117	0	0
PulseIsPulse_A	6890910	117	0	0
StayInStableSt	6890910	730	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6890910	6782	0	0
gen_low_level_sva.LowLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	117	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	265	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	2	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	2	0	0
T28	0	6	0	0
T31	0	5	0	0
T32	0	1	0	0
T35	0	6	0	0
T36	0	2	0	0
T39	0	2	0	0
T62	0	2	0	0
T63	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	327012	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	70	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	43	0	0
T28	0	157	0	0
T31	0	198	0	0
T32	0	65	0	0
T35	0	183	0	0
T36	0	73	0	0
T54	0	5425	0	0
T62	0	93	0	0
T63	0	129	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236267	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	345	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1	0	0
T87	963	0	0	0
T90	15719	1	0	0
T100	5217	0	0	0
T112	503	0	0	0
T113	432	0	0	0
T114	1449	0	0	0
T115	402	0	0	0
T116	425	0	0	0
T117	16631	0	0	0
T118	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	847	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	11	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	3	0	0
T28	0	9	0	0
T31	0	21	0	0
T35	0	10	0	0
T36	0	10	0	0
T39	0	12	0	0
T63	0	10	0	0
T119	0	19	0	0
T120	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	117	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T31	0	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T119	0	2	0	0
T120	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5903276	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	231	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5905453	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	231	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	148	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T31	0	3	0	0
T32	0	1	0	0
T35	0	3	0	0
T36	0	1	0	0
T54	0	1	0	0
T62	0	2	0	0
T63	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	119	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T31	0	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T119	0	2	0	0
T120	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	117	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T31	0	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T119	0	2	0	0
T120	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	117	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T31	0	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T119	0	2	0	0
T120	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	730	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	10	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	2	0	0
T28	0	6	0	0
T31	0	19	0	0
T35	0	7	0	0
T36	0	9	0	0
T39	0	11	0	0
T63	0	8	0	0
T119	0	17	0	0
T120	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6782	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	30	0	0
T4	748	3	0	0
T5	254446	6	0	0
T6	505	0	0	0
T7	21449	34	0	0
T8	23338	9	0	0
T24	9167	28	0	0
T25	238296	0	0	0
T26	0	4	0	0
T27	0	3	0	0
T28	0	3	0	0
T29	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	117	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	0	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T27	0	1	0	0
T28	0	3	0	0
T31	0	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T63	0	2	0	0
T119	0	2	0	0
T120	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T16,T17,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T23
1	0	Covered	T4,T5,T24
1	1	Covered	T16,T17,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T23
0	1	Covered	T40,T90,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T23
0	1	Unreachable
1	0	Covered	T16,T17,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T17,T23
DetectSt	168	Covered	T16,T17,T23
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T16,T17,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T17,T23
DebounceSt->IdleSt	163	Covered	T36,T42,T123
DetectSt->IdleSt	186	Covered	T40,T90,T96
DetectSt->StableSt	191	Covered	T16,T17,T23
IdleSt->DebounceSt	148	Covered	T16,T17,T23
StableSt->IdleSt	206	Covered	T16,T17,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T23
0	1	Covered	T16,T17,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T23
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T17,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T42,T123
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T23
DetectSt	-	-	-	-	1	-	-	Covered	T40,T90,T96
DetectSt	-	-	-	-	0	1	-	Covered	T16,T17,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T17,T23
StableSt	-	-	-	-	-	-	0	Covered	T16,T17,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	183	0	0
CntIncr_A	6890910	167953	0	0
CntNoWrap_A	6890910	6236349	0	0
DetectStDropOut_A	6890910	11	0	0
DetectedOut_A	6890910	354632	0	0
DetectedPulseOut_A	6890910	49	0	0
DisabledIdleSt_A	6890910	5422075	0	0
DisabledNoDetection_A	6890910	5424310	0	0
EnterDebounceSt_A	6890910	124	0	0
EnterDetectSt_A	6890910	60	0	0
EnterStableSt_A	6890910	49	0	0
PulseIsPulse_A	6890910	49	0	0
StayInStableSt	6890910	354583	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6890910	6782	0	0
gen_low_level_sva.LowLevelEvent_A	6890910	6238768	0	0
gen_sticky_sva.StableStDropOut_A	6890910	48124	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	183	0	0
T16	1184	2	0	0
T17	53846	2	0	0
T18	11510	0	0	0
T23	0	2	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	6	0	0
T42	0	4	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	167953	0	0
T16	1184	65	0	0
T17	53846	50	0	0
T18	11510	0	0	0
T23	0	71	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	116	0	0
T37	0	58639	0	0
T38	0	87	0	0
T39	0	63	0	0
T40	0	90	0	0
T41	0	165	0	0
T42	0	107	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236349	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	11	0	0
T40	921	1	0	0
T41	1717	0	0	0
T90	0	1	0	0
T94	563	0	0	0
T96	0	2	0	0
T127	0	1	0	0
T128	0	2	0	0
T129	0	1	0	0
T130	0	2	0	0
T131	0	1	0	0
T132	423	0	0	0
T133	28003	0	0	0
T134	522	0	0	0
T135	16421	0	0	0
T136	494	0	0	0
T137	493	0	0	0
T138	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	354632	0	0
T16	1184	51	0	0
T17	53846	47	0	0
T18	11510	0	0	0
T23	0	44	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T37	0	186436	0	0
T38	0	89	0	0
T39	0	134	0	0
T41	0	523	0	0
T42	0	200	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T124	0	329	0	0
T125	0	98722	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	49	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T124	0	1	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5422075	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5424310	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	124	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	4	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	3	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	60	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T124	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	49	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T124	0	1	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	49	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T124	0	1	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	354583	0	0
T16	1184	50	0	0
T17	53846	46	0	0
T18	11510	0	0	0
T23	0	43	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T37	0	186435	0	0
T38	0	88	0	0
T39	0	133	0	0
T41	0	520	0	0
T42	0	199	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T124	0	328	0	0
T125	0	98721	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6782	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	30	0	0
T4	748	3	0	0
T5	254446	6	0	0
T6	505	0	0	0
T7	21449	34	0	0
T8	23338	9	0	0
T24	9167	28	0	0
T25	238296	0	0	0
T26	0	4	0	0
T27	0	3	0	0
T28	0	3	0	0
T29	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	48124	0	0
T16	1184	39	0	0
T17	53846	31	0	0
T18	11510	0	0	0
T23	0	33	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T37	0	50	0	0
T38	0	44	0	0
T39	0	53	0	0
T41	0	490	0	0
T42	0	114	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T124	0	72	0	0
T125	0	41	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T16,T17,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T23
1	0	Covered	T5,T1,T2
1	1	Covered	T16,T17,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T23
0	1	Covered	T38,T42,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T23
0	1	Unreachable
1	0	Covered	T16,T17,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T17,T23
DetectSt	168	Covered	T16,T17,T23
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T16,T17,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T17,T23
DebounceSt->IdleSt	163	Covered	T42,T95,T125
DetectSt->IdleSt	186	Covered	T38,T42,T95
DetectSt->StableSt	191	Covered	T16,T17,T23
IdleSt->DebounceSt	148	Covered	T16,T17,T23
StableSt->IdleSt	206	Covered	T16,T17,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T23
0	1	Covered	T16,T17,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T23
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T17,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T95,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T23
DetectSt	-	-	-	-	1	-	-	Covered	T38,T42,T95
DetectSt	-	-	-	-	0	1	-	Covered	T16,T17,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T17,T23
StableSt	-	-	-	-	-	-	0	Covered	T16,T17,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	171	0	0
CntIncr_A	6890910	159259	0	0
CntNoWrap_A	6890910	6236361	0	0
DetectStDropOut_A	6890910	11	0	0
DetectedOut_A	6890910	8832	0	0
DetectedPulseOut_A	6890910	55	0	0
DisabledIdleSt_A	6890910	5422075	0	0
DisabledNoDetection_A	6890910	5424310	0	0
EnterDebounceSt_A	6890910	106	0	0
EnterDetectSt_A	6890910	66	0	0
EnterStableSt_A	6890910	55	0	0
PulseIsPulse_A	6890910	55	0	0
StayInStableSt	6890910	8777	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_sticky_sva.StableStDropOut_A	6890910	533961	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	171	0	0
T16	1184	2	0	0
T17	53846	2	0	0
T18	11510	0	0	0
T23	0	2	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	6	0	0
T42	0	11	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	159259	0	0
T16	1184	27	0	0
T17	53846	72	0	0
T18	11510	0	0	0
T23	0	91	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	30	0	0
T37	0	39	0	0
T38	0	44	0	0
T39	0	50	0	0
T40	0	27	0	0
T41	0	30	0	0
T42	0	84	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236361	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	11	0	0
T38	899	2	0	0
T42	0	5	0	0
T54	45616	0	0	0
T55	13197	0	0	0
T74	5167	0	0	0
T79	0	1	0	0
T95	0	2	0	0
T139	0	1	0	0
T140	447	0	0	0
T141	441	0	0	0
T142	422	0	0	0
T143	506	0	0	0
T144	422	0	0	0
T145	418	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	8832	0	0
T16	1184	4	0	0
T17	53846	2	0	0
T18	11510	0	0	0
T23	0	25	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	123	0	0
T37	0	190	0	0
T39	0	63	0	0
T40	0	18	0	0
T41	0	82	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T123	0	130	0	0
T124	0	213	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	55	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T123	0	1	0	0
T124	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5422075	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5424310	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	106	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	6	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	66	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	5	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	55	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T123	0	1	0	0
T124	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	55	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T123	0	1	0	0
T124	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	8777	0	0
T16	1184	3	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	24	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	122	0	0
T37	0	189	0	0
T39	0	62	0	0
T40	0	17	0	0
T41	0	79	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T123	0	129	0	0
T124	0	212	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	533961	0	0
T16	1184	128	0	0
T17	53846	58	0	0
T18	11510	0	0	0
T23	0	52	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	124	0	0
T37	0	244907	0	0
T39	0	134	0	0
T40	0	87	0	0
T41	0	1076	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T123	0	37186	0	0
T124	0	178	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T24

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T16,T17,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T17,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T23
1	0	Covered	T5,T1,T24
1	1	Covered	T16,T17,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T36,T37
0	1	Covered	T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T36,T37
0	1	Unreachable
1	0	Covered	T17,T36,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T17,T23
DetectSt	168	Covered	T17,T36,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T17,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T36,T37
DebounceSt->IdleSt	163	Covered	T16,T23,T41
DetectSt->IdleSt	186	Covered	T91,T92
DetectSt->StableSt	191	Covered	T17,T36,T37
IdleSt->DebounceSt	148	Covered	T16,T17,T23
StableSt->IdleSt	206	Covered	T17,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T17,T23
0	1	Covered	T16,T17,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T36,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T17,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T23,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T17,T23
DetectSt	-	-	-	-	1	-	-	Covered	T91,T92
DetectSt	-	-	-	-	0	1	-	Covered	T17,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T36,T37
StableSt	-	-	-	-	-	-	0	Covered	T17,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	172	0	0
CntIncr_A	6890910	31512	0	0
CntNoWrap_A	6890910	6236360	0	0
DetectStDropOut_A	6890910	5	0	0
DetectedOut_A	6890910	106578	0	0
DetectedPulseOut_A	6890910	52	0	0
DisabledIdleSt_A	6890910	5422075	0	0
DisabledNoDetection_A	6890910	5424310	0	0
EnterDebounceSt_A	6890910	116	0	0
EnterDetectSt_A	6890910	57	0	0
EnterStableSt_A	6890910	52	0	0
PulseIsPulse_A	6890910	52	0	0
StayInStableSt	6890910	106526	0	0
gen_high_event_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_sticky_sva.StableStDropOut_A	6890910	670281	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	172	0	0
T16	1184	1	0	0
T17	53846	2	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	7	0	0
T42	0	4	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	31512	0	0
T16	1184	37	0	0
T17	53846	64	0	0
T18	11510	0	0	0
T23	0	89	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	36	0	0
T37	0	99	0	0
T38	0	34	0	0
T39	0	48	0	0
T40	0	80	0	0
T41	0	567	0	0
T42	0	137	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236360	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5	0	0
T88	6976	0	0	0
T91	26836	2	0	0
T92	0	3	0	0
T146	60254	0	0	0
T147	8453	0	0	0
T148	25439	0	0	0
T149	914	0	0	0
T150	407	0	0	0
T151	27206	0	0	0
T152	623	0	0	0
T153	19836	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	106578	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	131	0	0
T37	0	238	0	0
T38	0	62	0	0
T39	0	128	0	0
T40	0	20	0	0
T42	0	376	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T72	2443	0	0	0
T95	0	357	0	0
T123	0	318	0	0
T124	0	323	0	0
T126	429	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	52	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T72	2443	0	0	0
T95	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T126	429	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5422075	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5424310	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	116	0	0
T16	1184	1	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T23	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	7	0	0
T42	0	2	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	57	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T72	2443	0	0	0
T95	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T126	429	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	52	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T72	2443	0	0	0
T95	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T126	429	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	52	0	0
T17	53846	1	0	0
T18	11510	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T72	2443	0	0	0
T95	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T126	429	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	106526	0	0
T36	9124	130	0	0
T37	245583	237	0	0
T38	899	61	0	0
T39	0	127	0	0
T40	0	19	0	0
T42	0	374	0	0
T55	13197	0	0	0
T63	722	0	0	0
T67	489	0	0	0
T68	496	0	0	0
T95	0	356	0	0
T123	0	317	0	0
T124	0	322	0	0
T125	0	155	0	0
T140	447	0	0	0
T141	441	0	0	0
T142	422	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	670281	0	0
T17	53846	69	0	0
T18	11510	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T36	0	118	0	0
T37	0	244807	0	0
T38	0	140	0	0
T39	0	86	0	0
T40	0	34	0	0
T42	0	126	0	0
T43	714	0	0	0
T44	1292	0	0	0
T45	452	0	0	0
T72	2443	0	0	0
T95	0	62	0	0
T123	0	36947	0	0
T124	0	60	0	0
T126	429	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T54,T39,T58

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T54,T39,T58

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T54,T39,T58

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T14
1	0	Covered	T4,T5,T1
1	1	Covered	T54,T39,T58

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T54,T39,T58
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T54,T39,T58
0	1	Covered	T54,T39,T58
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T54,T39,T58
1	-	Covered	T54,T39,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T54,T39,T58
DetectSt	168	Covered	T54,T39,T58
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T54,T39,T58

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T54,T39,T58
DebounceSt->IdleSt	163	Covered	T154,T155
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T54,T39,T58
IdleSt->DebounceSt	148	Covered	T54,T39,T58
StableSt->IdleSt	206	Covered	T54,T39,T58

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T54,T39,T58
0	1	Covered	T54,T39,T58
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T54,T39,T58
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T54,T39,T58
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T54,T39,T58
DebounceSt	-	0	1	0	-	-	-	Covered	T154,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T54,T39,T58
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T54,T39,T58
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T54,T39,T58
StableSt	-	-	-	-	-	-	0	Covered	T54,T39,T58
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	68	0	0
CntIncr_A	6890910	1964	0	0
CntNoWrap_A	6890910	6236464	0	0
DetectStDropOut_A	6890910	0	0	0
DetectedOut_A	6890910	2523	0	0
DetectedPulseOut_A	6890910	33	0	0
DisabledIdleSt_A	6890910	6100013	0	0
DisabledNoDetection_A	6890910	6102200	0	0
EnterDebounceSt_A	6890910	35	0	0
EnterDetectSt_A	6890910	33	0	0
EnterStableSt_A	6890910	33	0	0
PulseIsPulse_A	6890910	33	0	0
StayInStableSt	6890910	2474	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	68	0	0
T39	81238	2	0	0
T54	45616	4	0	0
T58	0	2	0	0
T91	0	2	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	2	0	0
T121	626	0	0	0
T154	0	3	0	0
T156	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	2	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1964	0	0
T39	81238	54	0	0
T54	45616	144	0	0
T58	0	59	0	0
T91	0	35	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	13	0	0
T121	626	0	0	0
T154	0	168	0	0
T156	0	156	0	0
T157	0	16	0	0
T158	0	56	0	0
T159	0	89	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236464	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2523	0	0
T39	81238	40	0	0
T54	45616	88	0	0
T58	0	44	0	0
T91	0	50	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	69	0	0
T121	626	0	0	0
T154	0	16	0	0
T156	0	82	0	0
T157	0	120	0	0
T158	0	42	0	0
T159	0	189	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	33	0	0
T39	81238	1	0	0
T54	45616	2	0	0
T58	0	1	0	0
T91	0	1	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	1	0	0
T121	626	0	0	0
T154	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6100013	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	3	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6102200	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	3	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	35	0	0
T39	81238	1	0	0
T54	45616	2	0	0
T58	0	1	0	0
T91	0	1	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	1	0	0
T121	626	0	0	0
T154	0	2	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	33	0	0
T39	81238	1	0	0
T54	45616	2	0	0
T58	0	1	0	0
T91	0	1	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	1	0	0
T121	626	0	0	0
T154	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	33	0	0
T39	81238	1	0	0
T54	45616	2	0	0
T58	0	1	0	0
T91	0	1	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	1	0	0
T121	626	0	0	0
T154	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	33	0	0
T39	81238	1	0	0
T54	45616	2	0	0
T58	0	1	0	0
T91	0	1	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	1	0	0
T121	626	0	0	0
T154	0	1	0	0
T156	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2474	0	0
T39	81238	39	0	0
T54	45616	85	0	0
T58	0	43	0	0
T91	0	48	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	68	0	0
T121	626	0	0	0
T154	0	15	0	0
T156	0	79	0	0
T157	0	118	0	0
T158	0	40	0	0
T159	0	187	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	15	0	0
T39	81238	1	0	0
T54	45616	1	0	0
T58	0	1	0	0
T97	17287	0	0	0
T98	502	0	0	0
T102	0	1	0	0
T121	626	0	0	0
T154	0	1	0	0
T156	0	1	0	0
T160	431	0	0	0
T161	404	0	0	0
T162	528	0	0	0
T163	409	0	0	0
T164	496	0	0	0
T165	0	1	0	0
T166	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T2,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T6,T3,T7
1	1	Covered	T1,T2,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T169,T170
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T39,T94,T42
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T13
1	-	Covered	T39,T94,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T13
DetectSt	168	Covered	T1,T2,T13
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T2,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T13
DebounceSt->IdleSt	163	Covered	T20,T56,T171
DetectSt->IdleSt	186	Covered	T169,T170
DetectSt->StableSt	191	Covered	T1,T2,T13
IdleSt->DebounceSt	148	Covered	T1,T2,T13
StableSt->IdleSt	206	Covered	T17,T18,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T13
0	1	Covered	T1,T2,T13
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T56,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T13
DetectSt	-	-	-	-	1	-	-	Covered	T169,T170
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T94,T42
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	131	0	0
CntIncr_A	6890910	136504	0	0
CntNoWrap_A	6890910	6236401	0	0
DetectStDropOut_A	6890910	2	0	0
DetectedOut_A	6890910	25431	0	0
DetectedPulseOut_A	6890910	61	0	0
DisabledIdleSt_A	6890910	5776857	0	0
DisabledNoDetection_A	6890910	5779040	0	0
EnterDebounceSt_A	6890910	69	0	0
EnterDetectSt_A	6890910	63	0	0
EnterStableSt_A	6890910	61	0	0
PulseIsPulse_A	6890910	61	0	0
StayInStableSt	6890910	25338	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6890910	2649	0	0
gen_low_level_sva.LowLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	131	0	0
T1	678	2	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T17	0	2	0	0
T18	0	2	0	0
T20	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	3	0	0
T64	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	136504	0	0
T1	678	98	0	0
T2	915	92	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	59	0	0
T14	0	46185	0	0
T15	0	81	0	0
T17	0	10282	0	0
T18	0	84	0	0
T20	0	10	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	172	0	0
T64	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236401	0	0
T1	678	275	0	0
T2	915	512	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2	0	0
T80	1320	0	0	0
T83	25445	0	0	0
T128	965	0	0	0
T169	609	1	0	0
T170	0	1	0	0
T173	403	0	0	0
T174	10445	0	0	0
T175	432	0	0	0
T176	1416	0	0	0
T177	503	0	0	0
T178	13759	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	25431	0	0
T1	678	171	0	0
T2	915	413	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	43	0	0
T14	0	42	0	0
T15	0	41	0	0
T17	0	3774	0	0
T18	0	167	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	192	0	0
T57	0	281	0	0
T64	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	61	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T64	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5776857	0	0
T1	678	3	0	0
T2	915	4	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5779040	0	0
T1	678	3	0	0
T2	915	4	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	69	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	2	0	0
T64	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	63	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T64	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	61	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T64	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	61	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T64	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	25338	0	0
T1	678	169	0	0
T2	915	411	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	41	0	0
T14	0	40	0	0
T15	0	39	0	0
T17	0	3772	0	0
T18	0	165	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	190	0	0
T57	0	279	0	0
T64	0	35	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2649	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	1	0	0
T7	21449	20	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	4	0	0
T29	0	6	0	0
T51	0	3	0	0
T52	0	6	0	0
T53	0	3	0	0
T70	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	27	0	0
T39	81238	2	0	0
T42	0	1	0	0
T75	7863	0	0	0
T76	10797	0	0	0
T91	0	1	0	0
T93	30947	0	0	0
T94	0	1	0	0
T121	626	0	0	0
T122	502	0	0	0
T159	0	1	0	0
T172	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	522	0	0	0
T184	438	0	0	0
T185	445	0	0	0
T186	495	0	0	0