Unified Coverage Report :: Module :: sysrst_ctrl_ulp

Module : sysrst_ctrl_ulp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_ulp	100.00	100.00	100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_ulp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.98	100.00	94.92		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_ulp

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	99	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
90	1	1
94	1	1
99	1	1

---

Cond Coverage for Module : sysrst_ctrl_ulp

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       90
 EXPRESSION (pwrb_det_pulse | lid_open_det_pulse | ac_present_det_pulse)
             -------1------   ---------2--------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T1
0	0	1	Covered	T17,T36,T37
0	1	0	Covered	T16,T17,T36
1	0	0	Covered	T16,T17,T37

 LINE       94
 EXPRESSION (pwrb_det | lid_open_det | ac_present_det)
             ----1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T1
0	0	1	Covered	T36,T38,T39
0	1	0	Covered	T16,T37,T40
1	0	0	Covered	T17,T42,T124