Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.48	100.00	96.95		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	89.69	91.30	90.48		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	89.77	91.30	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	97.18	95.65	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.77	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.69	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T7
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T3,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T7,T10,T53
1	0	Covered	T88,T89

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T60,T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T3,T7,T8

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.77	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T24
1	1	Covered	T4,T1,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T39,T90,T91
1	0	Covered	T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T2
0	1	Covered	T4,T1,T2
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T1,T2
1	-	Covered	T4,T1,T2

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T30
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T30
1	0	Covered	T3,T60,T55
1	1	Covered	T24,T3,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T59
0	1	Covered	T24,T30,T55
1	0	Covered	T55,T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T59
0	1	Covered	T24,T3,T59
1	0	Covered	T76,T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T3,T59
1	-	Covered	T24,T3,T59

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T24

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T17,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T23
1	0	Covered	T5,T1,T24
1	1	Covered	T16,T17,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T36,T37
0	1	Covered	T91,T92
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T36,T37
0	1	Unreachable
1	0	Covered	T17,T36,T37

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.69	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T2,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T56,T93,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T14,T56,T57
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T13
1	-	Covered	T14,T56,T57

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T23
1	0	Covered	T5,T1,T2
1	1	Covered	T16,T17,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T23
0	1	Covered	T38,T42,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T23
0	1	Unreachable
1	0	Covered	T16,T17,T23

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T16,T17,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T23
1	0	Covered	T4,T5,T24
1	1	Covered	T16,T17,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T23
0	1	Covered	T40,T90,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T23
0	1	Unreachable
1	0	Covered	T16,T17,T23

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T1,T2
DetectSt	168	Covered	T4,T1,T2
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T1,T2

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T1,T2
DebounceSt->IdleSt	163	Covered	T31,T62,T32
DetectSt->IdleSt	186	Covered	T38,T39,T93
DetectSt->StableSt	191	Covered	T4,T1,T2
IdleSt->DebounceSt	148	Covered	T4,T1,T2
StableSt->IdleSt	206	Covered	T4,T1,T2

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.77	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.69	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.18	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T1,T2
0	1	Covered	T4,T1,T2
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T1,T2
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T1,T2
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T62,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T1,T2
DetectSt	-	-	-	-	1	-	-	Covered	T38,T39,T93
DetectSt	-	-	-	-	0	1	-	Covered	T4,T1,T2
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T4,T1,T2
StableSt	-	-	-	-	-	-	0	Covered	T4,T1,T2
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T3,T30
0	1	Covered	T24,T3,T30
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T3,T30
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T24,T3,T30
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T3,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T30,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T3,T30
DetectSt	-	-	-	-	1	-	-	Covered	T24,T30,T55
DetectSt	-	-	-	-	0	1	-	Covered	T24,T3,T59
DetectSt	-	-	-	-	0	0	-	Covered	T24,T3,T59
StableSt	-	-	-	-	-	-	1	Covered	T24,T3,T59
StableSt	-	-	-	-	-	-	0	Covered	T24,T3,T59
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	179163660	17001	0	0
CntIncr_A	179163660	2499116	0	0
CntNoWrap_A	179163660	162132831	0	0
DetectStDropOut_A	179163660	1596	0	0
DetectedOut_A	179163660	1296904	0	0
DetectedPulseOut_A	179163660	5798	0	0
DisabledIdleSt_A	179163660	151478235	0	0
DisabledNoDetection_A	179163660	151532458	0	0
EnterDebounceSt_A	179163660	8900	0	0
EnterDetectSt_A	179163660	8127	0	0
EnterStableSt_A	179163660	5798	0	0
PulseIsPulse_A	179163660	5798	0	0
StayInStableSt	179163660	1290296	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	62018190	51016	0	0
gen_high_event_sva.HighLevelEvent_A	34454550	31193840	0	0
gen_high_level_sva.HighLevelEvent_A	117145470	106059056	0	0
gen_low_level_sva.LowLevelEvent_A	62018190	56148912	0	0
gen_not_sticky_sva.StableStDropOut_A	158490930	4778	0	0
gen_sticky_sva.StableStDropOut_A	20672730	1252366	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	17001	0	0
T1	1356	0	0	0
T2	5490	0	0	0
T3	203504	70	0	0
T4	748	2	0	0
T5	254446	0	0	0
T6	3030	0	0	0
T7	214490	4	0	0
T8	233380	0	0	0
T9	4392	2	0	0
T10	0	5	0	0
T12	0	13	0	0
T17	0	25	0	0
T19	0	8	0	0
T21	0	12	0	0
T24	55002	25	0	0
T25	1429776	0	0	0
T26	3942	0	0	0
T27	5664	2	0	0
T28	5844	6	0	0
T29	1788	0	0	0
T30	20268	0	0	0
T31	2940	5	0	0
T32	0	1	0	0
T35	0	6	0	0
T36	0	2	0	0
T39	0	2	0	0
T44	0	1	0	0
T51	994	0	0	0
T53	0	18	0	0
T54	45616	0	0	0
T62	0	2	0	0
T63	0	4	0	0
T97	17287	0	0	0
T98	502	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	2499116	0	0
T1	1356	0	0	0
T2	5490	0	0	0
T3	203504	2487	0	0
T4	748	70	0	0
T5	254446	0	0	0
T6	3030	0	0	0
T7	214490	241	0	0
T8	233380	0	0	0
T9	4392	25	0	0
T10	0	262	0	0
T12	0	769	0	0
T17	0	1358	0	0
T18	0	20	0	0
T19	0	520	0	0
T24	55002	3777	0	0
T25	1429776	0	0	0
T26	3942	0	0	0
T27	5664	43	0	0
T28	5844	157	0	0
T29	1788	0	0	0
T30	20268	0	0	0
T31	2940	198	0	0
T32	0	65	0	0
T35	0	183	0	0
T36	0	73	0	0
T44	0	20	0	0
T51	994	0	0	0
T53	0	1211	0	0
T54	45616	5425	0	0
T62	0	93	0	0
T63	0	129	0	0
T97	17287	0	0	0
T98	502	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	162132831	0	0
T1	17628	7196	0	0
T2	23790	13348	0	0
T3	661388	649410	0	0
T4	19448	9020	0	0
T5	6615596	6605170	0	0
T6	13130	2704	0	0
T7	557674	494104	0	0
T8	606788	594724	0	0
T24	238342	227832	0	0
T25	6195696	6185270	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	1596	0	0
T7	21449	2	0	0
T8	23338	0	0	0
T9	488	0	0	0
T17	0	7	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	10134	8	0	0
T31	1470	0	0	0
T49	1311	0	0	0
T51	994	0	0	0
T74	0	11	0	0
T87	963	0	0	0
T88	0	1	0	0
T90	15719	1	0	0
T91	0	10	0	0
T93	0	1	0	0
T99	0	1	0	0
T100	5217	8	0	0
T101	0	11	0	0
T102	0	1	0	0
T103	0	4	0	0
T104	0	25	0	0
T105	0	3	0	0
T106	0	11	0	0
T107	0	2	0	0
T108	0	3	0	0
T109	0	5	0	0
T110	0	8	0	0
T111	0	2	0	0
T112	503	0	0	0
T113	432	0	0	0
T114	1449	0	0	0
T115	402	0	0	0
T116	425	0	0	0
T117	16631	0	0	0
T118	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	1296904	0	0
T1	1356	0	0	0
T2	2745	0	0	0
T3	203504	3064	0	0
T4	748	11	0	0
T5	254446	0	0	0
T6	1515	0	0	0
T7	214490	0	0	0
T8	233380	0	0	0
T9	4392	3	0	0
T10	0	12	0	0
T12	0	379	0	0
T17	0	117	0	0
T19	0	321	0	0
T21	0	56	0	0
T22	0	3	0	0
T24	27501	303	0	0
T25	714888	0	0	0
T26	3942	0	0	0
T27	5664	3	0	0
T28	10227	9	0	0
T29	3129	0	0	0
T30	35469	0	0	0
T31	5145	21	0	0
T35	0	10	0	0
T36	0	10	0	0
T39	0	12	0	0
T51	994	0	0	0
T53	0	82	0	0
T54	45616	0	0	0
T60	0	323	0	0
T63	0	10	0	0
T97	17287	0	0	0
T98	502	0	0	0
T119	0	19	0	0
T120	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	5798	0	0
T1	1356	0	0	0
T2	2745	0	0	0
T3	203504	35	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	1515	0	0	0
T7	214490	0	0	0
T8	233380	0	0	0
T9	4392	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	5	0	0
T19	0	4	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	27501	8	0	0
T25	714888	0	0	0
T26	3942	0	0	0
T27	5664	1	0	0
T28	10227	3	0	0
T29	3129	0	0	0
T30	35469	0	0	0
T31	5145	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T51	994	0	0	0
T53	0	8	0	0
T54	45616	0	0	0
T60	0	15	0	0
T63	0	2	0	0
T97	17287	0	0	0
T98	502	0	0	0
T119	0	2	0	0
T120	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	151478235	0	0
T1	17628	5558	0	0
T2	23790	9794	0	0
T3	661388	625128	0	0
T4	19448	8906	0	0
T5	6615596	6605170	0	0
T6	13130	2300	0	0
T7	557674	476350	0	0
T8	606788	580512	0	0
T24	238342	200609	0	0
T25	6195696	6185270	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	151532458	0	0
T1	17628	5578	0	0
T2	23790	9813	0	0
T3	661388	625340	0	0
T4	19448	8931	0	0
T5	6615596	6605196	0	0
T6	13130	2322	0	0
T7	557674	476608	0	0
T8	606788	580719	0	0
T24	238342	200631	0	0
T25	6195696	6185296	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	8900	0	0
T1	1356	0	0	0
T2	5490	0	0	0
T3	203504	35	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	3030	0	0	0
T7	214490	2	0	0
T8	233380	0	0	0
T9	4392	1	0	0
T10	0	3	0	0
T12	0	7	0	0
T17	0	13	0	0
T18	0	1	0	0
T19	0	4	0	0
T24	55002	17	0	0
T25	1429776	0	0	0
T26	3942	0	0	0
T27	5664	1	0	0
T28	5844	3	0	0
T29	1788	0	0	0
T30	20268	0	0	0
T31	2940	3	0	0
T32	0	1	0	0
T35	0	3	0	0
T36	0	1	0	0
T44	0	1	0	0
T51	994	0	0	0
T53	0	10	0	0
T54	45616	1	0	0
T62	0	2	0	0
T63	0	2	0	0
T97	17287	0	0	0
T98	502	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	8127	0	0
T1	1356	0	0	0
T2	4575	0	0	0
T3	203504	35	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	2525	0	0	0
T7	214490	2	0	0
T8	233380	0	0	0
T9	4392	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	12	0	0
T19	0	4	0	0
T21	0	6	0	0
T24	45835	8	0	0
T25	1191480	0	0	0
T26	3942	0	0	0
T27	5664	1	0	0
T28	7305	3	0	0
T29	2235	0	0	0
T30	25335	0	0	0
T31	3675	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T51	994	0	0	0
T53	0	8	0	0
T54	45616	0	0	0
T60	0	15	0	0
T63	0	2	0	0
T97	17287	0	0	0
T98	502	0	0	0
T119	0	2	0	0
T120	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	5798	0	0
T1	1356	0	0	0
T2	2745	0	0	0
T3	203504	35	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	1515	0	0	0
T7	214490	0	0	0
T8	233380	0	0	0
T9	4392	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	5	0	0
T19	0	4	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	27501	8	0	0
T25	714888	0	0	0
T26	3942	0	0	0
T27	5664	1	0	0
T28	10227	3	0	0
T29	3129	0	0	0
T30	35469	0	0	0
T31	5145	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T51	994	0	0	0
T53	0	8	0	0
T54	45616	0	0	0
T60	0	15	0	0
T63	0	2	0	0
T97	17287	0	0	0
T98	502	0	0	0
T119	0	2	0	0
T120	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	5798	0	0
T1	1356	0	0	0
T2	2745	0	0	0
T3	203504	35	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	1515	0	0	0
T7	214490	0	0	0
T8	233380	0	0	0
T9	4392	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	5	0	0
T19	0	4	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	27501	8	0	0
T25	714888	0	0	0
T26	3942	0	0	0
T27	5664	1	0	0
T28	10227	3	0	0
T29	3129	0	0	0
T30	35469	0	0	0
T31	5145	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	0	1	0	0
T51	994	0	0	0
T53	0	8	0	0
T54	45616	0	0	0
T60	0	15	0	0
T63	0	2	0	0
T97	17287	0	0	0
T98	502	0	0	0
T119	0	2	0	0
T120	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	179163660	1290296	0	0
T1	1356	0	0	0
T2	2745	0	0	0
T3	203504	3021	0	0
T4	748	10	0	0
T5	254446	0	0	0
T6	1515	0	0	0
T7	214490	0	0	0
T8	233380	0	0	0
T9	4392	2	0	0
T10	0	10	0	0
T12	0	373	0	0
T17	0	112	0	0
T19	0	317	0	0
T21	0	50	0	0
T22	0	2	0	0
T24	27501	295	0	0
T25	714888	0	0	0
T26	3942	0	0	0
T27	5664	2	0	0
T28	10227	6	0	0
T29	3129	0	0	0
T30	35469	0	0	0
T31	5145	19	0	0
T35	0	7	0	0
T36	0	9	0	0
T39	0	11	0	0
T51	994	0	0	0
T53	0	74	0	0
T54	45616	0	0	0
T60	0	306	0	0
T63	0	8	0	0
T97	17287	0	0	0
T98	502	0	0	0
T119	0	17	0	0
T120	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62018190	51016	0	0
T1	4068	2	0	0
T2	8235	3	0	0
T3	228942	150	0	0
T4	2244	3	0	0
T5	1017784	12	0	0
T6	4545	4	0	0
T7	193041	190	0	0
T8	210042	57	0	0
T9	2440	3	0	0
T10	0	12	0	0
T24	82503	134	0	0
T25	2144664	5	0	0
T26	2628	31	0	0
T27	2124	3	0	0
T28	0	3	0	0
T29	0	36	0	0
T30	0	98	0	0
T51	0	35	0	0
T52	0	11	0	0
T53	0	8	0	0
T70	0	3	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34454550	31193840	0	0
T1	3390	1390	0	0
T2	4575	2575	0	0
T3	127190	124955	0	0
T4	3740	1740	0	0
T5	1272230	1270230	0	0
T6	2525	525	0	0
T7	107245	95080	0	0
T8	116690	114420	0	0
T24	45835	43835	0	0
T25	1191480	1189480	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117145470	106059056	0	0
T1	11526	4726	0	0
T2	15555	8755	0	0
T3	432446	424847	0	0
T4	12716	5916	0	0
T5	4325582	4318782	0	0
T6	8585	1785	0	0
T7	364633	323272	0	0
T8	396746	389028	0	0
T24	155839	149039	0	0
T25	4051032	4044232	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62018190	56148912	0	0
T1	6102	2502	0	0
T2	8235	4635	0	0
T3	228942	224919	0	0
T4	6732	3132	0	0
T5	2290014	2286414	0	0
T6	4545	945	0	0
T7	193041	171144	0	0
T8	210042	205956	0	0
T24	82503	78903	0	0
T25	2144664	2141064	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158490930	4778	0	0
T1	678	0	0	0
T2	1830	0	0	0
T3	178066	27	0	0
T4	748	1	0	0
T5	254446	0	0	0
T6	1010	0	0	0
T7	193041	0	0	0
T8	210042	0	0	0
T9	3904	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	5	0	0
T19	0	4	0	0
T21	0	6	0	0
T22	0	1	0	0
T24	18334	8	0	0
T25	476592	0	0	0
T26	3504	0	0	0
T27	5664	1	0	0
T28	10227	3	0	0
T29	3129	0	0	0
T30	35469	0	0	0
T31	5145	2	0	0
T35	0	3	0	0
T36	0	1	0	0
T39	81238	1	0	0
T51	994	0	0	0
T53	0	7	0	0
T63	0	2	0	0
T65	0	1	0	0
T119	0	2	0	0
T120	0	2	0	0
T121	626	0	0	0
T122	502	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20672730	1252366	0	0
T16	2368	167	0	0
T17	161538	158	0	0
T18	34530	0	0	0
T23	0	85	0	0
T32	1326	0	0	0
T33	1206	0	0	0
T34	25206	0	0	0
T35	2094	0	0	0
T36	0	242	0	0
T37	0	489764	0	0
T38	0	184	0	0
T39	0	273	0	0
T40	0	121	0	0
T41	0	1566	0	0
T42	0	240	0	0
T43	2142	0	0	0
T44	3876	0	0	0
T45	1356	0	0	0
T72	2443	0	0	0
T95	0	62	0	0
T123	0	74133	0	0
T124	0	310	0	0
T125	0	41	0	0
T126	429	0	0	0