Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T13,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T13,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T13,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T13,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T18
0	1	Covered	T93,T181,T187
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T13,T18
0	1	Covered	T188,T154,T157
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T13,T18
1	-	Covered	T188,T154,T157

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T18
DetectSt	168	Covered	T2,T13,T18
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T13,T18

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T13,T18
DebounceSt->IdleSt	163	Covered	T94,T189
DetectSt->IdleSt	186	Covered	T93,T181,T187
DetectSt->StableSt	191	Covered	T2,T13,T18
IdleSt->DebounceSt	148	Covered	T2,T13,T18
StableSt->IdleSt	206	Covered	T18,T39,T188

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T13,T18
0	1	Covered	T2,T13,T18
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T18
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T18
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T13,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T94,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T18
DetectSt	-	-	-	-	1	-	-	Covered	T93,T181,T187
DetectSt	-	-	-	-	0	1	-	Covered	T2,T13,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T188,T154,T157
StableSt	-	-	-	-	-	-	0	Covered	T2,T13,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	66	0	0
CntIncr_A	6890910	1909	0	0
CntNoWrap_A	6890910	6236466	0	0
DetectStDropOut_A	6890910	3	0	0
DetectedOut_A	6890910	1525	0	0
DetectedPulseOut_A	6890910	29	0	0
DisabledIdleSt_A	6890910	6203611	0	0
DisabledNoDetection_A	6890910	6205798	0	0
EnterDebounceSt_A	6890910	34	0	0
EnterDetectSt_A	6890910	32	0	0
EnterStableSt_A	6890910	29	0	0
PulseIsPulse_A	6890910	29	0	0
StayInStableSt	6890910	1481	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	66	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	2	0	0
T18	0	2	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	2	0	0
T57	0	2	0	0
T93	0	2	0	0
T94	0	1	0	0
T154	0	4	0	0
T156	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1909	0	0
T2	915	92	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	59	0	0
T18	0	84	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	42	0	0
T57	0	48	0	0
T93	0	34	0	0
T94	0	19	0	0
T154	0	168	0	0
T156	0	78	0	0
T188	0	73	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236466	0	0
T1	678	277	0	0
T2	915	512	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	3	0	0
T40	921	0	0	0
T61	14215	0	0	0
T76	10797	0	0	0
T93	30947	1	0	0
T132	423	0	0	0
T133	28003	0	0	0
T134	522	0	0	0
T181	0	1	0	0
T186	495	0	0	0
T187	0	1	0	0
T188	7043	0	0	0
T190	2248	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1525	0	0
T2	915	43	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	42	0	0
T18	0	41	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	46	0	0
T57	0	42	0	0
T114	0	51	0	0
T154	0	182	0	0
T156	0	40	0	0
T157	0	82	0	0
T188	0	160	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	29	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T57	0	1	0	0
T114	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T157	0	2	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6203611	0	0
T1	678	277	0	0
T2	915	4	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6205798	0	0
T1	678	278	0	0
T2	915	4	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	34	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T57	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	32	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T57	0	1	0	0
T93	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T157	0	2	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	29	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T57	0	1	0	0
T114	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T157	0	2	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	29	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T18	0	1	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T57	0	1	0	0
T114	0	1	0	0
T154	0	2	0	0
T156	0	1	0	0
T157	0	2	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1481	0	0
T2	915	41	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	40	0	0
T18	0	39	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	44	0	0
T57	0	40	0	0
T114	0	49	0	0
T154	0	180	0	0
T156	0	38	0	0
T157	0	79	0	0
T188	0	159	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	12	0	0
T40	921	0	0	0
T41	1717	0	0	0
T94	563	0	0	0
T132	423	0	0	0
T133	28003	0	0	0
T134	522	0	0	0
T135	16421	0	0	0
T136	494	0	0	0
T137	493	0	0	0
T154	0	2	0	0
T157	0	1	0	0
T159	0	1	0	0
T167	0	1	0	0
T172	0	1	0	0
T180	0	1	0	0
T187	0	1	0	0
T188	7043	1	0	0
T191	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T2,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T25,T6,T3
1	1	Covered	T1,T2,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T14
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T14
0	1	Covered	T1,T2,T18
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T14
1	-	Covered	T1,T2,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T14
DetectSt	168	Covered	T1,T2,T14
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T2,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T14
DebounceSt->IdleSt	163	Covered	T180
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T2,T14
IdleSt->DebounceSt	148	Covered	T1,T2,T14
StableSt->IdleSt	206	Covered	T1,T2,T18

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T14
0	1	Covered	T1,T2,T14
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T14
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T14
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T180
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T14
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T18
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	115	0	0
CntIncr_A	6890910	130854	0	0
CntNoWrap_A	6890910	6236417	0	0
DetectStDropOut_A	6890910	0	0	0
DetectedOut_A	6890910	66745	0	0
DetectedPulseOut_A	6890910	57	0	0
DisabledIdleSt_A	6890910	5833833	0	0
DisabledNoDetection_A	6890910	5836022	0	0
EnterDebounceSt_A	6890910	58	0	0
EnterDetectSt_A	6890910	57	0	0
EnterStableSt_A	6890910	57	0	0
PulseIsPulse_A	6890910	57	0	0
StayInStableSt	6890910	66666	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6890910	3018	0	0
gen_low_level_sva.LowLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	115	0	0
T1	678	2	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T14	0	2	0	0
T18	0	2	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	4	0	0
T56	0	2	0	0
T90	0	4	0	0
T93	0	4	0	0
T94	0	4	0	0
T193	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	130854	0	0
T1	678	98	0	0
T2	915	92	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T14	0	46185	0	0
T18	0	84	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	118	0	0
T56	0	86	0	0
T90	0	44	0	0
T93	0	68	0	0
T94	0	38	0	0
T193	0	23	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236417	0	0
T1	678	275	0	0
T2	915	512	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	66745	0	0
T1	678	28	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T14	0	42	0	0
T18	0	40	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	253	0	0
T56	0	43	0	0
T90	0	10	0	0
T93	0	253	0	0
T94	0	89	0	0
T193	0	72	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	57	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	2	0	0
T56	0	1	0	0
T90	0	2	0	0
T93	0	2	0	0
T94	0	2	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5833833	0	0
T1	678	3	0	0
T2	915	4	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5836022	0	0
T1	678	3	0	0
T2	915	4	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	58	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	2	0	0
T56	0	1	0	0
T90	0	2	0	0
T93	0	2	0	0
T94	0	2	0	0
T193	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	57	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	2	0	0
T56	0	1	0	0
T90	0	2	0	0
T93	0	2	0	0
T94	0	2	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	57	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	2	0	0
T56	0	1	0	0
T90	0	2	0	0
T93	0	2	0	0
T94	0	2	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	57	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T14	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	2	0	0
T56	0	1	0	0
T90	0	2	0	0
T93	0	2	0	0
T94	0	2	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	66666	0	0
T1	678	27	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T14	0	40	0	0
T18	0	39	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	250	0	0
T56	0	42	0	0
T90	0	8	0	0
T93	0	250	0	0
T94	0	86	0	0
T193	0	71	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	3018	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	1	0	0
T7	21449	18	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	0	0	0
T25	238296	5	0	0
T26	438	4	0	0
T29	0	6	0	0
T51	0	6	0	0
T52	0	5	0	0
T53	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	33	0	0
T1	678	1	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	1	0	0
T56	0	1	0	0
T90	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T1,T24

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T1,T24
1	1	Covered	T5,T1,T24

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T13,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T13,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T13,T14

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T13
1	0	Covered	T5,T24,T2
1	1	Covered	T1,T13,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T14
0	1	Covered	T195,T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T14
0	1	Covered	T14,T56,T57
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T13,T14
1	-	Covered	T14,T56,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T13,T14
DetectSt	168	Covered	T1,T13,T14
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T13,T14

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T13,T14
DebounceSt->IdleSt	163	Covered	T17,T20,T194
DetectSt->IdleSt	186	Covered	T195,T196
DetectSt->StableSt	191	Covered	T1,T13,T14
IdleSt->DebounceSt	148	Covered	T1,T13,T14
StableSt->IdleSt	206	Covered	T14,T18,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T13,T14
0	1	Covered	T1,T13,T14
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T14
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T13,T14
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T24
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T13,T14
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T194,T191
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T13,T14
DetectSt	-	-	-	-	1	-	-	Covered	T195,T196
DetectSt	-	-	-	-	0	1	-	Covered	T1,T13,T14
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T56,T57
StableSt	-	-	-	-	-	-	0	Covered	T1,T13,T14
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	127	0	0
CntIncr_A	6890910	214289	0	0
CntNoWrap_A	6890910	6236405	0	0
DetectStDropOut_A	6890910	2	0	0
DetectedOut_A	6890910	79139	0	0
DetectedPulseOut_A	6890910	57	0	0
DisabledIdleSt_A	6890910	5760524	0	0
DisabledNoDetection_A	6890910	5762706	0	0
EnterDebounceSt_A	6890910	69	0	0
EnterDetectSt_A	6890910	59	0	0
EnterStableSt_A	6890910	57	0	0
PulseIsPulse_A	6890910	57	0	0
StayInStableSt	6890910	79058	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	127	0	0
T1	678	2	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T18	0	2	0	0
T20	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T54	0	4	0	0
T56	0	4	0	0
T57	0	2	0	0
T64	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	214289	0	0
T1	678	98	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	59	0	0
T14	0	46185	0	0
T15	0	81	0	0
T17	0	1019	0	0
T18	0	84	0	0
T20	0	10	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	172	0	0
T57	0	48	0	0
T64	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236405	0	0
T1	678	275	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2	0	0
T106	5416	0	0	0
T107	4982	0	0	0
T195	1054	1	0	0
T196	0	1	0	0
T197	423	0	0	0
T198	728	0	0	0
T199	509	0	0	0
T200	873	0	0	0
T201	77314	0	0	0
T202	27935	0	0	0
T203	37892	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	79139	0	0
T1	678	171	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	43	0	0
T14	0	11338	0	0
T15	0	42	0	0
T18	0	41	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	165	0	0
T54	0	143	0	0
T56	0	84	0	0
T57	0	135	0	0
T64	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	57	0	0
T1	678	1	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	2	0	0
T54	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T64	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5760524	0	0
T1	678	3	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5762706	0	0
T1	678	3	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	69	0	0
T1	678	1	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T20	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T64	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	59	0	0
T1	678	1	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	2	0	0
T54	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T64	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	57	0	0
T1	678	1	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	2	0	0
T54	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T64	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	57	0	0
T1	678	1	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T18	0	1	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	2	0	0
T54	0	2	0	0
T56	0	2	0	0
T57	0	1	0	0
T64	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	79058	0	0
T1	678	169	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T13	0	41	0	0
T14	0	11337	0	0
T15	0	40	0	0
T18	0	39	0	0
T24	9167	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T39	0	162	0	0
T54	0	141	0	0
T56	0	81	0	0
T57	0	134	0	0
T64	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	31	0	0
T14	104160	1	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	1	0	0
T43	714	0	0	0
T54	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T114	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T24
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T24
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T14,T20,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T14,T20,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T14,T20,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T13
1	0	Covered	T5,T24,T6
1	1	Covered	T14,T20,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T20,T54
0	1	Covered	T39
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T20,T54
0	1	Covered	T93,T188,T90
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T20,T54
1	-	Covered	T93,T188,T90

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T20,T54
DetectSt	168	Covered	T14,T20,T54
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T14,T20,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T20,T54
DebounceSt->IdleSt	163	Covered	T156,T205
DetectSt->IdleSt	186	Covered	T39
DetectSt->StableSt	191	Covered	T14,T20,T54
IdleSt->DebounceSt	148	Covered	T14,T20,T54
StableSt->IdleSt	206	Covered	T20,T54,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T20,T54
0	1	Covered	T14,T20,T54
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T20,T54
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T20,T54
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T20,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T156
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T20,T54
DetectSt	-	-	-	-	1	-	-	Covered	T39
DetectSt	-	-	-	-	0	1	-	Covered	T14,T20,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T93,T188,T90
StableSt	-	-	-	-	-	-	0	Covered	T14,T20,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	91	0	0
CntIncr_A	6890910	92777	0	0
CntNoWrap_A	6890910	6236441	0	0
DetectStDropOut_A	6890910	1	0	0
DetectedOut_A	6890910	2585	0	0
DetectedPulseOut_A	6890910	44	0	0
DisabledIdleSt_A	6890910	5986790	0	0
DisabledNoDetection_A	6890910	5988967	0	0
EnterDebounceSt_A	6890910	47	0	0
EnterDetectSt_A	6890910	45	0	0
EnterStableSt_A	6890910	44	0	0
PulseIsPulse_A	6890910	44	0	0
StayInStableSt	6890910	2517	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6890910	6491	0	0
gen_low_level_sva.LowLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	91	0	0
T14	104160	2	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T20	0	2	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	4	0	0
T43	714	0	0	0
T54	0	4	0	0
T90	0	6	0	0
T93	0	2	0	0
T114	0	2	0	0
T156	0	1	0	0
T157	0	2	0	0
T188	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	92777	0	0
T14	104160	46185	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T20	0	10	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	114	0	0
T43	714	0	0	0
T54	0	86	0	0
T90	0	66	0	0
T93	0	34	0	0
T114	0	31	0	0
T156	0	67	0	0
T157	0	16	0	0
T188	0	146	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236441	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1	0	0
T39	81238	1	0	0
T75	7863	0	0	0
T76	10797	0	0	0
T93	30947	0	0	0
T121	626	0	0	0
T122	502	0	0	0
T183	522	0	0	0
T184	438	0	0	0
T185	445	0	0	0
T186	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2585	0	0
T14	104160	41	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T20	0	44	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	38	0	0
T43	714	0	0	0
T54	0	124	0	0
T87	0	59	0	0
T90	0	130	0	0
T93	0	40	0	0
T114	0	51	0	0
T157	0	60	0	0
T188	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	44	0	0
T14	104160	1	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T20	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	1	0	0
T43	714	0	0	0
T54	0	2	0	0
T87	0	1	0	0
T90	0	3	0	0
T93	0	1	0	0
T114	0	1	0	0
T157	0	1	0	0
T188	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5986790	0	0
T1	678	3	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5988967	0	0
T1	678	3	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	47	0	0
T14	104160	1	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T20	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	2	0	0
T43	714	0	0	0
T54	0	2	0	0
T90	0	3	0	0
T93	0	1	0	0
T114	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T188	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	45	0	0
T14	104160	1	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T20	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	2	0	0
T43	714	0	0	0
T54	0	2	0	0
T87	0	1	0	0
T90	0	3	0	0
T93	0	1	0	0
T114	0	1	0	0
T157	0	1	0	0
T188	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	44	0	0
T14	104160	1	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T20	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	1	0	0
T43	714	0	0	0
T54	0	2	0	0
T87	0	1	0	0
T90	0	3	0	0
T93	0	1	0	0
T114	0	1	0	0
T157	0	1	0	0
T188	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	44	0	0
T14	104160	1	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T20	0	1	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	1	0	0
T43	714	0	0	0
T54	0	2	0	0
T87	0	1	0	0
T90	0	3	0	0
T93	0	1	0	0
T114	0	1	0	0
T157	0	1	0	0
T188	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2517	0	0
T14	104160	39	0	0
T15	871	0	0	0
T16	1184	0	0	0
T17	53846	0	0	0
T18	11510	0	0	0
T20	0	42	0	0
T32	663	0	0	0
T33	402	0	0	0
T34	8402	0	0	0
T35	698	0	0	0
T39	0	36	0	0
T43	714	0	0	0
T54	0	120	0	0
T87	0	57	0	0
T90	0	126	0	0
T93	0	39	0	0
T114	0	49	0	0
T157	0	58	0	0
T188	0	98	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6491	0	0
T1	678	0	0	0
T2	915	0	0	0
T3	25438	33	0	0
T5	254446	6	0	0
T6	505	1	0	0
T7	21449	28	0	0
T8	23338	10	0	0
T24	9167	24	0	0
T25	238296	0	0	0
T26	438	4	0	0
T29	0	5	0	0
T30	0	27	0	0
T51	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	18	0	0
T40	921	0	0	0
T61	14215	0	0	0
T76	10797	0	0	0
T90	0	2	0	0
T91	0	1	0	0
T93	30947	1	0	0
T132	423	0	0	0
T133	28003	0	0	0
T134	522	0	0	0
T155	0	1	0	0
T159	0	2	0	0
T172	0	1	0	0
T186	495	0	0	0
T188	7043	1	0	0
T190	2248	0	0	0
T195	0	1	0	0
T206	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T24,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T24,T2
1	1	Covered	T1,T24,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T57,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T57,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T57,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T18
1	0	Covered	T1,T24,T6
1	1	Covered	T2,T57,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T57,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T57,T36
0	1	Covered	T2,T57,T54
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T57,T36
1	-	Covered	T2,T57,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T57,T36
DetectSt	168	Covered	T2,T57,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T57,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T57,T36
DebounceSt->IdleSt	163	Covered	T159,T171,T208
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T57,T36
IdleSt->DebounceSt	148	Covered	T2,T57,T36
StableSt->IdleSt	206	Covered	T2,T57,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T57,T36
0	1	Covered	T2,T57,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T57,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T57,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T24,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T57,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T159,T208
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T57,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T57,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T57,T54
StableSt	-	-	-	-	-	-	0	Covered	T2,T57,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	128	0	0
CntIncr_A	6890910	55637	0	0
CntNoWrap_A	6890910	6236404	0	0
DetectStDropOut_A	6890910	0	0	0
DetectedOut_A	6890910	68228	0	0
DetectedPulseOut_A	6890910	63	0	0
DisabledIdleSt_A	6890910	5901439	0	0
DisabledNoDetection_A	6890910	5903623	0	0
EnterDebounceSt_A	6890910	66	0	0
EnterDetectSt_A	6890910	63	0	0
EnterStableSt_A	6890910	63	0	0
PulseIsPulse_A	6890910	63	0	0
StayInStableSt	6890910	68132	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	128	0	0
T2	915	4	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T36	0	2	0	0
T39	0	4	0	0
T54	0	8	0	0
T57	0	2	0	0
T58	0	4	0	0
T90	0	4	0	0
T94	0	2	0	0
T156	0	2	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	55637	0	0
T2	915	184	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T36	0	64	0	0
T39	0	96	0	0
T54	0	230	0	0
T57	0	48	0	0
T58	0	118	0	0
T90	0	41	0	0
T94	0	19	0	0
T156	0	78	0	0
T194	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236404	0	0
T1	678	277	0	0
T2	915	510	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	68228	0	0
T2	915	184	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T36	0	378	0	0
T39	0	82	0	0
T54	0	478	0	0
T57	0	134	0	0
T58	0	197	0	0
T90	0	204	0	0
T94	0	69	0	0
T156	0	40	0	0
T194	0	91	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	63	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T54	0	4	0	0
T57	0	1	0	0
T58	0	2	0	0
T90	0	2	0	0
T94	0	1	0	0
T156	0	1	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5901439	0	0
T1	678	277	0	0
T2	915	4	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5903623	0	0
T1	678	278	0	0
T2	915	4	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	66	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T54	0	4	0	0
T57	0	1	0	0
T58	0	2	0	0
T90	0	2	0	0
T94	0	1	0	0
T156	0	1	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	63	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T54	0	4	0	0
T57	0	1	0	0
T58	0	2	0	0
T90	0	2	0	0
T94	0	1	0	0
T156	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	63	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T54	0	4	0	0
T57	0	1	0	0
T58	0	2	0	0
T90	0	2	0	0
T94	0	1	0	0
T156	0	1	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	63	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T36	0	1	0	0
T39	0	2	0	0
T54	0	4	0	0
T57	0	1	0	0
T58	0	2	0	0
T90	0	2	0	0
T94	0	1	0	0
T156	0	1	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	68132	0	0
T2	915	181	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T36	0	376	0	0
T39	0	80	0	0
T54	0	471	0	0
T57	0	133	0	0
T58	0	194	0	0
T90	0	200	0	0
T94	0	67	0	0
T156	0	38	0	0
T194	0	90	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	28	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	2	0	0
T54	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T91	0	1	0	0
T102	0	2	0	0
T159	0	3	0	0
T179	0	1	0	0
T194	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T24,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T56,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T56,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T56,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T24,T3,T7
1	1	Covered	T2,T56,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T56,T54
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T56,T54
0	1	Covered	T2,T56,T54
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T56,T54
1	-	Covered	T2,T56,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T56,T54
DetectSt	168	Covered	T2,T56,T54
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T56,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T56,T54
DebounceSt->IdleSt	163	Covered	T93,T188,T180
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T56,T54
IdleSt->DebounceSt	148	Covered	T2,T56,T54
StableSt->IdleSt	206	Covered	T2,T56,T54

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T56,T54
0	1	Covered	T2,T56,T54
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T56,T54
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T56,T54
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T56,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T93,T188,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T56,T54
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T56,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T56,T54
StableSt	-	-	-	-	-	-	0	Covered	T2,T56,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	73	0	0
CntIncr_A	6890910	51498	0	0
CntNoWrap_A	6890910	6236459	0	0
DetectStDropOut_A	6890910	0	0	0
DetectedOut_A	6890910	2857	0	0
DetectedPulseOut_A	6890910	35	0	0
DisabledIdleSt_A	6890910	5760029	0	0
DisabledNoDetection_A	6890910	5762210	0	0
EnterDebounceSt_A	6890910	38	0	0
EnterDetectSt_A	6890910	35	0	0
EnterStableSt_A	6890910	35	0	0
PulseIsPulse_A	6890910	35	0	0
StayInStableSt	6890910	2809	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6890910	6185	0	0
gen_low_level_sva.LowLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	73	0	0
T2	915	2	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	2	0	0
T54	0	2	0	0
T56	0	2	0	0
T93	0	3	0	0
T102	0	4	0	0
T114	0	4	0	0
T159	0	10	0	0
T188	0	3	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	51498	0	0
T2	915	92	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	72	0	0
T54	0	72	0	0
T56	0	86	0	0
T93	0	68	0	0
T102	0	26	0	0
T114	0	62	0	0
T159	0	386	0	0
T188	0	146	0	0
T194	0	17	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6236459	0	0
T1	678	277	0	0
T2	915	512	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2857	0	0
T2	915	44	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	203	0	0
T54	0	116	0	0
T56	0	65	0	0
T93	0	1	0	0
T102	0	163	0	0
T114	0	94	0	0
T159	0	633	0	0
T188	0	114	0	0
T194	0	97	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	35	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T93	0	1	0	0
T102	0	2	0	0
T114	0	2	0	0
T159	0	5	0	0
T188	0	1	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5760029	0	0
T1	678	3	0	0
T2	915	4	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	3	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5762210	0	0
T1	678	3	0	0
T2	915	4	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	3	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	38	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T93	0	2	0	0
T102	0	2	0	0
T114	0	2	0	0
T159	0	5	0	0
T188	0	2	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	35	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T93	0	1	0	0
T102	0	2	0	0
T114	0	2	0	0
T159	0	5	0	0
T188	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	35	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T93	0	1	0	0
T102	0	2	0	0
T114	0	2	0	0
T159	0	5	0	0
T188	0	1	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	35	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T93	0	1	0	0
T102	0	2	0	0
T114	0	2	0	0
T159	0	5	0	0
T188	0	1	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2809	0	0
T2	915	43	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	202	0	0
T54	0	115	0	0
T56	0	64	0	0
T88	0	1	0	0
T102	0	160	0	0
T114	0	91	0	0
T159	0	626	0	0
T188	0	112	0	0
T194	0	95	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6185	0	0
T2	915	1	0	0
T3	25438	31	0	0
T6	505	0	0	0
T7	21449	26	0	0
T8	23338	11	0	0
T9	488	1	0	0
T24	9167	25	0	0
T25	238296	0	0	0
T26	438	5	0	0
T27	708	0	0	0
T29	0	5	0	0
T30	0	27	0	0
T51	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	20	0	0
T2	915	1	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T39	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T93	0	1	0	0
T102	0	1	0	0
T114	0	1	0	0
T155	0	1	0	0
T159	0	3	0	0
T179	0	1	0	0