Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T30
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T30
1	0	Covered	T3,T60,T55
1	1	Covered	T24,T3,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T59
0	1	Covered	T30,T74,T100
1	0	Covered	T75,T76,T230

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T59
0	1	Covered	T24,T3,T59
1	0	Covered	T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T3,T59
1	-	Covered	T24,T3,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T3,T30
DetectSt	168	Covered	T24,T3,T30
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T24,T3,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T3,T30
DebounceSt->IdleSt	163	Covered	T24,T30,T59
DetectSt->IdleSt	186	Covered	T30,T74,T75
DetectSt->StableSt	191	Covered	T24,T3,T59
IdleSt->DebounceSt	148	Covered	T24,T3,T30
StableSt->IdleSt	206	Covered	T24,T3,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T3,T30
0	1	Covered	T24,T3,T30
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T3,T30
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T24,T3,T30
IdleSt	0	-	-	-	-	-	-	Covered	T24,T3,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T3,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T30,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T3,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T74,T75
DetectSt	-	-	-	-	0	1	-	Covered	T24,T3,T59
DetectSt	-	-	-	-	0	0	-	Covered	T24,T3,T59
StableSt	-	-	-	-	-	-	1	Covered	T24,T3,T59
StableSt	-	-	-	-	-	-	0	Covered	T24,T3,T59
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	2825	0	0
CntIncr_A	6890910	109454	0	0
CntNoWrap_A	6890910	6233707	0	0
DetectStDropOut_A	6890910	279	0	0
DetectedOut_A	6890910	72284	0	0
DetectedPulseOut_A	6890910	920	0	0
DisabledIdleSt_A	6890910	5758823	0	0
DisabledNoDetection_A	6890910	5760875	0	0
EnterDebounceSt_A	6890910	1465	0	0
EnterDetectSt_A	6890910	1361	0	0
EnterStableSt_A	6890910	920	0	0
PulseIsPulse_A	6890910	920	0	0
StayInStableSt	6890910	71273	0	0
gen_high_event_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	828	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2825	0	0
T2	915	0	0	0
T3	25438	54	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	25	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	36	0	0
T55	0	34	0	0
T59	0	9	0	0
T60	0	28	0	0
T61	0	22	0	0
T74	0	22	0	0
T75	0	16	0	0
T76	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	109454	0	0
T2	915	0	0	0
T3	25438	2079	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	3777	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	1400	0	0
T55	0	918	0	0
T59	0	2189	0	0
T60	0	1120	0	0
T61	0	891	0	0
T74	0	558	0	0
T75	0	563	0	0
T76	0	214	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6233707	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24928	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8741	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	279	0	0
T10	13663	0	0	0
T11	544	0	0	0
T30	5067	8	0	0
T31	735	0	0	0
T49	1311	0	0	0
T50	840	0	0	0
T51	497	0	0	0
T52	505	0	0	0
T53	28002	0	0	0
T59	15265	0	0	0
T74	0	11	0	0
T88	0	1	0	0
T100	0	8	0	0
T101	0	11	0	0
T103	0	4	0	0
T104	0	25	0	0
T105	0	3	0	0
T106	0	11	0	0
T107	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	72284	0	0
T2	915	0	0	0
T3	25438	2466	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	303	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T55	0	494	0	0
T59	0	203	0	0
T60	0	268	0	0
T61	0	138	0	0
T135	0	270	0	0
T231	0	389	0	0
T232	0	97	0	0
T233	0	1046	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	920	0	0
T2	915	0	0	0
T3	25438	27	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	8	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T55	0	17	0	0
T59	0	1	0	0
T60	0	14	0	0
T61	0	11	0	0
T135	0	6	0	0
T231	0	9	0	0
T232	0	9	0	0
T233	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5758823	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	18280	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	2015	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5760875	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	18280	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	2015	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1465	0	0
T2	915	0	0	0
T3	25438	27	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	17	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	28	0	0
T55	0	17	0	0
T59	0	8	0	0
T60	0	14	0	0
T61	0	11	0	0
T74	0	11	0	0
T75	0	8	0	0
T76	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1361	0	0
T2	915	0	0	0
T3	25438	27	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	8	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	8	0	0
T55	0	17	0	0
T59	0	1	0	0
T60	0	14	0	0
T61	0	11	0	0
T74	0	11	0	0
T75	0	8	0	0
T76	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	920	0	0
T2	915	0	0	0
T3	25438	27	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	8	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T55	0	17	0	0
T59	0	1	0	0
T60	0	14	0	0
T61	0	11	0	0
T135	0	6	0	0
T231	0	9	0	0
T232	0	9	0	0
T233	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	920	0	0
T2	915	0	0	0
T3	25438	27	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	8	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T55	0	17	0	0
T59	0	1	0	0
T60	0	14	0	0
T61	0	11	0	0
T135	0	6	0	0
T231	0	9	0	0
T232	0	9	0	0
T233	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	71273	0	0
T2	915	0	0	0
T3	25438	2431	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	295	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T55	0	476	0	0
T59	0	202	0	0
T60	0	253	0	0
T61	0	126	0	0
T135	0	264	0	0
T231	0	380	0	0
T232	0	88	0	0
T233	0	1028	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	828	0	0
T2	915	0	0	0
T3	25438	19	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	8	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T55	0	16	0	0
T59	0	1	0	0
T60	0	13	0	0
T61	0	10	0	0
T135	0	6	0	0
T231	0	9	0	0
T232	0	9	0	0
T233	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T7
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T7,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T7
1	0	Covered	T24,T3,T7
1	1	Covered	T3,T7,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T9
0	1	Covered	T7,T17,T93
1	0	Covered	T88,T89

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T10
0	1	Covered	T3,T9,T10
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T10
1	-	Covered	T3,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T9
DetectSt	168	Covered	T3,T7,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T9
DebounceSt->IdleSt	163	Covered	T10,T53,T12
DetectSt->IdleSt	186	Covered	T7,T17,T93
DetectSt->StableSt	191	Covered	T3,T9,T10
IdleSt->DebounceSt	148	Covered	T3,T7,T9
StableSt->IdleSt	206	Covered	T3,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T9
0	1	Covered	T3,T7,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T53,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T9
DetectSt	-	-	-	-	1	-	-	Covered	T7,T17,T93
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T9
StableSt	-	-	-	-	-	-	1	Covered	T3,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	811	0	0
CntIncr_A	6890910	42648	0	0
CntNoWrap_A	6890910	6235721	0	0
DetectStDropOut_A	6890910	40	0	0
DetectedOut_A	6890910	11794	0	0
DetectedPulseOut_A	6890910	332	0	0
DisabledIdleSt_A	6890910	5881401	0	0
DisabledNoDetection_A	6890910	5882999	0	0
EnterDebounceSt_A	6890910	441	0	0
EnterDetectSt_A	6890910	377	0	0
EnterStableSt_A	6890910	332	0	0
PulseIsPulse_A	6890910	332	0	0
StayInStableSt	6890910	11428	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	294	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	811	0	0
T3	25438	16	0	0
T7	21449	4	0	0
T8	23338	0	0	0
T9	488	2	0	0
T10	0	5	0	0
T12	0	13	0	0
T17	0	25	0	0
T19	0	8	0	0
T21	0	12	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T44	0	1	0	0
T53	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	42648	0	0
T3	25438	408	0	0
T7	21449	241	0	0
T8	23338	0	0	0
T9	488	25	0	0
T10	0	262	0	0
T12	0	769	0	0
T17	0	1358	0	0
T18	0	20	0	0
T19	0	520	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T44	0	20	0	0
T53	0	1211	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6235721	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24966	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19001	0	0
T8	23338	22875	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	40	0	0
T7	21449	2	0	0
T8	23338	0	0	0
T9	488	0	0	0
T17	0	7	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T51	497	0	0	0
T91	0	10	0	0
T93	0	1	0	0
T99	0	1	0	0
T102	0	1	0	0
T108	0	3	0	0
T109	0	5	0	0
T110	0	8	0	0
T111	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	11794	0	0
T3	25438	598	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	3	0	0
T10	0	12	0	0
T12	0	379	0	0
T17	0	117	0	0
T19	0	321	0	0
T21	0	56	0	0
T22	0	3	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	82	0	0
T60	0	55	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	332	0	0
T3	25438	8	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	5	0	0
T19	0	4	0	0
T21	0	6	0	0
T22	0	1	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	8	0	0
T60	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5881401	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	22523	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	14560	0	0
T8	23338	22875	0	0
T24	9167	8463	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5882999	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	22524	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	14564	0	0
T8	23338	22884	0	0
T24	9167	8464	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	441	0	0
T3	25438	8	0	0
T7	21449	2	0	0
T8	23338	0	0	0
T9	488	1	0	0
T10	0	3	0	0
T12	0	7	0	0
T17	0	13	0	0
T18	0	1	0	0
T19	0	4	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T44	0	1	0	0
T53	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	377	0	0
T3	25438	8	0	0
T7	21449	2	0	0
T8	23338	0	0	0
T9	488	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	12	0	0
T19	0	4	0	0
T21	0	6	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	8	0	0
T60	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	332	0	0
T3	25438	8	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	5	0	0
T19	0	4	0	0
T21	0	6	0	0
T22	0	1	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	8	0	0
T60	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	332	0	0
T3	25438	8	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	5	0	0
T19	0	4	0	0
T21	0	6	0	0
T22	0	1	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	8	0	0
T60	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	11428	0	0
T3	25438	590	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	2	0	0
T10	0	10	0	0
T12	0	373	0	0
T17	0	112	0	0
T19	0	317	0	0
T21	0	50	0	0
T22	0	2	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	74	0	0
T60	0	53	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	294	0	0
T3	25438	8	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	1	0	0
T10	0	2	0	0
T12	0	6	0	0
T17	0	5	0	0
T19	0	4	0	0
T21	0	6	0	0
T22	0	1	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	7	0	0
T65	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T30
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T30
1	0	Covered	T3,T60,T55
1	1	Covered	T24,T3,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T60
0	1	Covered	T24,T55,T74
1	0	Covered	T55,T75,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T60,T61
0	1	Covered	T3,T60,T61
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T60,T61
1	-	Covered	T3,T60,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T3,T30
DetectSt	168	Covered	T24,T3,T60
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T60,T61

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T3,T60
DebounceSt->IdleSt	163	Covered	T24,T30,T59
DetectSt->IdleSt	186	Covered	T24,T55,T74
DetectSt->StableSt	191	Covered	T3,T60,T61
IdleSt->DebounceSt	148	Covered	T24,T3,T30
StableSt->IdleSt	206	Covered	T3,T60,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T3,T30
0	1	Covered	T24,T3,T30
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T3,T60
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T24,T3,T30
IdleSt	0	-	-	-	-	-	-	Covered	T24,T3,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T3,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T30,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T3,T30
DetectSt	-	-	-	-	1	-	-	Covered	T24,T55,T74
DetectSt	-	-	-	-	0	1	-	Covered	T3,T60,T61
DetectSt	-	-	-	-	0	0	-	Covered	T24,T3,T60
StableSt	-	-	-	-	-	-	1	Covered	T3,T60,T61
StableSt	-	-	-	-	-	-	0	Covered	T3,T60,T61
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	2994	0	0
CntIncr_A	6890910	114161	0	0
CntNoWrap_A	6890910	6233538	0	0
DetectStDropOut_A	6890910	372	0	0
DetectedOut_A	6890910	69871	0	0
DetectedPulseOut_A	6890910	816	0	0
DisabledIdleSt_A	6890910	5753906	0	0
DisabledNoDetection_A	6890910	5755979	0	0
EnterDebounceSt_A	6890910	1534	0	0
EnterDetectSt_A	6890910	1461	0	0
EnterStableSt_A	6890910	816	0	0
PulseIsPulse_A	6890910	816	0	0
StayInStableSt	6890910	68983	0	0
gen_high_event_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	742	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2994	0	0
T2	915	0	0	0
T3	25438	14	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	24	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	7	0	0
T55	0	54	0	0
T59	0	7	0	0
T60	0	24	0	0
T61	0	4	0	0
T74	0	52	0	0
T75	0	26	0	0
T76	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	114161	0	0
T2	915	0	0	0
T3	25438	476	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	3697	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	350	0	0
T55	0	1747	0	0
T59	0	1883	0	0
T60	0	876	0	0
T61	0	128	0	0
T74	0	1325	0	0
T75	0	915	0	0
T76	0	1404	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6233538	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24968	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8742	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	372	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	9	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T55	0	3	0	0
T74	0	26	0	0
T88	0	1	0	0
T100	0	29	0	0
T104	0	6	0	0
T153	0	12	0	0
T230	0	20	0	0
T234	0	5	0	0
T235	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	69871	0	0
T3	25438	244	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T60	0	445	0	0
T61	0	38	0	0
T101	0	264	0	0
T103	0	1215	0	0
T135	0	3438	0	0
T231	0	3105	0	0
T232	0	11	0	0
T236	0	4120	0	0
T237	0	1605	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	816	0	0
T3	25438	7	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T60	0	12	0	0
T61	0	2	0	0
T101	0	3	0	0
T103	0	13	0	0
T135	0	30	0	0
T231	0	29	0	0
T232	0	5	0	0
T236	0	11	0	0
T237	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5753906	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	20480	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	2015	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5755979	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	20487	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	2015	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1534	0	0
T2	915	0	0	0
T3	25438	7	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	15	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	7	0	0
T55	0	27	0	0
T59	0	7	0	0
T60	0	12	0	0
T61	0	2	0	0
T74	0	26	0	0
T75	0	13	0	0
T76	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1461	0	0
T2	915	0	0	0
T3	25438	7	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	9	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T55	0	27	0	0
T60	0	12	0	0
T61	0	2	0	0
T74	0	26	0	0
T75	0	13	0	0
T76	0	26	0	0
T135	0	30	0	0
T231	0	29	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	816	0	0
T3	25438	7	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T60	0	12	0	0
T61	0	2	0	0
T101	0	3	0	0
T103	0	13	0	0
T135	0	30	0	0
T231	0	29	0	0
T232	0	5	0	0
T236	0	11	0	0
T237	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	816	0	0
T3	25438	7	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T60	0	12	0	0
T61	0	2	0	0
T101	0	3	0	0
T103	0	13	0	0
T135	0	30	0	0
T231	0	29	0	0
T232	0	5	0	0
T236	0	11	0	0
T237	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	68983	0	0
T3	25438	236	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T60	0	432	0	0
T61	0	36	0	0
T101	0	261	0	0
T103	0	1202	0	0
T135	0	3405	0	0
T231	0	3076	0	0
T232	0	6	0	0
T236	0	4105	0	0
T237	0	1589	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	742	0	0
T3	25438	6	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T60	0	11	0	0
T61	0	2	0	0
T101	0	3	0	0
T103	0	13	0	0
T135	0	27	0	0
T231	0	29	0	0
T232	0	5	0	0
T236	0	7	0	0
T237	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T7
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T24,T3,T7
1	1	Covered	T3,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T10,T53,T39
1	0	Covered	T88,T89

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T8
1	-	Covered	T3,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T8
DetectSt	168	Covered	T3,T7,T8
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T8
DebounceSt->IdleSt	163	Covered	T12,T17,T19
DetectSt->IdleSt	186	Covered	T10,T53,T39
DetectSt->StableSt	191	Covered	T3,T7,T8
IdleSt->DebounceSt	148	Covered	T3,T7,T8
StableSt->IdleSt	206	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T8
0	1	Covered	T3,T7,T8
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T17,T19
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T10,T53,T39
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	714	0	0
CntIncr_A	6890910	38887	0	0
CntNoWrap_A	6890910	6235818	0	0
DetectStDropOut_A	6890910	51	0	0
DetectedOut_A	6890910	17033	0	0
DetectedPulseOut_A	6890910	282	0	0
DisabledIdleSt_A	6890910	5884464	0	0
DisabledNoDetection_A	6890910	5886132	0	0
EnterDebounceSt_A	6890910	378	0	0
EnterDetectSt_A	6890910	336	0	0
EnterStableSt_A	6890910	282	0	0
PulseIsPulse_A	6890910	282	0	0
StayInStableSt	6890910	16719	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	246	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	714	0	0
T3	25438	2	0	0
T7	21449	8	0	0
T8	23338	2	0	0
T9	488	0	0	0
T10	0	4	0	0
T12	0	29	0	0
T17	0	7	0	0
T19	0	7	0	0
T21	0	8	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	16	0	0
T54	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	38887	0	0
T3	25438	42	0	0
T7	21449	300	0	0
T8	23338	190	0	0
T9	488	0	0	0
T10	0	240	0	0
T12	0	1833	0	0
T17	0	321	0	0
T19	0	594	0	0
T21	0	684	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	835	0	0
T54	0	316	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6235818	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24980	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	18997	0	0
T8	23338	22873	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	51	0	0
T10	13663	2	0	0
T11	544	0	0	0
T12	39331	0	0	0
T39	0	1	0	0
T50	840	0	0	0
T52	505	0	0	0
T53	28002	7	0	0
T59	15265	0	0	0
T62	654	0	0	0
T69	585	0	0	0
T70	420	0	0	0
T89	0	1	0	0
T238	0	1	0	0
T239	0	3	0	0
T240	0	6	0	0
T241	0	1	0	0
T242	0	2	0	0
T243	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	17033	0	0
T3	25438	85	0	0
T7	21449	185	0	0
T8	23338	5	0	0
T9	488	0	0	0
T12	0	787	0	0
T17	0	85	0	0
T19	0	125	0	0
T21	0	24	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	32	0	0
T54	0	98	0	0
T97	0	55	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	282	0	0
T3	25438	1	0	0
T7	21449	4	0	0
T8	23338	1	0	0
T9	488	0	0	0
T12	0	14	0	0
T17	0	3	0	0
T19	0	3	0	0
T21	0	4	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T97	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5884464	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24739	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	14560	0	0
T8	23338	18129	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5886132	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24747	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	14564	0	0
T8	23338	18129	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	378	0	0
T3	25438	1	0	0
T7	21449	4	0	0
T8	23338	1	0	0
T9	488	0	0	0
T10	0	2	0	0
T12	0	15	0	0
T17	0	4	0	0
T19	0	4	0	0
T21	0	4	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	8	0	0
T54	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	336	0	0
T3	25438	1	0	0
T7	21449	4	0	0
T8	23338	1	0	0
T9	488	0	0	0
T10	0	2	0	0
T12	0	14	0	0
T17	0	3	0	0
T19	0	3	0	0
T21	0	4	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	8	0	0
T54	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	282	0	0
T3	25438	1	0	0
T7	21449	4	0	0
T8	23338	1	0	0
T9	488	0	0	0
T12	0	14	0	0
T17	0	3	0	0
T19	0	3	0	0
T21	0	4	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T97	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	282	0	0
T3	25438	1	0	0
T7	21449	4	0	0
T8	23338	1	0	0
T9	488	0	0	0
T12	0	14	0	0
T17	0	3	0	0
T19	0	3	0	0
T21	0	4	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T97	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	16719	0	0
T3	25438	84	0	0
T7	21449	181	0	0
T8	23338	4	0	0
T9	488	0	0	0
T12	0	773	0	0
T17	0	82	0	0
T19	0	122	0	0
T21	0	20	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	31	0	0
T54	0	96	0	0
T97	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	246	0	0
T3	25438	1	0	0
T7	21449	4	0	0
T8	23338	1	0	0
T9	488	0	0	0
T12	0	14	0	0
T17	0	3	0	0
T19	0	3	0	0
T21	0	4	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T97	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T30
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T30
1	0	Covered	T3,T60,T55
1	1	Covered	T24,T3,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T3,T60
0	1	Covered	T24,T30,T74
1	0	Covered	T75,T117,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T60,T55
0	1	Covered	T3,T60,T55
1	0	Covered	T217

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T60,T55
1	-	Covered	T3,T60,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T3,T30
DetectSt	168	Covered	T24,T3,T30
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T60,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T3,T30
DebounceSt->IdleSt	163	Covered	T24,T30,T59
DetectSt->IdleSt	186	Covered	T24,T30,T74
DetectSt->StableSt	191	Covered	T3,T60,T55
IdleSt->DebounceSt	148	Covered	T24,T3,T30
StableSt->IdleSt	206	Covered	T3,T60,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T3,T30
0	1	Covered	T24,T3,T30
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T3,T30
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T24,T3,T30
IdleSt	0	-	-	-	-	-	-	Covered	T24,T3,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T3,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T30,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T3,T30
DetectSt	-	-	-	-	1	-	-	Covered	T24,T30,T74
DetectSt	-	-	-	-	0	1	-	Covered	T3,T60,T55
DetectSt	-	-	-	-	0	0	-	Covered	T24,T3,T60
StableSt	-	-	-	-	-	-	1	Covered	T3,T60,T55
StableSt	-	-	-	-	-	-	0	Covered	T3,T60,T55
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	2993	0	0
CntIncr_A	6890910	106819	0	0
CntNoWrap_A	6890910	6233539	0	0
DetectStDropOut_A	6890910	365	0	0
DetectedOut_A	6890910	87827	0	0
DetectedPulseOut_A	6890910	974	0	0
DisabledIdleSt_A	6890910	5743813	0	0
DisabledNoDetection_A	6890910	5745849	0	0
EnterDebounceSt_A	6890910	1531	0	0
EnterDetectSt_A	6890910	1463	0	0
EnterStableSt_A	6890910	974	0	0
PulseIsPulse_A	6890910	974	0	0
StayInStableSt	6890910	86744	0	0
gen_high_event_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	861	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2993	0	0
T2	915	0	0	0
T3	25438	14	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	27	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	16	0	0
T55	0	44	0	0
T59	0	5	0	0
T60	0	10	0	0
T61	0	30	0	0
T74	0	24	0	0
T75	0	50	0	0
T76	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	106819	0	0
T2	915	0	0	0
T3	25438	364	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	4485	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	750	0	0
T55	0	1298	0	0
T59	0	1345	0	0
T60	0	410	0	0
T61	0	795	0	0
T74	0	608	0	0
T75	0	1759	0	0
T76	0	1326	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6233539	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24968	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8739	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	365	0	0
T2	915	0	0	0
T3	25438	0	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	9	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	1	0	0
T74	0	12	0	0
T75	0	12	0	0
T88	0	1	0	0
T100	0	26	0	0
T104	0	7	0	0
T105	0	29	0	0
T106	0	27	0	0
T117	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	87827	0	0
T3	25438	219	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	1191	0	0
T60	0	159	0	0
T61	0	987	0	0
T76	0	1520	0	0
T135	0	3348	0	0
T230	0	1824	0	0
T231	0	3062	0	0
T232	0	66	0	0
T236	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	974	0	0
T3	25438	7	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	22	0	0
T60	0	5	0	0
T61	0	15	0	0
T76	0	26	0	0
T135	0	30	0	0
T230	0	16	0	0
T231	0	26	0	0
T232	0	8	0	0
T236	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5743813	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	20630	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	2015	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5745849	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	20638	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	2015	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1531	0	0
T2	915	0	0	0
T3	25438	7	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	19	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	15	0	0
T55	0	22	0	0
T59	0	5	0	0
T60	0	5	0	0
T61	0	15	0	0
T74	0	12	0	0
T75	0	25	0	0
T76	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1463	0	0
T2	915	0	0	0
T3	25438	7	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	9	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	1	0	0
T55	0	22	0	0
T60	0	5	0	0
T61	0	15	0	0
T74	0	12	0	0
T75	0	25	0	0
T76	0	26	0	0
T135	0	30	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	974	0	0
T3	25438	7	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	22	0	0
T60	0	5	0	0
T61	0	15	0	0
T76	0	26	0	0
T135	0	30	0	0
T230	0	16	0	0
T231	0	26	0	0
T232	0	8	0	0
T236	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	974	0	0
T3	25438	7	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	22	0	0
T60	0	5	0	0
T61	0	15	0	0
T76	0	26	0	0
T135	0	30	0	0
T230	0	16	0	0
T231	0	26	0	0
T232	0	8	0	0
T236	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	86744	0	0
T3	25438	212	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	1166	0	0
T60	0	154	0	0
T61	0	970	0	0
T76	0	1492	0	0
T135	0	3315	0	0
T230	0	1807	0	0
T231	0	3036	0	0
T232	0	58	0	0
T236	0	106	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	861	0	0
T3	25438	7	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	19	0	0
T60	0	5	0	0
T61	0	13	0	0
T76	0	24	0	0
T135	0	27	0	0
T230	0	15	0	0
T231	0	26	0	0
T232	0	8	0	0
T236	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T7
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T24,T3,T7
1	1	Covered	T7,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T10
0	1	Covered	T53,T99,T91
1	0	Covered	T88,T89

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T10
0	1	Covered	T7,T8,T10
1	0	Covered	T88,T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T10
1	-	Covered	T7,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T10
DetectSt	168	Covered	T7,T8,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T10
DebounceSt->IdleSt	163	Covered	T8,T10,T19
DetectSt->IdleSt	186	Covered	T53,T99,T91
DetectSt->StableSt	191	Covered	T7,T8,T10
IdleSt->DebounceSt	148	Covered	T7,T8,T10
StableSt->IdleSt	206	Covered	T7,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T10
0	1	Covered	T7,T8,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T10,T19
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T53,T99,T91
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T10
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	758	0	0
CntIncr_A	6890910	43179	0	0
CntNoWrap_A	6890910	6235774	0	0
DetectStDropOut_A	6890910	31	0	0
DetectedOut_A	6890910	16025	0	0
DetectedPulseOut_A	6890910	319	0	0
DisabledIdleSt_A	6890910	5866338	0	0
DisabledNoDetection_A	6890910	5867968	0	0
EnterDebounceSt_A	6890910	404	0	0
EnterDetectSt_A	6890910	355	0	0
EnterStableSt_A	6890910	319	0	0
PulseIsPulse_A	6890910	319	0	0
StayInStableSt	6890910	15664	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	275	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	758	0	0
T7	21449	6	0	0
T8	23338	17	0	0
T9	488	0	0	0
T10	0	9	0	0
T12	0	6	0	0
T19	0	1	0	0
T21	0	16	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T51	497	0	0	0
T53	0	8	0	0
T54	0	20	0	0
T55	0	2	0	0
T97	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	43179	0	0
T7	21449	309	0	0
T8	23338	935	0	0
T9	488	0	0	0
T10	0	382	0	0
T12	0	483	0	0
T19	0	87	0	0
T21	0	1360	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T51	497	0	0	0
T53	0	589	0	0
T54	0	860	0	0
T55	0	56	0	0
T97	0	104	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6235774	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	18999	0	0
T8	23338	22858	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	31	0	0
T11	544	0	0	0
T12	39331	0	0	0
T13	604	0	0	0
T14	104160	0	0	0
T53	28002	3	0	0
T62	654	0	0	0
T69	585	0	0	0
T70	420	0	0	0
T71	523	0	0	0
T91	0	3	0	0
T99	0	1	0	0
T108	0	1	0	0
T220	589	0	0	0
T244	0	5	0	0
T245	0	11	0	0
T246	0	1	0	0
T247	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	16025	0	0
T7	21449	52	0	0
T8	23338	714	0	0
T9	488	0	0	0
T10	0	132	0	0
T12	0	64	0	0
T21	0	60	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	34	0	0
T51	497	0	0	0
T53	0	5	0	0
T54	0	850	0	0
T55	0	32	0	0
T97	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	319	0	0
T7	21449	3	0	0
T8	23338	8	0	0
T9	488	0	0	0
T10	0	4	0	0
T12	0	3	0	0
T21	0	8	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	1	0	0
T51	497	0	0	0
T53	0	1	0	0
T54	0	10	0	0
T55	0	1	0	0
T97	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5866338	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24760	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	14560	0	0
T8	23338	18129	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5867968	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24769	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	14564	0	0
T8	23338	18129	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	404	0	0
T7	21449	3	0	0
T8	23338	9	0	0
T9	488	0	0	0
T10	0	5	0	0
T12	0	3	0	0
T19	0	1	0	0
T21	0	8	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T51	497	0	0	0
T53	0	4	0	0
T54	0	10	0	0
T55	0	1	0	0
T97	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	355	0	0
T7	21449	3	0	0
T8	23338	8	0	0
T9	488	0	0	0
T10	0	4	0	0
T12	0	3	0	0
T21	0	8	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	1	0	0
T51	497	0	0	0
T53	0	4	0	0
T54	0	10	0	0
T55	0	1	0	0
T97	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	319	0	0
T7	21449	3	0	0
T8	23338	8	0	0
T9	488	0	0	0
T10	0	4	0	0
T12	0	3	0	0
T21	0	8	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	1	0	0
T51	497	0	0	0
T53	0	1	0	0
T54	0	10	0	0
T55	0	1	0	0
T97	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	319	0	0
T7	21449	3	0	0
T8	23338	8	0	0
T9	488	0	0	0
T10	0	4	0	0
T12	0	3	0	0
T21	0	8	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	1	0	0
T51	497	0	0	0
T53	0	1	0	0
T54	0	10	0	0
T55	0	1	0	0
T97	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	15664	0	0
T7	21449	49	0	0
T8	23338	706	0	0
T9	488	0	0	0
T10	0	128	0	0
T12	0	61	0	0
T21	0	52	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	33	0	0
T51	497	0	0	0
T53	0	4	0	0
T54	0	840	0	0
T55	0	30	0	0
T97	0	60	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	275	0	0
T7	21449	3	0	0
T8	23338	8	0	0
T9	488	0	0	0
T10	0	4	0	0
T12	0	3	0	0
T21	0	8	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	1	0	0
T51	497	0	0	0
T53	0	1	0	0
T54	0	10	0	0
T93	0	4	0	0
T97	0	2	0	0