Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T30
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T3,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T30,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T30
1	0	Covered	T3,T60,T55
1	1	Covered	T24,T3,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T60,T55
0	1	Covered	T30,T74,T231
1	0	Covered	T231,T230,T101

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T60,T55
0	1	Covered	T3,T60,T55
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T60,T55
1	-	Covered	T3,T60,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T3,T30
DetectSt	168	Covered	T3,T30,T60
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T60,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T30,T60
DebounceSt->IdleSt	163	Covered	T24,T30,T59
DetectSt->IdleSt	186	Covered	T30,T74,T231
DetectSt->StableSt	191	Covered	T3,T60,T55
IdleSt->DebounceSt	148	Covered	T24,T3,T30
StableSt->IdleSt	206	Covered	T3,T60,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T3,T30
0	1	Covered	T24,T3,T30
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T30,T60
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T24,T3,T30
IdleSt	0	-	-	-	-	-	-	Covered	T24,T3,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T30,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T30,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T3,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T74,T231
DetectSt	-	-	-	-	0	1	-	Covered	T3,T60,T55
DetectSt	-	-	-	-	0	0	-	Covered	T3,T60,T55
StableSt	-	-	-	-	-	-	1	Covered	T3,T60,T55
StableSt	-	-	-	-	-	-	0	Covered	T3,T60,T55
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	2946	0	0
CntIncr_A	6890910	113001	0	0
CntNoWrap_A	6890910	6233586	0	0
DetectStDropOut_A	6890910	335	0	0
DetectedOut_A	6890910	83149	0	0
DetectedPulseOut_A	6890910	938	0	0
DisabledIdleSt_A	6890910	5743349	0	0
DisabledNoDetection_A	6890910	5745412	0	0
EnterDebounceSt_A	6890910	1518	0	0
EnterDetectSt_A	6890910	1429	0	0
EnterStableSt_A	6890910	938	0	0
PulseIsPulse_A	6890910	938	0	0
StayInStableSt	6890910	82131	0	0
gen_high_event_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	853	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	2946	0	0
T2	915	0	0	0
T3	25438	22	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	8	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	22	0	0
T55	0	28	0	0
T59	0	7	0	0
T60	0	54	0	0
T61	0	46	0	0
T74	0	50	0	0
T75	0	48	0	0
T76	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	113001	0	0
T2	915	0	0	0
T3	25438	671	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	1736	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	950	0	0
T55	0	686	0	0
T59	0	1883	0	0
T60	0	2214	0	0
T61	0	1196	0	0
T74	0	1281	0	0
T75	0	1488	0	0
T76	0	184	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6233586	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24960	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	8758	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	335	0	0
T10	13663	0	0	0
T11	544	0	0	0
T30	5067	3	0	0
T31	735	0	0	0
T49	1311	0	0	0
T50	840	0	0	0
T51	497	0	0	0
T52	505	0	0	0
T53	28002	0	0	0
T59	15265	0	0	0
T74	0	25	0	0
T88	0	1	0	0
T100	0	12	0	0
T101	0	19	0	0
T104	0	16	0	0
T105	0	26	0	0
T106	0	30	0	0
T230	0	7	0	0
T231	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	83149	0	0
T3	25438	904	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	628	0	0
T60	0	1501	0	0
T61	0	1658	0	0
T75	0	1921	0	0
T76	0	30	0	0
T135	0	212	0	0
T232	0	113	0	0
T233	0	2819	0	0
T236	0	5371	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	938	0	0
T3	25438	11	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	14	0	0
T60	0	27	0	0
T61	0	23	0	0
T75	0	24	0	0
T76	0	4	0	0
T135	0	7	0	0
T232	0	6	0	0
T233	0	33	0	0
T236	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5743349	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	19964	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	19005	0	0
T8	23338	22875	0	0
T24	9167	2015	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5745412	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	19972	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	2015	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1518	0	0
T2	915	0	0	0
T3	25438	11	0	0
T6	505	0	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T24	9167	8	0	0
T25	238296	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T30	0	19	0	0
T55	0	14	0	0
T59	0	7	0	0
T60	0	27	0	0
T61	0	23	0	0
T74	0	25	0	0
T75	0	24	0	0
T76	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	1429	0	0
T3	25438	11	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	3	0	0
T31	735	0	0	0
T55	0	14	0	0
T60	0	27	0	0
T61	0	23	0	0
T74	0	25	0	0
T75	0	24	0	0
T76	0	4	0	0
T135	0	7	0	0
T231	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	938	0	0
T3	25438	11	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	14	0	0
T60	0	27	0	0
T61	0	23	0	0
T75	0	24	0	0
T76	0	4	0	0
T135	0	7	0	0
T232	0	6	0	0
T233	0	33	0	0
T236	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	938	0	0
T3	25438	11	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	14	0	0
T60	0	27	0	0
T61	0	23	0	0
T75	0	24	0	0
T76	0	4	0	0
T135	0	7	0	0
T232	0	6	0	0
T233	0	33	0	0
T236	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	82131	0	0
T3	25438	893	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	612	0	0
T60	0	1473	0	0
T61	0	1633	0	0
T75	0	1897	0	0
T76	0	26	0	0
T135	0	205	0	0
T232	0	107	0	0
T233	0	2784	0	0
T236	0	5350	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	853	0	0
T3	25438	11	0	0
T7	21449	0	0	0
T8	23338	0	0	0
T9	488	0	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T55	0	12	0	0
T60	0	26	0	0
T61	0	21	0	0
T75	0	24	0	0
T117	0	16	0	0
T135	0	7	0	0
T232	0	6	0	0
T233	0	31	0	0
T236	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T24,T3,T7
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T3,T7
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T24,T3,T7
1	1	Covered	T7,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T10
0	1	Covered	T10,T53,T21
1	0	Covered	T88,T89

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T53
0	1	Covered	T7,T8,T53
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T53
1	-	Covered	T7,T8,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T10
DetectSt	168	Covered	T7,T8,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T8,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T10
DebounceSt->IdleSt	163	Covered	T8,T10,T53
DetectSt->IdleSt	186	Covered	T10,T53,T21
DetectSt->StableSt	191	Covered	T7,T8,T53
IdleSt->DebounceSt	148	Covered	T7,T8,T10
StableSt->IdleSt	206	Covered	T7,T8,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T10
0	1	Covered	T7,T8,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T88,T89
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T10,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T10,T53,T21
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T53
DetectSt	-	-	-	-	0	0	-	Covered	T7,T8,T10
StableSt	-	-	-	-	-	-	1	Covered	T7,T8,T53
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6890910	744	0	0
CntIncr_A	6890910	43241	0	0
CntNoWrap_A	6890910	6235788	0	0
DetectStDropOut_A	6890910	80	0	0
DetectedOut_A	6890910	14138	0	0
DetectedPulseOut_A	6890910	270	0	0
DisabledIdleSt_A	6890910	5870428	0	0
DisabledNoDetection_A	6890910	5872085	0	0
EnterDebounceSt_A	6890910	390	0	0
EnterDetectSt_A	6890910	354	0	0
EnterStableSt_A	6890910	270	0	0
PulseIsPulse_A	6890910	270	0	0
StayInStableSt	6890910	13837	0	0
gen_high_level_sva.HighLevelEvent_A	6890910	6238768	0	0
gen_not_sticky_sva.StableStDropOut_A	6890910	235	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	744	0	0
T7	21449	8	0	0
T8	23338	7	0	0
T9	488	0	0	0
T10	0	7	0	0
T12	0	2	0	0
T17	0	4	0	0
T19	0	6	0	0
T21	0	10	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T51	497	0	0	0
T53	0	14	0	0
T55	0	4	0	0
T60	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	43241	0	0
T7	21449	400	0	0
T8	23338	610	0	0
T9	488	0	0	0
T10	0	395	0	0
T12	0	136	0	0
T17	0	136	0	0
T19	0	453	0	0
T21	0	885	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T51	497	0	0	0
T53	0	895	0	0
T55	0	120	0	0
T60	0	296	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6235788	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24982	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	18997	0	0
T8	23338	22868	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	80	0	0
T10	13663	3	0	0
T11	544	0	0	0
T12	39331	0	0	0
T21	0	5	0	0
T50	840	0	0	0
T52	505	0	0	0
T53	28002	3	0	0
T59	15265	0	0	0
T62	654	0	0	0
T69	585	0	0	0
T70	420	0	0	0
T97	0	2	0	0
T109	0	1	0	0
T148	0	9	0	0
T151	0	13	0	0
T242	0	2	0	0
T248	0	6	0	0
T249	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	14138	0	0
T7	21449	81	0	0
T8	23338	56	0	0
T9	488	0	0	0
T12	0	46	0	0
T17	0	108	0	0
T19	0	178	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	54	0	0
T51	497	0	0	0
T53	0	49	0	0
T54	0	669	0	0
T55	0	60	0	0
T60	0	141	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	270	0	0
T7	21449	4	0	0
T8	23338	3	0	0
T9	488	0	0	0
T12	0	1	0	0
T17	0	2	0	0
T19	0	3	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	1	0	0
T51	497	0	0	0
T53	0	3	0	0
T54	0	8	0	0
T55	0	2	0	0
T60	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5870428	0	0
T1	678	277	0	0
T2	915	514	0	0
T3	25438	24076	0	0
T4	748	347	0	0
T5	254446	254045	0	0
T6	505	104	0	0
T7	21449	14560	0	0
T8	23338	18129	0	0
T24	9167	8766	0	0
T25	238296	237895	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	5872085	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24085	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	14564	0	0
T8	23338	18129	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	390	0	0
T7	21449	4	0	0
T8	23338	4	0	0
T9	488	0	0	0
T10	0	4	0	0
T12	0	1	0	0
T17	0	2	0	0
T19	0	3	0	0
T21	0	5	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T51	497	0	0	0
T53	0	8	0	0
T55	0	2	0	0
T60	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	354	0	0
T7	21449	4	0	0
T8	23338	3	0	0
T9	488	0	0	0
T10	0	3	0	0
T12	0	1	0	0
T17	0	2	0	0
T19	0	3	0	0
T21	0	5	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T51	497	0	0	0
T53	0	6	0	0
T55	0	2	0	0
T60	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	270	0	0
T7	21449	4	0	0
T8	23338	3	0	0
T9	488	0	0	0
T12	0	1	0	0
T17	0	2	0	0
T19	0	3	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	1	0	0
T51	497	0	0	0
T53	0	3	0	0
T54	0	8	0	0
T55	0	2	0	0
T60	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	270	0	0
T7	21449	4	0	0
T8	23338	3	0	0
T9	488	0	0	0
T12	0	1	0	0
T17	0	2	0	0
T19	0	3	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	1	0	0
T51	497	0	0	0
T53	0	3	0	0
T54	0	8	0	0
T55	0	2	0	0
T60	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	13837	0	0
T7	21449	77	0	0
T8	23338	53	0	0
T9	488	0	0	0
T12	0	45	0	0
T17	0	106	0	0
T19	0	175	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	53	0	0
T51	497	0	0	0
T53	0	46	0	0
T54	0	661	0	0
T55	0	58	0	0
T60	0	137	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	6238768	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6890910	235	0	0
T7	21449	4	0	0
T8	23338	3	0	0
T9	488	0	0	0
T12	0	1	0	0
T17	0	2	0	0
T19	0	3	0	0
T26	438	0	0	0
T27	708	0	0	0
T28	1461	0	0	0
T29	447	0	0	0
T30	5067	0	0	0
T31	735	0	0	0
T39	0	1	0	0
T51	497	0	0	0
T53	0	2	0	0
T54	0	8	0	0
T55	0	2	0	0
T60	0	3	0	0