Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_ec_rst_ctl_cdc

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	88.73			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.61	100.00	94.44			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T25,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T25,T3
1	1	Covered	T24,T25,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T25,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T25,T3
1	1	Covered	T24,T25,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T25,T3
0	0	1	Covered	T24,T25,T3
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T25,T3
0	0	1	Covered	T24,T25,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1591324	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	2034	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1591324	0	0
T2	80874	0	0	0
T3	139915	1564	0	0
T6	63140	0	0	0
T7	257391	2682	0	0
T8	291725	3537	0	0
T9	58578	307	0	0
T10	0	2333	0	0
T24	220029	796	0	0
T25	119147	1993	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	809	0	0
T53	0	8145	0	0
T59	0	1719	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	2034	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	1	0	0
T10	0	5	0	0
T24	220029	1	0	0
T25	119147	1	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T53	0	10	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T5,T49,T50

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T50

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T5,T49,T50

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T50

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T49,T50
0	0	1	Covered	T5,T49,T50
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T49,T50
0	0	1	Covered	T5,T49,T50
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	899921	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1150	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	899921	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T5	209128	3998	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T16	0	2218	0	0
T17	0	162	0	0
T18	0	1910	0	0
T23	0	1422	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T36	0	1416	0	0
T49	0	822	0	0
T50	0	491	0	0
T53	0	981	0	0
T64	0	1919	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1150	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T5	209128	2	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T16	0	3	0	0
T17	0	2	0	0
T18	0	1	0	0
T23	0	1	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T36	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T53	0	1	0	0
T64	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T5,T49,T50

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T50

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T5,T49,T50

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T50

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T49,T50
0	0	1	Covered	T5,T49,T50
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T49,T50
0	0	1	Covered	T5,T49,T50
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	878245	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1161	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	878245	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T5	209128	3994	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T16	0	2193	0	0
T17	0	207	0	0
T18	0	1903	0	0
T23	0	1411	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T36	0	1405	0	0
T49	0	805	0	0
T50	0	488	0	0
T53	0	978	0	0
T64	0	1917	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1161	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T5	209128	2	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T16	0	3	0	0
T17	0	2	0	0
T18	0	1	0	0
T23	0	1	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T36	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T53	0	1	0	0
T64	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T5,T49,T50

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T50

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T5,T49,T50

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T49,T50
1	1	Covered	T5,T49,T50

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T49,T50
0	0	1	Covered	T5,T49,T50
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T5,T49,T50
0	0	1	Covered	T5,T49,T50
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	888875	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1154	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	888875	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T5	209128	3990	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T16	0	2176	0	0
T17	0	183	0	0
T18	0	1892	0	0
T23	0	1399	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T36	0	1394	0	0
T49	0	785	0	0
T50	0	486	0	0
T53	0	973	0	0
T64	0	1915	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1154	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T5	209128	2	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T16	0	3	0	0
T17	0	2	0	0
T18	0	1	0	0
T23	0	1	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T36	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T53	0	1	0	0
T64	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T16,T17,T23

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T16,T17,T23
1	1	Covered	T16,T17,T23

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T16,T17,T23
1	-	Covered	T16,T17,T23

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T16,T17,T23

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T17,T23
1	1	Covered	T16,T17,T23

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T16,T17,T23
0	0	1	Covered	T16,T17,T23
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T16,T17,T23
0	0	1	Covered	T16,T17,T23
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	895571	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1165	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	895571	0	0
T16	117292	1475	0	0
T17	160791	148	0	0
T18	505676	0	0	0
T23	0	3358	0	0
T32	331440	0	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T36	0	2859	0	0
T37	0	738	0	0
T38	0	388	0	0
T39	0	1947	0	0
T40	0	852	0	0
T41	0	1457	0	0
T42	0	5663	0	0
T43	342783	0	0	0
T44	639751	0	0	0
T45	149384	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1165	0	0
T16	117292	2	0	0
T17	160791	2	0	0
T18	505676	0	0	0
T23	0	2	0	0
T32	331440	0	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	6	0	0
T42	0	4	0	0
T43	342783	0	0	0
T44	639751	0	0	0
T45	149384	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T16,T17,T23

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T16,T17,T23
1	1	Covered	T16,T17,T23

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T46,T47,T48
1	-	Covered	T16,T17,T23

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T16,T17,T23
1	0	Covered	T16,T17,T23

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T17,T23
1	1	Covered	T16,T17,T23

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T16,T17,T23

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T16,T17,T23
0	0	1	Covered	T16,T17,T23
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T16,T17,T23
0	0	1	Covered	T16,T17,T23
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	591928	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	592	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	591928	0	0
T16	117292	735	0	0
T17	160791	87	0	0
T18	505676	0	0	0
T23	0	1438	0	0
T32	331440	0	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T36	0	1417	0	0
T37	0	353	0	0
T38	0	189	0	0
T39	0	945	0	0
T40	0	327	0	0
T41	0	679	0	0
T42	0	3228	0	0
T43	342783	0	0	0
T44	639751	0	0	0
T45	149384	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	592	0	0
T16	117292	1	0	0
T17	160791	1	0	0
T18	505676	0	0	0
T23	0	1	0	0
T32	331440	0	0	0
T33	201361	0	0	0
T34	394938	0	0	0
T35	233941	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	342783	0	0	0
T44	639751	0	0	0
T45	149384	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T7,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T9,T22,T65
1	-	Covered	T3,T7,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T7,T8
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T7,T8
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1015620	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1068	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1015620	0	0
T3	139915	1435	0	0
T7	257391	1137	0	0
T8	291725	3347	0	0
T9	58578	331	0	0
T10	0	1819	0	0
T12	0	9360	0	0
T16	0	725	0	0
T17	0	844	0	0
T19	0	1535	0	0
T21	0	261	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1068	0	0
T3	139915	8	0	0
T7	257391	3	0	0
T8	291725	8	0	0
T9	58578	1	0	0
T10	0	4	0	0
T12	0	6	0	0
T16	0	1	0	0
T17	0	8	0	0
T19	0	4	0	0
T21	0	4	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T51,T17,T18

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T51,T17,T18
1	1	Covered	T51,T17,T18

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T51,T17,T18

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T51,T17,T18
1	1	Covered	T51,T17,T18

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T51,T17,T18
0	0	1	Covered	T51,T17,T18
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T51,T17,T18
0	0	1	Covered	T51,T17,T18
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	2694358	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	3159	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	2694358	0	0
T10	163954	0	0	0
T11	130858	0	0	0
T17	0	10233	0	0
T18	0	33473	0	0
T20	0	8523	0	0
T23	0	35303	0	0
T36	0	70348	0	0
T49	51022	0	0	0
T50	52392	0	0	0
T51	69697	10099	0	0
T52	68303	0	0	0
T53	692564	0	0	0
T54	0	1945	0	0
T59	748035	0	0	0
T66	0	32533	0	0
T67	0	32305	0	0
T68	0	35900	0	0
T69	146556	0	0	0
T70	149248	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	3159	0	0
T10	163954	0	0	0
T11	130858	0	0	0
T17	0	100	0	0
T18	0	20	0	0
T20	0	20	0	0
T23	0	20	0	0
T36	0	40	0	0
T49	51022	0	0	0
T50	52392	0	0	0
T51	69697	20	0	0
T52	68303	0	0	0
T53	692564	0	0	0
T54	0	20	0	0
T59	748035	0	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	0	20	0	0
T69	146556	0	0	0
T70	149248	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T7,T51,T52

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T7,T51,T52
1	1	Covered	T7,T51,T52

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T7,T51,T52

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T51,T52
1	1	Covered	T7,T51,T52

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T7,T51,T52
0	0	1	Covered	T7,T51,T52
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T7,T51,T52
0	0	1	Covered	T7,T51,T52
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	5832295	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	6622	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	5832295	0	0
T7	257391	31237	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T17	0	14943	0	0
T18	0	69050	0	0
T20	0	8922	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T51	69697	384	0	0
T52	0	8962	0	0
T53	0	17120	0	0
T71	0	17371	0	0
T72	0	31639	0	0
T73	0	34026	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	6622	0	0
T7	257391	80	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T17	0	165	0	0
T18	0	41	0	0
T20	0	21	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T51	69697	1	0	0
T52	0	20	0	0
T53	0	20	0	0
T71	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T25,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T25,T3
1	1	Covered	T24,T25,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T25,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T25,T3
1	1	Covered	T24,T25,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T25,T3
0	0	1	Covered	T24,T25,T3
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T25,T3
0	0	1	Covered	T24,T25,T3
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	6816449	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	7659	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	6816449	0	0
T2	80874	0	0	0
T3	139915	1649	0	0
T6	63140	0	0	0
T7	257391	35791	0	0
T8	291725	3725	0	0
T9	58578	338	0	0
T10	0	2318	0	0
T24	220029	958	0	0
T25	119147	2000	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	934	0	0
T51	0	395	0	0
T52	0	9222	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	7659	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	87	0	0
T8	291725	9	0	0
T9	58578	1	0	0
T10	0	5	0	0
T24	220029	1	0	0
T25	119147	1	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T51	0	1	0	0
T52	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T7,T52,T53

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T7,T52,T53
1	1	Covered	T7,T52,T53

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T7,T52,T53

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T52,T53
1	1	Covered	T7,T52,T53

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T7,T52,T53
0	0	1	Covered	T7,T52,T53
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T7,T52,T53
0	0	1	Covered	T7,T52,T53
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	5805558	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	6545	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	5805558	0	0
T7	257391	32056	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T17	0	14666	0	0
T18	0	67559	0	0
T20	0	8487	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T51	69697	0	0	0
T52	0	9108	0	0
T53	0	17269	0	0
T64	0	133786	0	0
T71	0	17605	0	0
T72	0	31782	0	0
T73	0	34260	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	6545	0	0
T7	257391	80	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T17	0	160	0	0
T18	0	40	0	0
T20	0	20	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0
T51	69697	0	0	0
T52	0	20	0	0
T53	0	20	0	0
T64	0	80	0	0
T71	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T2,T6
0	0	1	Covered	T1,T2,T6
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	899035	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1173	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	899035	0	0
T1	78118	326	0	0
T2	80874	472	0	0
T3	139915	0	0	0
T6	63140	374	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T11	0	702	0	0
T13	0	716	0	0
T14	0	1496	0	0
T15	0	1978	0	0
T17	0	208	0	0
T18	0	1915	0	0
T20	0	480	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T26	210577	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1173	0	0
T1	78118	1	0	0
T2	80874	1	0	0
T3	139915	0	0	0
T6	63140	1	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T20	0	1	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T26	210577	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T24,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T24,T2
1	1	Covered	T1,T24,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T24,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T24,T2
1	1	Covered	T1,T24,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T24,T2
0	0	1	Covered	T1,T24,T2
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T1,T24,T2
0	0	1	Covered	T1,T24,T2
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1546467	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1995	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1546467	0	0
T1	78118	318	0	0
T2	80874	459	0	0
T3	139915	1493	0	0
T6	63140	372	0	0
T7	257391	2717	0	0
T8	291725	3519	0	0
T9	58578	301	0	0
T10	0	2290	0	0
T24	220029	793	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T30	0	801	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1995	0	0
T1	78118	1	0	0
T2	80874	1	0	0
T3	139915	9	0	0
T6	63140	1	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	1	0	0
T10	0	5	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T30	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T27,T28

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T27,T28

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T27,T28
0	0	1	Covered	T4,T27,T28
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T27,T28
0	0	1	Covered	T4,T27,T28
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1201405	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1460	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1201405	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T4	370605	6905	0	0
T5	209128	0	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T27	0	3801	0	0
T28	0	6492	0	0
T31	0	3605	0	0
T32	0	6991	0	0
T35	0	4350	0	0
T36	0	8631	0	0
T43	0	4797	0	0
T62	0	5574	0	0
T63	0	4735	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1460	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T4	370605	4	0	0
T5	209128	0	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T27	0	5	0	0
T28	0	4	0	0
T31	0	4	0	0
T32	0	4	0	0
T35	0	4	0	0
T36	0	5	0	0
T43	0	3	0	0
T62	0	5	0	0
T63	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T27,T28

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T4,T27,T28

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T27,T28
1	1	Covered	T4,T27,T28

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T27,T28
0	0	1	Covered	T4,T27,T28
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T4,T27,T28
0	0	1	Covered	T4,T27,T28
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1053381	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1327	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1053381	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T4	370605	5413	0	0
T5	209128	0	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T27	0	2112	0	0
T28	0	4982	0	0
T31	0	2824	0	0
T32	0	5469	0	0
T35	0	3343	0	0
T36	0	4762	0	0
T43	0	4780	0	0
T62	0	3401	0	0
T63	0	3696	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1327	0	0
T1	78118	0	0	0
T2	80874	0	0	0
T3	139915	0	0	0
T4	370605	3	0	0
T5	209128	0	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T24	220029	0	0	0
T25	119147	0	0	0
T27	0	3	0	0
T28	0	3	0	0
T31	0	3	0	0
T32	0	3	0	0
T35	0	3	0	0
T36	0	3	0	0
T43	0	3	0	0
T62	0	3	0	0
T63	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	6163652	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	7237	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	6163652	0	0
T2	80874	0	0	0
T3	139915	11515	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	43351	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	41489	0	0
T55	0	114447	0	0
T59	0	89874	0	0
T60	0	28100	0	0
T61	0	127635	0	0
T74	0	42023	0	0
T75	0	34565	0	0
T76	0	106969	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	7237	0	0
T2	80874	0	0	0
T3	139915	64	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	51	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	51	0	0
T55	0	70	0	0
T59	0	51	0	0
T60	0	65	0	0
T61	0	80	0	0
T74	0	51	0	0
T75	0	75	0	0
T76	0	79	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	6132216	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	7307	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	6132216	0	0
T2	80874	0	0	0
T3	139915	14024	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	42668	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	40757	0	0
T55	0	141319	0	0
T59	0	88767	0	0
T60	0	28096	0	0
T61	0	141107	0	0
T74	0	40915	0	0
T75	0	32977	0	0
T76	0	105782	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	7307	0	0
T2	80874	0	0	0
T3	139915	84	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	51	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	51	0	0
T55	0	87	0	0
T59	0	51	0	0
T60	0	67	0	0
T61	0	89	0	0
T74	0	51	0	0
T75	0	75	0	0
T76	0	79	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	5883294	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	7169	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	5883294	0	0
T2	80874	0	0	0
T3	139915	13673	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	41889	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	40000	0	0
T55	0	103696	0	0
T59	0	87656	0	0
T60	0	30379	0	0
T61	0	120155	0	0
T74	0	39871	0	0
T75	0	31305	0	0
T76	0	70905	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	7169	0	0
T2	80874	0	0	0
T3	139915	84	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	51	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	51	0	0
T55	0	65	0	0
T59	0	51	0	0
T60	0	74	0	0
T61	0	76	0	0
T74	0	51	0	0
T75	0	75	0	0
T76	0	53	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	5829732	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	7185	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	5829732	0	0
T2	80874	0	0	0
T3	139915	13609	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	41156	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	39308	0	0
T55	0	114597	0	0
T59	0	86566	0	0
T60	0	20037	0	0
T61	0	107568	0	0
T74	0	38839	0	0
T75	0	20206	0	0
T76	0	103803	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	7185	0	0
T2	80874	0	0	0
T3	139915	80	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	51	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	51	0	0
T55	0	73	0	0
T59	0	51	0	0
T60	0	52	0	0
T61	0	68	0	0
T74	0	51	0	0
T75	0	51	0	0
T76	0	79	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1028312	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1336	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1028312	0	0
T2	80874	0	0	0
T3	139915	1648	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	946	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	931	0	0
T55	0	6667	0	0
T59	0	1946	0	0
T60	0	846	0	0
T61	0	6434	0	0
T74	0	705	0	0
T75	0	534	0	0
T76	0	4328	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1336	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T55	0	4	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	4	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1014296	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1312	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1014296	0	0
T2	80874	0	0	0
T3	139915	1467	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	908	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	899	0	0
T55	0	6476	0	0
T59	0	1887	0	0
T60	0	767	0	0
T61	0	6394	0	0
T74	0	658	0	0
T75	0	484	0	0
T76	0	4236	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1312	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T55	0	4	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	4	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1070136	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1355	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1070136	0	0
T2	80874	0	0	0
T3	139915	1466	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	881	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	864	0	0
T55	0	6303	0	0
T59	0	1826	0	0
T60	0	707	0	0
T61	0	6354	0	0
T74	0	613	0	0
T75	0	444	0	0
T76	0	4108	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1355	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T55	0	4	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	4	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T30
1	1	Covered	T24,T3,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T30
0	0	1	Covered	T24,T3,T30
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1039518	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1350	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1039518	0	0
T2	80874	0	0	0
T3	139915	1514	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	836	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	830	0	0
T55	0	6104	0	0
T59	0	1771	0	0
T60	0	766	0	0
T61	0	6314	0	0
T74	0	561	0	0
T75	0	529	0	0
T76	0	4003	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1350	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	0	0	0
T8	291725	0	0	0
T9	58578	0	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T55	0	4	0	0
T59	0	1	0	0
T60	0	2	0	0
T61	0	4	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	6643315	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	7809	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	6643315	0	0
T2	80874	0	0	0
T3	139915	11671	0	0
T6	63140	0	0	0
T7	257391	2849	0	0
T8	291725	3753	0	0
T9	58578	332	0	0
T10	0	2382	0	0
T12	0	28432	0	0
T24	220029	43658	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	41859	0	0
T53	0	8959	0	0
T59	0	90373	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	7809	0	0
T2	80874	0	0	0
T3	139915	64	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	1	0	0
T10	0	5	0	0
T12	0	17	0	0
T24	220029	51	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	51	0	0
T53	0	10	0	0
T59	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	6612426	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	7818	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	6612426	0	0
T2	80874	0	0	0
T3	139915	14923	0	0
T6	63140	0	0	0
T7	257391	2781	0	0
T8	291725	3735	0	0
T9	58578	0	0	0
T10	0	2321	0	0
T12	0	28293	0	0
T17	0	902	0	0
T24	220029	42960	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	41113	0	0
T53	0	7889	0	0
T59	0	89281	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	7818	0	0
T2	80874	0	0	0
T3	139915	84	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	0	0	0
T10	0	5	0	0
T12	0	17	0	0
T17	0	9	0	0
T24	220029	51	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	51	0	0
T53	0	9	0	0
T59	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	6325561	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	7673	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	6325561	0	0
T2	80874	0	0	0
T3	139915	14072	0	0
T6	63140	0	0	0
T7	257391	2709	0	0
T8	291725	3717	0	0
T9	58578	0	0	0
T10	0	2289	0	0
T12	0	28124	0	0
T17	0	906	0	0
T24	220029	42234	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	40349	0	0
T53	0	7826	0	0
T59	0	88153	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	7673	0	0
T2	80874	0	0	0
T3	139915	84	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	0	0	0
T10	0	5	0	0
T12	0	17	0	0
T17	0	9	0	0
T24	220029	51	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	51	0	0
T53	0	9	0	0
T59	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	6319264	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	7712	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	6319264	0	0
T2	80874	0	0	0
T3	139915	13429	0	0
T6	63140	0	0	0
T7	257391	2624	0	0
T8	291725	3699	0	0
T9	58578	0	0	0
T10	0	2232	0	0
T12	0	27963	0	0
T17	0	982	0	0
T24	220029	41477	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	39648	0	0
T53	0	7767	0	0
T59	0	87090	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	7712	0	0
T2	80874	0	0	0
T3	139915	80	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	0	0	0
T10	0	5	0	0
T12	0	17	0	0
T17	0	9	0	0
T24	220029	51	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	51	0	0
T53	0	9	0	0
T59	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1519239	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1924	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1519239	0	0
T2	80874	0	0	0
T3	139915	1499	0	0
T6	63140	0	0	0
T7	257391	2562	0	0
T8	291725	3681	0	0
T9	58578	328	0	0
T10	0	2183	0	0
T12	0	27803	0	0
T24	220029	933	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	921	0	0
T53	0	8682	0	0
T59	0	1921	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1924	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	1	0	0
T10	0	5	0	0
T12	0	17	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T53	0	10	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1395749	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1808	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1395749	0	0
T2	80874	0	0	0
T3	139915	1564	0	0
T6	63140	0	0	0
T7	257391	2492	0	0
T8	291725	3663	0	0
T9	58578	0	0	0
T10	0	2127	0	0
T12	0	27620	0	0
T17	0	949	0	0
T24	220029	894	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	886	0	0
T53	0	7649	0	0
T59	0	1863	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1808	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	0	0	0
T10	0	5	0	0
T12	0	17	0	0
T17	0	9	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T53	0	9	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1471166	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1875	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1471166	0	0
T2	80874	0	0	0
T3	139915	1564	0	0
T6	63140	0	0	0
T7	257391	2405	0	0
T8	291725	3645	0	0
T9	58578	0	0	0
T10	0	2052	0	0
T12	0	27457	0	0
T17	0	969	0	0
T24	220029	861	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	845	0	0
T53	0	7595	0	0
T59	0	1803	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1875	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	0	0	0
T10	0	5	0	0
T12	0	17	0	0
T17	0	9	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T53	0	9	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1414449	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1839	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1414449	0	0
T2	80874	0	0	0
T3	139915	1535	0	0
T6	63140	0	0	0
T7	257391	2342	0	0
T8	291725	3627	0	0
T9	58578	0	0	0
T10	0	1992	0	0
T12	0	27258	0	0
T17	0	922	0	0
T24	220029	814	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	822	0	0
T53	0	7519	0	0
T59	0	1744	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1839	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	0	0	0
T10	0	5	0	0
T12	0	17	0	0
T17	0	9	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T53	0	9	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1511316	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1929	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1511316	0	0
T2	80874	0	0	0
T3	139915	1470	0	0
T6	63140	0	0	0
T7	257391	2258	0	0
T8	291725	3609	0	0
T9	58578	316	0	0
T10	0	1952	0	0
T12	0	27084	0	0
T24	220029	926	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	914	0	0
T53	0	8415	0	0
T59	0	1914	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1929	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	1	0	0
T10	0	5	0	0
T12	0	17	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T53	0	10	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1481194	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1887	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1481194	0	0
T2	80874	0	0	0
T3	139915	1523	0	0
T6	63140	0	0	0
T7	257391	2183	0	0
T8	291725	3591	0	0
T9	58578	0	0	0
T10	0	1893	0	0
T12	0	26922	0	0
T17	0	884	0	0
T24	220029	892	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	880	0	0
T53	0	7392	0	0
T59	0	1856	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1887	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	0	0	0
T10	0	5	0	0
T12	0	17	0	0
T17	0	9	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T53	0	9	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1409332	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1838	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1409332	0	0
T2	80874	0	0	0
T3	139915	1524	0	0
T6	63140	0	0	0
T7	257391	2335	0	0
T8	291725	3573	0	0
T9	58578	0	0	0
T10	0	2071	0	0
T12	0	26721	0	0
T17	0	948	0	0
T24	220029	851	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	843	0	0
T53	0	7335	0	0
T59	0	1791	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1838	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	0	0	0
T10	0	5	0	0
T12	0	17	0	0
T17	0	9	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T53	0	9	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T3,T7
1	1	Covered	T24,T3,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T24,T3,T7
0	0	1	Covered	T24,T3,T7
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	1416867	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	1850	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1416867	0	0
T2	80874	0	0	0
T3	139915	1555	0	0
T6	63140	0	0	0
T7	257391	2503	0	0
T8	291725	3555	0	0
T9	58578	0	0	0
T10	0	2376	0	0
T12	0	26522	0	0
T17	0	951	0	0
T24	220029	808	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	820	0	0
T53	0	7256	0	0
T59	0	1730	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1850	0	0
T2	80874	0	0	0
T3	139915	9	0	0
T6	63140	0	0	0
T7	257391	7	0	0
T8	291725	9	0	0
T9	58578	0	0	0
T10	0	5	0	0
T12	0	17	0	0
T17	0	9	0	0
T24	220029	1	0	0
T25	119147	0	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T30	0	1	0	0
T53	0	9	0	0
T59	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T3,T7,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Not Covered
1	1	Covered	T3,T7,T8

---

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T7,T8
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T1
0	1	-	Covered	T3,T7,T8
0	0	1	Covered	T3,T7,T8
0	0	0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1193245780	915537	0	0
DstReqKnown_A	7166523	6319419	0	0
SrcAckBusyChk_A	1193245780	987	0	0
SrcBusyKnown_A	1193245780	1191549265	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	915537	0	0
T3	139915	1281	0	0
T7	257391	1088	0	0
T8	291725	3331	0	0
T9	58578	349	0	0
T10	0	1754	0	0
T12	0	9310	0	0
T17	0	751	0	0
T19	0	1531	0	0
T21	0	279	0	0
T22	0	162	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7166523	6319419	0	0
T1	678	278	0	0
T2	915	515	0	0
T3	25438	24991	0	0
T4	748	348	0	0
T5	254446	254046	0	0
T6	505	105	0	0
T7	21449	19016	0	0
T8	23338	22884	0	0
T24	9167	8767	0	0
T25	238296	237896	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	987	0	0
T3	139915	8	0	0
T7	257391	3	0	0
T8	291725	8	0	0
T9	58578	1	0	0
T10	0	4	0	0
T12	0	6	0	0
T17	0	7	0	0
T19	0	4	0	0
T21	0	4	0	0
T22	0	1	0	0
T26	210577	0	0	0
T27	170033	0	0	0
T28	730777	0	0	0
T29	55977	0	0	0
T30	119089	0	0	0
T31	191153	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193245780	1191549265	0	0
T1	78118	78052	0	0
T2	80874	80800	0	0
T3	139915	139647	0	0
T4	370605	370517	0	0
T5	209128	209029	0	0
T6	63140	63051	0	0
T7	257391	256945	0	0
T8	291725	291043	0	0
T24	220029	220020	0	0
T25	119147	119147	0	0