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Module Instance : tb.dut.u_reg.u_key_intr_status_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.76 100.00 88.73 98.31 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.61 100.00 94.44 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.36 100.00 87.76 97.67 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

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Module Instances:
tb.dut.u_reg.u_key_intr_status_cdc
Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN5411100.00
ALWAYS6066100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN9811100.00
ALWAYS10499100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN18711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 1 1
60 1 1
61 1 1
62 1 1
63 1 1
64 1 1
65 1 1
MISSING_ELSE
74 1 1
98 1 1
104 1 1
105 1 1
106 1 1
107 1 1
112 1 1
113 1 1
114 1 1
123 1 1
124 1 1
MISSING_ELSE
139 1 1
144 1 1
145 1 1
187 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT4,T5,T1
01Unreachable
10CoveredT1,T2,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT4,T5,T1
10CoveredT1,T2,T6
11CoveredT1,T2,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT4,T5,T1
01CoveredT1,T2,T11
10CoveredT1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T6
11CoveredT1,T2,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT4,T5,T1
10Not Covered
11CoveredT1,T2,T11

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 4 4 100.00
IF 104 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 60 if ((!rst_src_ni)) -2-: 62 if (src_req) -3-: 64 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T6
0 0 1 Covered T1,T2,T6
0 0 0 Covered T4,T5,T1


LineNo. Expression -1-: 104 if ((!rst_src_ni)) -2-: 107 if (src_req) -3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T1
0 1 - Covered T1,T2,T6
0 0 1 Covered T1,T2,T6
0 0 0 Covered T4,T5,T1


Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1193245780 743449 0 0
DstReqKnown_A 7166523 6319419 0 0
SrcAckBusyChk_A 1193245780 764 0 0
SrcBusyKnown_A 1193245780 1191549265 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1193245780 743449 0 0
T1 78118 309 0 0
T2 80874 878 0 0
T3 139915 0 0 0
T6 63140 371 0 0
T7 257391 0 0 0
T8 291725 0 0 0
T9 58578 0 0 0
T11 0 694 0 0
T13 0 698 0 0
T14 0 1494 0 0
T15 0 3398 0 0
T17 0 161 0 0
T18 0 1897 0 0
T20 0 474 0 0
T24 220029 0 0 0
T25 119147 0 0 0
T26 210577 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7166523 6319419 0 0
T1 678 278 0 0
T2 915 515 0 0
T3 25438 24991 0 0
T4 748 348 0 0
T5 254446 254046 0 0
T6 505 105 0 0
T7 21449 19016 0 0
T8 23338 22884 0 0
T24 9167 8767 0 0
T25 238296 237896 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1193245780 764 0 0
T1 78118 1 0 0
T2 80874 2 0 0
T3 139915 0 0 0
T6 63140 1 0 0
T7 257391 0 0 0
T8 291725 0 0 0
T9 58578 0 0 0
T11 0 1 0 0
T13 0 1 0 0
T14 0 1 0 0
T15 0 2 0 0
T17 0 2 0 0
T18 0 1 0 0
T20 0 1 0 0
T24 220029 0 0 0
T25 119147 0 0 0
T26 210577 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1193245780 1191549265 0 0
T1 78118 78052 0 0
T2 80874 80800 0 0
T3 139915 139647 0 0
T4 370605 370517 0 0
T5 209128 209029 0 0
T6 63140 63051 0 0
T7 257391 256945 0 0
T8 291725 291043 0 0
T24 220029 220020 0 0
T25 119147 119147 0 0

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