Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_lid_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_pwrb_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	92.31			100.00	100.00	u_ulp_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.88	100.00	87.50			100.00	100.00	u_wkup_status_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_key_invert_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_pin_allowed_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_pin_out_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_pin_out_value_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_key_intr_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_key_intr_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_auto_block_debounce_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_auto_block_out_ctl_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_sel_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_pre_det_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_sel_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_det_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_com_out_ctl_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T24,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T24,T25,T26
1	1	Covered	T1,T2,T13

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	227580	0	0
SrcPulseCheck_M	2147483647	229778	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	227580	0	0
T1	7548150	51	0	0
T2	19384100	68	0	0
T3	8061950	0	0	0
T4	547200	144	0	0
T5	2238369	51	0	0
T6	199260	0	0	0
T7	109227	0	0	0
T8	0	153	0	0
T9	0	119	0	0
T12	1398025	0	0	0
T13	19656350	96	0	0
T14	1815190	0	0	0
T15	11131536	17	0	0
T16	6445088	0	0	0
T17	5496712	0	0	0
T18	8763216	16	0	0
T24	125431	148	0	0
T30	0	16	0	0
T34	0	80	0	0
T40	0	28	0	0
T42	0	14	0	0
T43	0	14	0	0
T44	0	1	0	0
T45	0	14	0	0
T46	0	1	0	0
T47	0	14	0	0
T48	0	16	0	0
T49	0	18	0	0
T50	787340	0	0	0
T51	52448	0	0	0
T52	613320	0	0	0
T53	435939	0	0	0
T54	605256	0	0	0
T55	217554	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	229778	0	0
T1	7548150	51	0	0
T2	19384100	68	0	0
T3	8061950	0	0	0
T4	547200	144	0	0
T5	2238369	51	0	0
T6	199260	0	0	0
T7	109227	0	0	0
T8	0	153	0	0
T9	0	119	0	0
T12	1398025	0	0	0
T13	19656350	96	0	0
T14	1815190	0	0	0
T15	11131536	17	0	0
T16	6445088	0	0	0
T17	5496712	0	0	0
T18	8763216	16	0	0
T24	247596	148	0	0
T30	0	16	0	0
T34	0	80	0	0
T40	0	28	0	0
T42	0	14	0	0
T43	0	14	0	0
T44	0	1	0	0
T45	0	14	0	0
T46	0	1	0	0
T47	0	14	0	0
T48	0	16	0	0
T49	0	18	0	0
T50	787340	0	0	0
T51	52448	0	0	0
T52	613320	0	0	0
T53	435939	0	0	0
T54	605256	0	0	0
T55	217554	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T33,T22,T23

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T33,T22,T23
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1998	0	0
SrcPulseCheck_M	1030591197	2059	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1998	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	1	0	0
T17	422	0	0	0
T18	672	0	0	0
T50	0	1	0	0
T53	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2059	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	1	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T50	0	1	0	0
T53	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T33,T22,T23

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T33,T22,T23
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	2055	0	0
SrcPulseCheck_M	9420022	2055	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2055	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	1	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T50	0	1	0	0
T53	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	2055	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	1	0	0
T17	422	0	0	0
T18	672	0	0	0
T50	0	1	0	0
T53	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T25,T26,T61

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T25,T26,T61
1	1	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1122	0	0
SrcPulseCheck_M	1030591197	1179	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1122	0	0
T24	247596	8	0	0
T25	1657	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	16125	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1179	0	0
T24	125431	8	0	0
T25	46039	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	733708	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T25,T26,T61

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T25,T26,T61
1	1	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1176	0	0
SrcPulseCheck_M	9420022	1176	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1176	0	0
T24	125431	8	0	0
T25	46039	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	733708	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1176	0	0
T24	247596	8	0	0
T25	1657	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	16125	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T25,T26,T61

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T25,T26,T61
1	1	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1105	0	0
SrcPulseCheck_M	1030591197	1170	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1105	0	0
T24	247596	8	0	0
T25	1657	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	16125	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1170	0	0
T24	125431	8	0	0
T25	46039	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	733708	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T25,T26,T61

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T25,T26,T61
1	1	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1166	0	0
SrcPulseCheck_M	9420022	1166	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1166	0	0
T24	125431	8	0	0
T25	46039	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	733708	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1166	0	0
T24	247596	8	0	0
T25	1657	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	16125	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T25,T26,T61

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T25,T26,T61
1	1	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1091	0	0
SrcPulseCheck_M	1030591197	1151	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1091	0	0
T24	247596	8	0	0
T25	1657	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	16125	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1151	0	0
T24	125431	8	0	0
T25	46039	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	733708	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T25,T26,T61

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T25,T26,T61
1	1	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1147	0	0
SrcPulseCheck_M	9420022	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1147	0	0
T24	125431	8	0	0
T25	46039	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	733708	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1147	0	0
T24	247596	8	0	0
T25	1657	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	16125	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1072	0	0
SrcPulseCheck_M	1030591197	1138	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1072	0	0
T24	247596	6	0	0
T25	1657	4	0	0
T26	0	2	0	0
T49	0	2	0	0
T58	16125	0	0	0
T61	0	2	0	0
T62	0	4	0	0
T64	0	4	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1138	0	0
T24	125431	6	0	0
T25	46039	4	0	0
T26	0	2	0	0
T49	0	2	0	0
T58	733708	0	0	0
T61	0	2	0	0
T62	0	4	0	0
T64	0	4	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1134	0	0
SrcPulseCheck_M	9420022	1134	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1134	0	0
T24	125431	6	0	0
T25	46039	4	0	0
T26	0	2	0	0
T49	0	2	0	0
T58	733708	0	0	0
T61	0	2	0	0
T62	0	4	0	0
T64	0	4	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1134	0	0
T24	247596	6	0	0
T25	1657	4	0	0
T26	0	2	0	0
T49	0	2	0	0
T58	16125	0	0	0
T61	0	2	0	0
T62	0	4	0	0
T64	0	4	0	0
T65	449	0	0	0
T66	522	0	0	0
T67	1309	0	0	0
T68	413	0	0	0
T69	494	0	0	0
T70	502	0	0	0
T71	402	0	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T58,T25,T96

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T4
1	0	Covered	T58,T25,T96
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1177	0	0
SrcPulseCheck_M	1030591197	1246	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1177	0	0
T1	11840	1	0	0
T2	15507	3	0	0
T3	625	0	0	0
T4	0	8	0	0
T5	0	1	0	0
T8	0	6	0	0
T9	0	2	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	3	0	0
T25	0	2	0	0
T34	0	4	0	0
T58	0	3	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1246	0	0
T1	290086	1	0	0
T2	759857	3	0	0
T3	309450	0	0	0
T4	0	8	0	0
T5	0	1	0	0
T8	0	6	0	0
T9	0	2	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	3	0	0
T25	0	2	0	0
T34	0	4	0	0
T58	0	3	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T14,T27,T24
1	0	Covered	T14,T27,T24
1	1	Covered	T14,T27,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T14,T27,T24
1	0	Covered	T14,T27,T24
1	1	Covered	T14,T27,T24

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	2925	0	0
SrcPulseCheck_M	1030591197	2991	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	2925	0	0
T3	625	0	0	0
T4	22800	0	0	0
T14	494	20	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	80	0	0
T27	0	20	0	0
T30	0	60	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T69	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0
T75	0	20	0	0
T76	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2991	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T14	69321	20	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	80	0	0
T27	0	20	0	0
T30	0	60	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T69	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0
T75	0	20	0	0
T76	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T14,T27,T24
1	0	Covered	T14,T27,T24
1	1	Covered	T14,T27,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T14,T27,T24
1	0	Covered	T14,T27,T24
1	1	Covered	T14,T27,T24

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	2987	0	0
SrcPulseCheck_M	9420022	2987	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2987	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T14	69321	20	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	80	0	0
T27	0	20	0	0
T30	0	60	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T69	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0
T75	0	20	0	0
T76	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	2987	0	0
T3	625	0	0	0
T4	22800	0	0	0
T14	494	20	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	80	0	0
T27	0	20	0	0
T30	0	60	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T69	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0
T75	0	20	0	0
T76	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T14,T27
1	0	Covered	T6,T14,T27
1	1	Covered	T6,T28,T29

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T14,T27
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	5869	0	0
SrcPulseCheck_M	1030591197	5932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	5869	0	0
T1	11840	0	0	0
T2	15507	0	0	0
T6	507	20	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	1	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	164	0	0
T27	0	1	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T69	0	1	0	0
T77	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5932	0	0
T1	290086	0	0	0
T2	759857	0	0	0
T6	65913	20	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	1	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	164	0	0
T27	0	1	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T69	0	1	0	0
T77	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T14,T27
1	0	Covered	T6,T14,T27
1	1	Covered	T6,T28,T29

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T14,T27
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T14,T27

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	5921	0	0
SrcPulseCheck_M	9420022	5921	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5921	0	0
T1	290086	0	0	0
T2	759857	0	0	0
T6	65913	20	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	1	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	164	0	0
T27	0	1	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T69	0	1	0	0
T77	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	5921	0	0
T1	11840	0	0	0
T2	15507	0	0	0
T6	507	20	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	1	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	164	0	0
T27	0	1	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T69	0	1	0	0
T77	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T28,T29

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T1,T2

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	6919	0	0
SrcPulseCheck_M	1030591197	6993	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	6919	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T4	0	9	0	0
T6	507	20	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	1	0	0
T15	16466	1	0	0
T16	515	1	0	0
T17	422	0	0	0
T18	672	0	0	0
T50	0	1	0	0
T53	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6993	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T4	0	9	0	0
T6	65913	20	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	1	0	0
T15	411670	1	0	0
T16	247373	1	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T50	0	1	0	0
T53	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T28,T29

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T1,T2

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	6982	0	0
SrcPulseCheck_M	9420022	6982	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6982	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T4	0	9	0	0
T6	65913	20	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	1	0	0
T15	411670	1	0	0
T16	247373	1	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T50	0	1	0	0
T53	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	6982	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T4	0	9	0	0
T6	507	20	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	1	0	0
T15	16466	1	0	0
T16	515	1	0	0
T17	422	0	0	0
T18	672	0	0	0
T50	0	1	0	0
T53	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T28,T29
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T28,T29

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T28,T29
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T28,T29

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	5776	0	0
SrcPulseCheck_M	1030591197	5849	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	5776	0	0
T1	11840	0	0	0
T2	15507	0	0	0
T6	507	20	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	160	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T70	0	20	0	0
T77	0	20	0	0
T78	0	20	0	0
T79	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5849	0	0
T1	290086	0	0	0
T2	759857	0	0	0
T6	65913	20	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	160	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T70	0	20	0	0
T77	0	20	0	0
T78	0	20	0	0
T79	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T28,T29
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T28,T29

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T6,T28,T29
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T28,T29

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	5839	0	0
SrcPulseCheck_M	9420022	5839	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5839	0	0
T1	290086	0	0	0
T2	759857	0	0	0
T6	65913	20	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	160	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T70	0	20	0	0
T77	0	20	0	0
T78	0	20	0	0
T79	0	20	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	5839	0	0
T1	11840	0	0	0
T2	15507	0	0	0
T6	507	20	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	0	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	160	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T70	0	20	0	0
T77	0	20	0	0
T78	0	20	0	0
T79	0	20	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T3,T7,T10
1	0	Covered	T56,T57,T33
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1090	0	0
SrcPulseCheck_M	1030591197	1151	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1090	0	0
T3	625	1	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T24	0	3	0	0
T30	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T80	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1151	0	0
T3	309450	1	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T24	0	3	0	0
T30	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T80	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T3,T7,T10
1	0	Covered	T56,T57,T33
1	1	Covered	T3,T7,T10

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1146	0	0
SrcPulseCheck_M	9420022	1146	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1146	0	0
T3	309450	1	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T24	0	3	0	0
T30	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T80	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1146	0	0
T3	625	1	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T24	0	3	0	0
T30	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0
T55	434	0	0	0
T80	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	2040	0	0
SrcPulseCheck_M	1030591197	2103	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	2040	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	1	0	0
T4	0	9	0	0
T5	0	3	0	0
T7	0	1	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2103	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	1	0	0
T4	0	9	0	0
T5	0	3	0	0
T7	0	1	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	2099	0	0
SrcPulseCheck_M	9420022	2099	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2099	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	1	0	0
T4	0	9	0	0
T5	0	3	0	0
T7	0	1	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	2099	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	1	0	0
T4	0	9	0	0
T5	0	3	0	0
T7	0	1	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T18,T24,T30
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T18,T24,T30
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1386	0	0
SrcPulseCheck_M	1030591197	1448	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1386	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	5	0	0
T24	0	5	0	0
T30	0	5	0	0
T40	0	8	0	0
T42	0	4	0	0
T43	0	4	0	0
T45	0	4	0	0
T47	0	4	0	0
T48	0	5	0	0
T49	0	6	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1448	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	0	0	0
T18	312300	5	0	0
T24	0	5	0	0
T30	0	5	0	0
T40	0	8	0	0
T42	0	4	0	0
T43	0	4	0	0
T45	0	4	0	0
T47	0	4	0	0
T48	0	5	0	0
T49	0	6	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T18,T24,T30
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T18,T24,T30
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1445	0	0
SrcPulseCheck_M	9420022	1445	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1445	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	0	0	0
T18	312300	5	0	0
T24	0	5	0	0
T30	0	5	0	0
T40	0	8	0	0
T42	0	4	0	0
T43	0	4	0	0
T45	0	4	0	0
T47	0	4	0	0
T48	0	5	0	0
T49	0	6	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1445	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	5	0	0
T24	0	5	0	0
T30	0	5	0	0
T40	0	8	0	0
T42	0	4	0	0
T43	0	4	0	0
T45	0	4	0	0
T47	0	4	0	0
T48	0	5	0	0
T49	0	6	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T18,T24,T30
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T18,T24,T30
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1256	0	0
SrcPulseCheck_M	1030591197	1320	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1256	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	3	0	0
T24	0	3	0	0
T30	0	3	0	0
T40	0	6	0	0
T42	0	3	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1320	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	0	0	0
T18	312300	3	0	0
T24	0	3	0	0
T30	0	3	0	0
T40	0	6	0	0
T42	0	3	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T18,T24,T30
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T18,T24,T30
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1316	0	0
SrcPulseCheck_M	9420022	1316	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1316	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	0	0	0
T18	312300	3	0	0
T24	0	3	0	0
T30	0	3	0	0
T40	0	6	0	0
T42	0	3	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1316	0	0
T3	625	0	0	0
T4	22800	0	0	0
T5	16581	0	0	0
T7	649	0	0	0
T18	672	3	0	0
T24	0	3	0	0
T30	0	3	0	0
T40	0	6	0	0
T42	0	3	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	800	0	0	0
T51	422	0	0	0
T52	1217	0	0	0
T53	705	0	0	0
T54	402	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	7095	0	0
SrcPulseCheck_M	1030591197	7162	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7095	0	0
T1	11840	73	0	0
T2	15507	77	0	0
T3	625	0	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T81	0	1	0	0
T82	0	69	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7162	0	0
T1	290086	73	0	0
T2	759857	77	0	0
T3	309450	0	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T81	0	1	0	0
T82	0	69	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	7158	0	0
SrcPulseCheck_M	9420022	7158	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7158	0	0
T1	290086	73	0	0
T2	759857	77	0	0
T3	309450	0	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T81	0	1	0	0
T82	0	69	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7158	0	0
T1	11840	73	0	0
T2	15507	77	0	0
T3	625	0	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T81	0	1	0	0
T82	0	69	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	7005	0	0
SrcPulseCheck_M	1030591197	7066	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7005	0	0
T1	11840	83	0	0
T2	15507	78	0	0
T3	625	0	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	59	0	0
T83	0	51	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7066	0	0
T1	290086	83	0	0
T2	759857	78	0	0
T3	309450	0	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	59	0	0
T83	0	51	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	7062	0	0
SrcPulseCheck_M	9420022	7062	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7062	0	0
T1	290086	83	0	0
T2	759857	78	0	0
T3	309450	0	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	59	0	0
T83	0	51	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7062	0	0
T1	11840	83	0	0
T2	15507	78	0	0
T3	625	0	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	59	0	0
T83	0	51	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	6935	0	0
SrcPulseCheck_M	1030591197	7001	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	6935	0	0
T1	11840	60	0	0
T2	15507	71	0	0
T3	625	0	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	69	0	0
T83	0	51	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7001	0	0
T1	290086	60	0	0
T2	759857	71	0	0
T3	309450	0	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	69	0	0
T83	0	51	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	6997	0	0
SrcPulseCheck_M	9420022	6997	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6997	0	0
T1	290086	60	0	0
T2	759857	71	0	0
T3	309450	0	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	69	0	0
T83	0	51	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	6997	0	0
T1	11840	60	0	0
T2	15507	71	0	0
T3	625	0	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	69	0	0
T83	0	51	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	6941	0	0
SrcPulseCheck_M	1030591197	7004	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	6941	0	0
T1	11840	83	0	0
T2	15507	54	0	0
T3	625	0	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	79	0	0
T83	0	51	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7004	0	0
T1	290086	83	0	0
T2	759857	54	0	0
T3	309450	0	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	79	0	0
T83	0	51	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	7001	0	0
SrcPulseCheck_M	9420022	7001	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7001	0	0
T1	290086	83	0	0
T2	759857	54	0	0
T3	309450	0	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	79	0	0
T83	0	51	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7001	0	0
T1	11840	83	0	0
T2	15507	54	0	0
T3	625	0	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	79	0	0
T83	0	51	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1275	0	0
SrcPulseCheck_M	1030591197	1334	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1275	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1334	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1329	0	0
SrcPulseCheck_M	9420022	1329	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1329	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1329	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1295	0	0
SrcPulseCheck_M	1030591197	1360	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1295	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1360	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1354	0	0
SrcPulseCheck_M	9420022	1354	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1354	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1354	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1276	0	0
SrcPulseCheck_M	1030591197	1338	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1276	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1338	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1333	0	0
SrcPulseCheck_M	9420022	1333	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1333	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1333	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1312	0	0
SrcPulseCheck_M	1030591197	1374	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1312	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1374	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T15
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T15
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1370	0	0
SrcPulseCheck_M	9420022	1370	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1370	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1370	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	0	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	7675	0	0
SrcPulseCheck_M	1030591197	7738	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7675	0	0
T1	11840	73	0	0
T2	15507	77	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	9	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7738	0	0
T1	290086	73	0	0
T2	759857	77	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	7735	0	0
SrcPulseCheck_M	9420022	7735	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7735	0	0
T1	290086	73	0	0
T2	759857	77	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7735	0	0
T1	11840	73	0	0
T2	15507	77	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	9	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	7581	0	0
SrcPulseCheck_M	1030591197	7649	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7581	0	0
T1	11840	83	0	0
T2	15507	78	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7649	0	0
T1	290086	83	0	0
T2	759857	78	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	7645	0	0
SrcPulseCheck_M	9420022	7645	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7645	0	0
T1	290086	83	0	0
T2	759857	78	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7645	0	0
T1	11840	83	0	0
T2	15507	78	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	7558	0	0
SrcPulseCheck_M	1030591197	7622	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7558	0	0
T1	11840	60	0	0
T2	15507	71	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7622	0	0
T1	290086	60	0	0
T2	759857	71	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	7617	0	0
SrcPulseCheck_M	9420022	7617	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7617	0	0
T1	290086	60	0	0
T2	759857	71	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7617	0	0
T1	11840	60	0	0
T2	15507	71	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	7550	0	0
SrcPulseCheck_M	1030591197	7619	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7550	0	0
T1	11840	83	0	0
T2	15507	54	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7619	0	0
T1	290086	83	0	0
T2	759857	54	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	7612	0	0
SrcPulseCheck_M	9420022	7612	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7612	0	0
T1	290086	83	0	0
T2	759857	54	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	7612	0	0
T1	11840	83	0	0
T2	15507	54	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	51	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1952	0	0
SrcPulseCheck_M	1030591197	2023	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1952	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	9	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2023	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	2020	0	0
SrcPulseCheck_M	9420022	2020	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2020	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	2020	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	9	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1874	0	0
SrcPulseCheck_M	1030591197	1935	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1874	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1935	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1932	0	0
SrcPulseCheck_M	9420022	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1932	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1932	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1876	0	0
SrcPulseCheck_M	1030591197	1937	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1876	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1937	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1932	0	0
SrcPulseCheck_M	9420022	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1932	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1932	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1852	0	0
SrcPulseCheck_M	1030591197	1920	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1852	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1920	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1918	0	0
SrcPulseCheck_M	9420022	1918	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1918	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1918	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1960	0	0
SrcPulseCheck_M	1030591197	2026	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1960	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	9	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2026	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	2022	0	0
SrcPulseCheck_M	9420022	2022	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2022	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	2022	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	9	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1868	0	0
SrcPulseCheck_M	1030591197	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1868	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1932	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1927	0	0
SrcPulseCheck_M	9420022	1927	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1927	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1927	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1827	0	0
SrcPulseCheck_M	1030591197	1895	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1827	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1895	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1892	0	0
SrcPulseCheck_M	9420022	1892	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1892	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1892	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	9420022	1858	0	0
SrcPulseCheck_M	1030591197	1924	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1858	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1924	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T1,T2,T13
1	1	Covered	T56,T57,T33

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T13
1	0	Covered	T56,T57,T33
1	1	Covered	T1,T2,T13

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1030591197	1920	0	0
SrcPulseCheck_M	9420022	1920	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1920	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	1920	0	0
T1	11840	3	0	0
T2	15507	4	0	0
T3	625	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	443	0	0	0
T13	17092	6	0	0
T14	494	0	0	0
T15	16466	1	0	0
T16	515	0	0	0
T17	422	0	0	0
T18	672	0	0	0
T24	0	8	0	0
T34	0	5	0	0