Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T24,T25,T26
1	-	Covered	T1,T2,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	107202316	0	0
DstReqKnown_A	320280748	291836858	0	0
SrcAckBusyChk_A	2147483647	115428	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107202316	0	0
T1	7252150	19311	0	0
T2	18996425	61046	0	0
T3	8045700	0	0	0
T4	456000	125496	0	0
T5	2188626	32732	0	0
T6	197739	0	0	0
T7	107280	0	0	0
T8	0	35577	0	0
T9	0	100202	0	0
T12	1386950	0	0	0
T13	19229050	6128	0	0
T14	1802346	0	0	0
T15	10703420	6572	0	0
T16	6431698	0	0	0
T17	5485740	0	0	0
T18	8744400	13469	0	0
T24	125431	8398	0	0
T30	0	2371	0	0
T34	0	29645	0	0
T40	0	5825	0	0
T42	0	3055	0	0
T43	0	1551	0	0
T44	0	373	0	0
T45	0	5587	0	0
T46	0	1914	0	0
T47	0	3333	0	0
T48	0	3856	0	0
T49	0	2753	0	0
T50	784140	0	0	0
T51	50760	0	0	0
T52	608452	0	0	0
T53	433824	0	0	0
T54	604050	0	0	0
T55	217120	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	320280748	291836858	0	0
T1	402560	388620	0	0
T2	527238	512924	0	0
T6	17238	3638	0	0
T12	15062	1462	0	0
T13	581128	566134	0	0
T14	16796	3196	0	0
T15	559844	546244	0	0
T16	17510	3910	0	0
T17	14348	748	0	0
T18	22848	9248	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	115428	0	0
T1	7252150	27	0	0
T2	18996425	36	0	0
T3	8045700	0	0	0
T4	456000	72	0	0
T5	2188626	27	0	0
T6	197739	0	0	0
T7	107280	0	0	0
T8	0	81	0	0
T9	0	63	0	0
T12	1386950	0	0	0
T13	19229050	48	0	0
T14	1802346	0	0	0
T15	10703420	9	0	0
T16	6431698	0	0	0
T17	5485740	0	0	0
T18	8744400	8	0	0
T24	125431	74	0	0
T30	0	8	0	0
T34	0	40	0	0
T40	0	14	0	0
T42	0	7	0	0
T43	0	7	0	0
T44	0	1	0	0
T45	0	7	0	0
T46	0	1	0	0
T47	0	7	0	0
T48	0	8	0	0
T49	0	9	0	0
T50	784140	0	0	0
T51	50760	0	0	0
T52	608452	0	0	0
T53	433824	0	0	0
T54	604050	0	0	0
T55	217120	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	9862924	9854390	0	0
T2	25835138	25799846	0	0
T6	2241042	2237710	0	0
T12	1886252	1883192	0	0
T13	26151508	26085854	0	0
T14	2356914	2353548	0	0
T15	13996780	13996576	0	0
T16	8410682	8407996	0	0
T17	7173660	7170294	0	0
T18	10618200	10615310	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T4

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T56,T57,T31
1	-	Covered	T1,T2,T4

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1123693	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1239	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1123693	0	0
T1	290086	732	0	0
T2	759857	4889	0	0
T3	309450	0	0	0
T4	0	14764	0	0
T5	0	1291	0	0
T8	0	2604	0	0
T9	0	2932	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	396	0	0
T25	0	521	0	0
T34	0	3270	0	0
T58	0	4947	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1239	0	0
T1	290086	1	0	0
T2	759857	3	0	0
T3	309450	0	0	0
T4	0	8	0	0
T5	0	1	0	0
T8	0	6	0	0
T9	0	2	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	3	0	0
T25	0	2	0	0
T34	0	4	0	0
T58	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1889782	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	2055	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1889782	0	0
T1	290086	2085	0	0
T2	759857	6702	0	0
T3	309450	0	0	0
T4	0	15257	0	0
T5	0	3311	0	0
T8	0	3771	0	0
T12	55478	0	0	0
T13	769162	712	0	0
T14	69321	0	0	0
T15	411670	710	0	0
T16	247373	1915	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T50	0	975	0	0
T53	0	815	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2055	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	1	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T50	0	1	0	0
T53	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T24,T25,T26
0	0	1	Covered	T24,T25,T26
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T24,T25,T26
0	0	1	Covered	T24,T25,T26
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1259568	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1176	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1259568	0	0
T24	125431	997	0	0
T25	46039	858	0	0
T26	0	1225	0	0
T49	0	642	0	0
T58	733708	0	0	0
T59	0	748	0	0
T60	0	386	0	0
T61	0	2356	0	0
T62	0	3959	0	0
T63	0	1632	0	0
T64	0	236	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1176	0	0
T24	125431	8	0	0
T25	46039	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	733708	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T24,T25,T26
0	0	1	Covered	T24,T25,T26
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T24,T25,T26
0	0	1	Covered	T24,T25,T26
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1231627	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1166	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1231627	0	0
T24	125431	981	0	0
T25	46039	824	0	0
T26	0	1188	0	0
T49	0	621	0	0
T58	733708	0	0	0
T59	0	739	0	0
T60	0	384	0	0
T61	0	2349	0	0
T62	0	3937	0	0
T63	0	1622	0	0
T64	0	224	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1166	0	0
T24	125431	8	0	0
T25	46039	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	733708	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T24,T25,T26
0	0	1	Covered	T24,T25,T26
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T24,T25,T26
0	0	1	Covered	T24,T25,T26
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1231893	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1147	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1231893	0	0
T24	125431	965	0	0
T25	46039	801	0	0
T26	0	1164	0	0
T49	0	613	0	0
T58	733708	0	0	0
T59	0	731	0	0
T60	0	382	0	0
T61	0	2337	0	0
T62	0	3930	0	0
T63	0	1618	0	0
T64	0	214	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1147	0	0
T24	125431	8	0	0
T25	46039	3	0	0
T26	0	3	0	0
T49	0	2	0	0
T58	733708	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T14,T27,T24

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T14,T27,T24
1	1	Covered	T14,T27,T24

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T14,T27,T24

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T27,T24
1	1	Covered	T14,T27,T24

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T14,T27,T24
0	0	1	Covered	T14,T27,T24
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T14,T27,T24
0	0	1	Covered	T14,T27,T24
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	3053489	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	2987	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	3053489	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T14	69321	9686	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9562	0	0
T27	0	35002	0	0
T30	0	17876	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T69	0	4238	0	0
T72	0	5563	0	0
T73	0	15412	0	0
T74	0	33354	0	0
T75	0	32888	0	0
T76	0	18255	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2987	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T14	69321	20	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	80	0	0
T27	0	20	0	0
T30	0	60	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T69	0	20	0	0
T72	0	20	0	0
T73	0	20	0	0
T74	0	20	0	0
T75	0	20	0	0
T76	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T6,T14,T27

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T14,T27
1	1	Covered	T6,T14,T27

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T6,T14,T27

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T14,T27
1	1	Covered	T6,T14,T27

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T6,T14,T27
0	0	1	Covered	T6,T14,T27
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T6,T14,T27
0	0	1	Covered	T6,T14,T27
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	5567532	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	5921	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5567532	0	0
T1	290086	0	0	0
T2	759857	0	0	0
T6	65913	9006	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	526	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	19275	0	0
T27	0	1494	0	0
T28	0	27616	0	0
T29	0	29953	0	0
T66	0	31667	0	0
T67	0	17178	0	0
T69	0	185	0	0
T77	0	7283	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5921	0	0
T1	290086	0	0	0
T2	759857	0	0	0
T6	65913	20	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	1	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	164	0	0
T27	0	1	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T69	0	1	0	0
T77	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	6485810	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	6982	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6485810	0	0
T1	290086	2191	0	0
T2	759857	6852	0	0
T4	0	16371	0	0
T6	65913	9285	0	0
T12	55478	0	0	0
T13	769162	820	0	0
T14	69321	538	0	0
T15	411670	746	0	0
T16	247373	1917	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T50	0	977	0	0
T53	0	817	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6982	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T4	0	9	0	0
T6	65913	20	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	1	0	0
T15	411670	1	0	0
T16	247373	1	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T50	0	1	0	0
T53	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T6,T28,T29

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T28,T29

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T6,T28,T29

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T28,T29
1	1	Covered	T6,T28,T29

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T6,T28,T29
0	0	1	Covered	T6,T28,T29
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T6,T28,T29
0	0	1	Covered	T6,T28,T29
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	5507110	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	5839	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5507110	0	0
T1	290086	0	0	0
T2	759857	0	0	0
T6	65913	9132	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	19121	0	0
T28	0	27656	0	0
T29	0	30164	0	0
T66	0	31707	0	0
T67	0	17218	0	0
T70	0	36221	0	0
T77	0	7519	0	0
T78	0	35968	0	0
T79	0	16465	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	5839	0	0
T1	290086	0	0	0
T2	759857	0	0	0
T6	65913	20	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	0	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	160	0	0
T28	0	20	0	0
T29	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0
T70	0	20	0	0
T77	0	20	0	0
T78	0	20	0	0
T79	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T3,T7,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T3,T7,T10
1	1	Covered	T3,T7,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T3,T7,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T7,T10
1	1	Covered	T3,T7,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T3,T7,T10
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T3,T7,T10
0	0	1	Covered	T3,T7,T10
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1248060	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1146	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1248060	0	0
T3	309450	1467	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	164	0	0
T10	0	374	0	0
T11	0	1720	0	0
T24	0	411	0	0
T30	0	260	0	0
T38	0	954	0	0
T39	0	417	0	0
T40	0	352	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T80	0	1968	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1146	0	0
T3	309450	1	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T24	0	3	0	0
T30	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0
T55	217120	0	0	0
T80	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1921865	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	2099	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1921865	0	0
T1	290086	2079	0	0
T2	759857	6694	0	0
T3	309450	1464	0	0
T4	0	15157	0	0
T5	0	3272	0	0
T7	0	162	0	0
T8	0	3753	0	0
T9	0	10978	0	0
T12	55478	0	0	0
T13	769162	700	0	0
T14	69321	0	0	0
T15	411670	708	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2099	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	1	0	0
T4	0	9	0	0
T5	0	3	0	0
T7	0	1	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T18,T24,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T18,T24,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T18,T24,T30
0	0	1	Covered	T18,T24,T30
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T18,T24,T30
0	0	1	Covered	T18,T24,T30
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1449062	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1445	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1449062	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	0	0	0
T18	312300	8363	0	0
T24	0	624	0	0
T30	0	1509	0	0
T40	0	3410	0	0
T42	0	1769	0	0
T43	0	897	0	0
T45	0	3163	0	0
T47	0	1912	0	0
T48	0	2369	0	0
T49	0	1768	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1445	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	0	0	0
T18	312300	5	0	0
T24	0	5	0	0
T30	0	5	0	0
T40	0	8	0	0
T42	0	4	0	0
T43	0	4	0	0
T45	0	4	0	0
T47	0	4	0	0
T48	0	5	0	0
T49	0	6	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T18,T24,T30

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T18,T24,T30

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T24,T30
1	1	Covered	T18,T24,T30

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T18,T24,T30
0	0	1	Covered	T18,T24,T30
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T18,T24,T30
0	0	1	Covered	T18,T24,T30
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1357553	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1316	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1357553	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	0	0	0
T18	312300	5106	0	0
T24	0	376	0	0
T30	0	862	0	0
T40	0	2415	0	0
T42	0	1286	0	0
T43	0	654	0	0
T45	0	2424	0	0
T47	0	1421	0	0
T48	0	1487	0	0
T49	0	985	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1316	0	0
T3	309450	0	0	0
T4	114000	0	0	0
T5	729542	0	0	0
T7	35760	0	0	0
T18	312300	3	0	0
T24	0	3	0	0
T30	0	3	0	0
T40	0	6	0	0
T42	0	3	0	0
T43	0	3	0	0
T45	0	3	0	0
T47	0	3	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	196035	0	0	0
T51	12690	0	0	0
T52	152113	0	0	0
T53	144608	0	0	0
T54	201350	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	6527067	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	7158	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6527067	0	0
T1	290086	62738	0	0
T2	759857	129179	0	0
T3	309450	0	0	0
T5	0	86677	0	0
T8	0	34700	0	0
T9	0	132065	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	44425	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	21923	0	0
T46	0	87157	0	0
T81	0	326	0	0
T82	0	57210	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7158	0	0
T1	290086	73	0	0
T2	759857	77	0	0
T3	309450	0	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T81	0	1	0	0
T82	0	69	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	6381102	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	7062	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6381102	0	0
T1	290086	70752	0	0
T2	759857	131315	0	0
T3	309450	0	0	0
T5	0	116548	0	0
T8	0	32409	0	0
T9	0	166027	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	44215	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	21713	0	0
T46	0	86270	0	0
T82	0	48619	0	0
T83	0	20251	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7062	0	0
T1	290086	83	0	0
T2	759857	78	0	0
T3	309450	0	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	59	0	0
T83	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	6250974	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	6997	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6250974	0	0
T1	290086	51014	0	0
T2	759857	119287	0	0
T3	309450	0	0	0
T5	0	84389	0	0
T8	0	39560	0	0
T9	0	132441	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	44005	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	21503	0	0
T46	0	85233	0	0
T82	0	56722	0	0
T83	0	19524	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6997	0	0
T1	290086	60	0	0
T2	759857	71	0	0
T3	309450	0	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	69	0	0
T83	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	6196448	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	7001	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6196448	0	0
T1	290086	70149	0	0
T2	759857	90299	0	0
T3	309450	0	0	0
T5	0	112497	0	0
T8	0	32580	0	0
T9	0	142881	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	43795	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	21293	0	0
T46	0	84349	0	0
T82	0	64151	0	0
T83	0	18942	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7001	0	0
T1	290086	83	0	0
T2	759857	54	0	0
T3	309450	0	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	51	0	0
T46	0	51	0	0
T82	0	79	0	0
T83	0	51	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1377776	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1329	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1377776	0	0
T1	290086	2199	0	0
T2	759857	6854	0	0
T3	309450	0	0	0
T5	0	3914	0	0
T8	0	4113	0	0
T9	0	11258	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	748	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	373	0	0
T46	0	1914	0	0
T81	0	324	0	0
T82	0	959	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1329	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1384729	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1354	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1384729	0	0
T1	290086	2169	0	0
T2	759857	6814	0	0
T3	309450	0	0	0
T5	0	3770	0	0
T8	0	4023	0	0
T9	0	11188	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	738	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	363	0	0
T46	0	1859	0	0
T82	0	949	0	0
T83	0	309	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1354	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1378726	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1333	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1378726	0	0
T1	290086	2139	0	0
T2	759857	6774	0	0
T3	309450	0	0	0
T5	0	3602	0	0
T8	0	3933	0	0
T9	0	11118	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	728	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	353	0	0
T46	0	1824	0	0
T82	0	939	0	0
T83	0	274	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1333	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T15

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T15
0	0	1	Covered	T1,T2,T15
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1413390	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1370	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1413390	0	0
T1	290086	2109	0	0
T2	759857	6734	0	0
T3	309450	0	0	0
T5	0	3448	0	0
T8	0	3843	0	0
T9	0	11048	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	718	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	343	0	0
T46	0	1781	0	0
T82	0	929	0	0
T83	0	355	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1370	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	0	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	6964695	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	7735	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6964695	0	0
T1	290086	62866	0	0
T2	759857	129309	0	0
T3	309450	0	0	0
T4	0	16449	0	0
T5	0	87133	0	0
T8	0	34806	0	0
T9	0	132175	0	0
T12	55478	0	0	0
T13	769162	856	0	0
T14	69321	0	0	0
T15	411670	44521	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	1122	0	0
T34	0	4051	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7735	0	0
T1	290086	73	0	0
T2	759857	77	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	80	0	0
T9	0	76	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	6852133	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	7645	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6852133	0	0
T1	290086	70900	0	0
T2	759857	131447	0	0
T3	309450	0	0	0
T4	0	16353	0	0
T5	0	117241	0	0
T8	0	32505	0	0
T9	0	166177	0	0
T12	55478	0	0	0
T13	769162	844	0	0
T14	69321	0	0	0
T15	411670	44311	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	1004	0	0
T34	0	4011	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7645	0	0
T1	290086	83	0	0
T2	759857	78	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	76	0	0
T8	0	75	0	0
T9	0	96	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	6754287	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	7617	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6754287	0	0
T1	290086	51116	0	0
T2	759857	119405	0	0
T3	309450	0	0	0
T4	0	16248	0	0
T5	0	84841	0	0
T8	0	39690	0	0
T9	0	132553	0	0
T12	55478	0	0	0
T13	769162	832	0	0
T14	69321	0	0	0
T15	411670	44101	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	988	0	0
T34	0	3969	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7617	0	0
T1	290086	60	0	0
T2	759857	71	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	56	0	0
T8	0	92	0	0
T9	0	77	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	6679724	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	7612	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	6679724	0	0
T1	290086	70297	0	0
T2	759857	90383	0	0
T3	309450	0	0	0
T4	0	16136	0	0
T5	0	113229	0	0
T8	0	32680	0	0
T9	0	143005	0	0
T12	55478	0	0	0
T13	769162	820	0	0
T14	69321	0	0	0
T15	411670	43891	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	972	0	0
T34	0	3915	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	7612	0	0
T1	290086	83	0	0
T2	759857	54	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	75	0	0
T8	0	77	0	0
T9	0	83	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	51	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1909152	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	2020	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1909152	0	0
T1	290086	2187	0	0
T2	759857	6838	0	0
T3	309450	0	0	0
T4	0	16041	0	0
T5	0	3863	0	0
T8	0	4077	0	0
T9	0	11230	0	0
T12	55478	0	0	0
T13	769162	808	0	0
T14	69321	0	0	0
T15	411670	744	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	1056	0	0
T34	0	3875	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2020	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1794046	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1932	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1794046	0	0
T1	290086	2157	0	0
T2	759857	6798	0	0
T3	309450	0	0	0
T4	0	15934	0	0
T5	0	3692	0	0
T8	0	3987	0	0
T9	0	11160	0	0
T12	55478	0	0	0
T13	769162	796	0	0
T14	69321	0	0	0
T15	411670	734	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	940	0	0
T34	0	3819	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1932	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1799620	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1932	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1799620	0	0
T1	290086	2127	0	0
T2	759857	6758	0	0
T3	309450	0	0	0
T4	0	15833	0	0
T5	0	3540	0	0
T8	0	3897	0	0
T9	0	11090	0	0
T12	55478	0	0	0
T13	769162	784	0	0
T14	69321	0	0	0
T15	411670	724	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	924	0	0
T34	0	3782	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1932	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1787729	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1918	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1787729	0	0
T1	290086	2097	0	0
T2	759857	6718	0	0
T3	309450	0	0	0
T4	0	15728	0	0
T5	0	3379	0	0
T8	0	3807	0	0
T9	0	11020	0	0
T12	55478	0	0	0
T13	769162	772	0	0
T14	69321	0	0	0
T15	411670	714	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	908	0	0
T34	0	3733	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1918	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1896898	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	2022	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1896898	0	0
T1	290086	2181	0	0
T2	759857	6830	0	0
T3	309450	0	0	0
T4	0	15639	0	0
T5	0	3837	0	0
T8	0	4059	0	0
T9	0	11216	0	0
T12	55478	0	0	0
T13	769162	760	0	0
T14	69321	0	0	0
T15	411670	742	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	990	0	0
T34	0	3685	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	2022	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	9	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1810208	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1927	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1810208	0	0
T1	290086	2151	0	0
T2	759857	6790	0	0
T3	309450	0	0	0
T4	0	15531	0	0
T5	0	3663	0	0
T8	0	3969	0	0
T9	0	11146	0	0
T12	55478	0	0	0
T13	769162	748	0	0
T14	69321	0	0	0
T15	411670	732	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	876	0	0
T34	0	3625	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1927	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1751331	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1892	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1751331	0	0
T1	290086	2121	0	0
T2	759857	6750	0	0
T3	309450	0	0	0
T4	0	15438	0	0
T5	0	3502	0	0
T8	0	3879	0	0
T9	0	11076	0	0
T12	55478	0	0	0
T13	769162	736	0	0
T14	69321	0	0	0
T15	411670	722	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	860	0	0
T34	0	3586	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1892	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T1,T2,T13
0	0	1	Covered	T1,T2,T13
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1763127	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1920	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1763127	0	0
T1	290086	2091	0	0
T2	759857	6710	0	0
T3	309450	0	0	0
T4	0	15352	0	0
T5	0	3342	0	0
T8	0	3789	0	0
T9	0	11006	0	0
T12	55478	0	0	0
T13	769162	724	0	0
T14	69321	0	0	0
T15	411670	712	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	844	0	0
T34	0	3540	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1920	0	0
T1	290086	3	0	0
T2	759857	4	0	0
T3	309450	0	0	0
T4	0	9	0	0
T5	0	3	0	0
T8	0	9	0	0
T9	0	7	0	0
T12	55478	0	0	0
T13	769162	6	0	0
T14	69321	0	0	0
T15	411670	1	0	0
T16	247373	0	0	0
T17	210990	0	0	0
T18	312300	0	0	0
T24	0	8	0	0
T34	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T24,T25,T26
1	-	Covered	T24,T25,T26

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T24,T25,T26
0	0	1	Covered	T24,T25,T26
0	0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T2
0	1	-	Covered	T24,T25,T26
0	0	1	Covered	T24,T25,T26
0	0	0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1030591197	1202110	0	0
DstReqKnown_A	9420022	8583437	0	0
SrcAckBusyChk_A	1030591197	1134	0	0
SrcBusyKnown_A	1030591197	1028984832	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1202110	0	0
T24	125431	714	0	0
T25	46039	1076	0	0
T26	0	838	0	0
T49	0	636	0	0
T58	733708	0	0	0
T61	0	2333	0	0
T62	0	7920	0	0
T64	0	458	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0
T84	0	3449	0	0
T85	0	790	0	0
T86	0	740	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9420022	8583437	0	0
T1	11840	11430	0	0
T2	15507	15086	0	0
T6	507	107	0	0
T12	443	43	0	0
T13	17092	16651	0	0
T14	494	94	0	0
T15	16466	16066	0	0
T16	515	115	0	0
T17	422	22	0	0
T18	672	272	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1134	0	0
T24	125431	6	0	0
T25	46039	4	0	0
T26	0	2	0	0
T49	0	2	0	0
T58	733708	0	0	0
T61	0	2	0	0
T62	0	4	0	0
T64	0	4	0	0
T65	53904	0	0	0
T66	240308	0	0	0
T67	327297	0	0	0
T68	20688	0	0	0
T69	32170	0	0	0
T70	251101	0	0	0
T71	194914	0	0	0
T84	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1030591197	1028984832	0	0
T1	290086	289835	0	0
T2	759857	758819	0	0
T6	65913	65815	0	0
T12	55478	55388	0	0
T13	769162	767231	0	0
T14	69321	69222	0	0
T15	411670	411664	0	0
T16	247373	247294	0	0
T17	210990	210891	0	0
T18	312300	312215	0	0