Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T6,T17,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T6,T17,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T6,T17,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T17,T31
1	0	Covered	T5,T6,T1
1	1	Covered	T6,T17,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T17,T31
0	1	Covered	T6,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T17,T31
0	1	Covered	T6,T17,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T17,T31
1	-	Covered	T6,T17,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T17,T31
DetectSt	168	Covered	T6,T17,T31
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T6,T17,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T17,T31
DebounceSt->IdleSt	163	Covered	T47,T114,T60
DetectSt->IdleSt	186	Covered	T6,T82,T83
DetectSt->StableSt	191	Covered	T6,T17,T31
IdleSt->DebounceSt	148	Covered	T6,T17,T31
StableSt->IdleSt	206	Covered	T6,T17,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T17,T31
0	1	Covered	T6,T17,T31
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T17,T31
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T17,T31
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T17,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T60,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T17,T31
DetectSt	-	-	-	-	1	-	-	Covered	T6,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T6,T17,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T17,T31
StableSt	-	-	-	-	-	-	0	Covered	T6,T17,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	318	0	0
CntIncr_A	6427592	119295	0	0
CntNoWrap_A	6427592	5751275	0	0
DetectStDropOut_A	6427592	5	0	0
DetectedOut_A	6427592	966	0	0
DetectedPulseOut_A	6427592	141	0	0
DisabledIdleSt_A	6427592	5624836	0	0
DisabledNoDetection_A	6427592	5627212	0	0
EnterDebounceSt_A	6427592	176	0	0
EnterDetectSt_A	6427592	146	0	0
EnterStableSt_A	6427592	141	0	0
PulseIsPulse_A	6427592	141	0	0
StayInStableSt	6427592	825	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6427592	7010	0	0
gen_low_level_sva.LowLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	141	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	318	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	4	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	2	0	0
T18	4773	0	0	0
T31	0	2	0	0
T44	0	6	0	0
T45	0	2	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	119295	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	160	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	44	0	0
T18	4773	0	0	0
T31	0	72	0	0
T44	0	188	0	0
T45	0	89	0	0
T46	0	97	0	0
T47	0	88	0	0
T48	0	99	0	0
T49	0	130	0	0
T50	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751275	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	330	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	291	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	1	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T91	0	1	0	0
T102	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	966	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	5	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	8	0	0
T18	4773	0	0	0
T31	0	7	0	0
T44	0	23	0	0
T45	0	7	0	0
T46	0	9	0	0
T47	0	12	0	0
T48	0	11	0	0
T49	0	23	0	0
T50	0	6	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	141	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	1	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	1	0	0
T18	4773	0	0	0
T31	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5624836	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	108	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	207	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5627212	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	108	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	208	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	176	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	2	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	1	0	0
T18	4773	0	0	0
T31	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	146	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	2	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	1	0	0
T18	4773	0	0	0
T31	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	141	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	1	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	1	0	0
T18	4773	0	0	0
T31	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	141	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	1	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	1	0	0
T18	4773	0	0	0
T31	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	825	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	4	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	7	0	0
T18	4773	0	0	0
T31	0	6	0	0
T44	0	20	0	0
T45	0	6	0	0
T46	0	7	0	0
T47	0	11	0	0
T48	0	10	0	0
T49	0	21	0	0
T50	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	7010	0	0
T1	17586	22	0	0
T2	33828	28	0	0
T3	927	1	0	0
T4	0	10	0	0
T5	426	1	0	0
T6	735	3	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	3	0	0
T18	0	27	0	0
T19	0	3	0	0
T32	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	141	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	1	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	1	0	0
T18	4773	0	0	0
T31	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T25,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T26,T27,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T5,T6,T1
1	1	Covered	T25,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T40,T56
0	1	Covered	T26,T27,T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T40,T56
0	1	Unreachable
1	0	Covered	T26,T40,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T27
DetectSt	168	Covered	T26,T27,T40
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T26,T40,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T27,T40
DebounceSt->IdleSt	163	Covered	T25,T27,T40
DetectSt->IdleSt	186	Covered	T26,T27,T40
DetectSt->StableSt	191	Covered	T26,T40,T56
IdleSt->DebounceSt	148	Covered	T25,T26,T27
StableSt->IdleSt	206	Covered	T26,T40,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T26,T27
0	1	Covered	T25,T26,T27
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T40
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T27,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T27,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T26,T27,T40
DetectSt	-	-	-	-	0	1	-	Covered	T26,T40,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T26,T40,T56
StableSt	-	-	-	-	-	-	0	Covered	T26,T40,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	199	0	0
CntIncr_A	6427592	50365	0	0
CntNoWrap_A	6427592	5751394	0	0
DetectStDropOut_A	6427592	25	0	0
DetectedOut_A	6427592	143289	0	0
DetectedPulseOut_A	6427592	48	0	0
DisabledIdleSt_A	6427592	5237599	0	0
DisabledNoDetection_A	6427592	5240035	0	0
EnterDebounceSt_A	6427592	126	0	0
EnterDetectSt_A	6427592	73	0	0
EnterStableSt_A	6427592	48	0	0
PulseIsPulse_A	6427592	48	0	0
StayInStableSt	6427592	143241	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6427592	7010	0	0
gen_low_level_sva.LowLevelEvent_A	6427592	5754030	0	0
gen_sticky_sva.StableStDropOut_A	6427592	81004	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	199	0	0
T25	1848	3	0	0
T26	3619	8	0	0
T27	8792	4	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	9	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	50365	0	0
T25	1848	114	0	0
T26	3619	204	0	0
T27	8792	102	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	225	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	54	0	0
T57	0	14	0	0
T58	0	231	0	0
T59	0	10	0	0
T75	0	64	0	0
T76	0	35	0	0
T77	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751394	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	25	0	0
T26	3619	3	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	2	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T77	406	0	0	0
T113	522	0	0	0
T115	0	1	0	0
T116	0	2	0	0
T117	0	2	0	0
T118	0	4	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	143289	0	0
T26	3619	52	0	0
T27	8792	0	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	424	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	75	0	0
T57	0	27	0	0
T59	0	27	0	0
T76	0	128	0	0
T77	406	0	0	0
T109	0	145	0	0
T110	0	652	0	0
T111	0	1	0	0
T112	0	705	0	0
T113	522	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	48	0	0
T26	3619	1	0	0
T27	8792	0	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	2	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	522	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5237599	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5240035	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	126	0	0
T25	1848	3	0	0
T26	3619	4	0	0
T27	8792	3	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	5	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	3	0	0
T59	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	73	0	0
T26	3619	4	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	4	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	1	0	0
T113	522	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	48	0	0
T26	3619	1	0	0
T27	8792	0	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	2	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	522	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	48	0	0
T26	3619	1	0	0
T27	8792	0	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	2	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	522	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	143241	0	0
T26	3619	51	0	0
T27	8792	0	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	422	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	74	0	0
T57	0	26	0	0
T59	0	26	0	0
T76	0	127	0	0
T77	406	0	0	0
T109	0	144	0	0
T110	0	649	0	0
T112	0	703	0	0
T113	522	0	0	0
T122	0	278	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	7010	0	0
T1	17586	22	0	0
T2	33828	28	0	0
T3	927	1	0	0
T4	0	10	0	0
T5	426	1	0	0
T6	735	3	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	3	0	0
T18	0	27	0	0
T19	0	3	0	0
T32	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	81004	0	0
T26	3619	161	0	0
T27	8792	0	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	175	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	180	0	0
T57	0	247	0	0
T59	0	506	0	0
T76	0	135	0	0
T77	406	0	0	0
T109	0	123	0	0
T110	0	661	0	0
T111	0	29	0	0
T112	0	577	0	0
T113	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T25,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T5,T1,T3
1	1	Covered	T25,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T40
0	1	Covered	T25,T40,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T40
0	1	Unreachable
1	0	Covered	T26,T27,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T27
DetectSt	168	Covered	T25,T26,T27
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T26,T27,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T26,T27
DebounceSt->IdleSt	163	Covered	T25,T27,T40
DetectSt->IdleSt	186	Covered	T25,T40,T88
DetectSt->StableSt	191	Covered	T26,T27,T40
IdleSt->DebounceSt	148	Covered	T25,T26,T27
StableSt->IdleSt	206	Covered	T26,T27,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T26,T27
0	1	Covered	T25,T26,T27
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T27
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T27,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T25,T40,T88
DetectSt	-	-	-	-	0	1	-	Covered	T26,T27,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T26,T27,T40
StableSt	-	-	-	-	-	-	0	Covered	T26,T27,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	202	0	0
CntIncr_A	6427592	180255	0	0
CntNoWrap_A	6427592	5751391	0	0
DetectStDropOut_A	6427592	18	0	0
DetectedOut_A	6427592	51218	0	0
DetectedPulseOut_A	6427592	49	0	0
DisabledIdleSt_A	6427592	5237599	0	0
DisabledNoDetection_A	6427592	5240035	0	0
EnterDebounceSt_A	6427592	135	0	0
EnterDetectSt_A	6427592	67	0	0
EnterStableSt_A	6427592	49	0	0
PulseIsPulse_A	6427592	49	0	0
StayInStableSt	6427592	51169	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_sticky_sva.StableStDropOut_A	6427592	19816	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	202	0	0
T25	1848	4	0	0
T26	3619	2	0	0
T27	8792	4	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	9	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	180255	0	0
T25	1848	111	0	0
T26	3619	76	0	0
T27	8792	106	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	243	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	158	0	0
T57	0	64	0	0
T58	0	22	0	0
T59	0	91	0	0
T75	0	65	0	0
T76	0	58	0	0
T77	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751391	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	18	0	0
T25	1848	1	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	2	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T77	406	0	0	0
T87	0	2	0	0
T88	0	3	0	0
T116	0	1	0	0
T117	0	2	0	0
T118	0	1	0	0
T121	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	51218	0	0
T26	3619	467	0	0
T27	8792	42	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	273	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T57	0	182	0	0
T58	0	69	0	0
T59	0	403	0	0
T76	0	177	0	0
T77	406	0	0	0
T109	0	95	0	0
T110	0	749	0	0
T111	0	46	0	0
T113	522	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	49	0	0
T26	3619	1	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	2	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	1	0	0
T113	522	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5237599	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5240035	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	135	0	0
T25	1848	3	0	0
T26	3619	1	0	0
T27	8792	3	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	5	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	67	0	0
T25	1848	1	0	0
T26	3619	1	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	4	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	49	0	0
T26	3619	1	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	2	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	1	0	0
T113	522	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	49	0	0
T26	3619	1	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	2	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	3	0	0
T111	0	1	0	0
T113	522	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	51169	0	0
T26	3619	466	0	0
T27	8792	41	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	271	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T57	0	181	0	0
T58	0	68	0	0
T59	0	402	0	0
T76	0	176	0	0
T77	406	0	0	0
T109	0	94	0	0
T110	0	746	0	0
T111	0	45	0	0
T113	522	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	19816	0	0
T26	3619	112	0	0
T27	8792	29	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	378	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T57	0	41	0	0
T58	0	258	0	0
T59	0	66	0	0
T76	0	49	0	0
T77	406	0	0	0
T109	0	164	0	0
T110	0	547	0	0
T111	0	26	0	0
T113	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T25,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T27,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T5,T1,T2
1	1	Covered	T25,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T27,T40
0	1	Covered	T58,T86,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T27,T40
0	1	Unreachable
1	0	Covered	T25,T27,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T27
DetectSt	168	Covered	T25,T27,T40
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T25,T27,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T27,T40
DebounceSt->IdleSt	163	Covered	T26,T27,T75
DetectSt->IdleSt	186	Covered	T58,T86,T87
DetectSt->StableSt	191	Covered	T25,T27,T40
IdleSt->DebounceSt	148	Covered	T25,T26,T27
StableSt->IdleSt	206	Covered	T25,T27,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T26,T27
0	1	Covered	T25,T26,T27
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T27,T40
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T27,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T27,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T58,T86,T87
DetectSt	-	-	-	-	0	1	-	Covered	T25,T27,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T27,T40
StableSt	-	-	-	-	-	-	0	Covered	T25,T27,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	167	0	0
CntIncr_A	6427592	70436	0	0
CntNoWrap_A	6427592	5751426	0	0
DetectStDropOut_A	6427592	5	0	0
DetectedOut_A	6427592	147027	0	0
DetectedPulseOut_A	6427592	58	0	0
DisabledIdleSt_A	6427592	5237599	0	0
DisabledNoDetection_A	6427592	5240035	0	0
EnterDebounceSt_A	6427592	104	0	0
EnterDetectSt_A	6427592	63	0	0
EnterStableSt_A	6427592	58	0	0
PulseIsPulse_A	6427592	58	0	0
StayInStableSt	6427592	146969	0	0
gen_high_event_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_sticky_sva.StableStDropOut_A	6427592	83681	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	167	0	0
T25	1848	2	0	0
T26	3619	5	0	0
T27	8792	3	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	6	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	4	0	0
T59	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	70436	0	0
T25	1848	66	0	0
T26	3619	70	0	0
T27	8792	101	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	120	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	15	0	0
T57	0	77	0	0
T58	0	22	0	0
T59	0	15	0	0
T75	0	64	0	0
T76	0	45	0	0
T77	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751426	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5	0	0
T58	1296	1	0	0
T59	2681	0	0	0
T86	0	2	0	0
T87	0	1	0	0
T94	17044	0	0	0
T125	0	1	0	0
T126	980	0	0	0
T127	488	0	0	0
T128	11699	0	0	0
T129	433	0	0	0
T130	491	0	0	0
T131	12016	0	0	0
T132	12051	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	147027	0	0
T25	1848	323	0	0
T26	3619	0	0	0
T27	8792	22	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	497	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	44	0	0
T57	0	177	0	0
T58	0	14	0	0
T59	0	44	0	0
T76	0	152	0	0
T77	406	0	0	0
T109	0	179	0	0
T110	0	327	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	58	0	0
T25	1848	1	0	0
T26	3619	0	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	3	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5237599	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5240035	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	104	0	0
T25	1848	1	0	0
T26	3619	5	0	0
T27	8792	2	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	3	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	63	0	0
T25	1848	1	0	0
T26	3619	0	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	3	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	2	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	58	0	0
T25	1848	1	0	0
T26	3619	0	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	3	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	58	0	0
T25	1848	1	0	0
T26	3619	0	0	0
T27	8792	1	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	3	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T76	0	1	0	0
T77	406	0	0	0
T109	0	1	0	0
T110	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	146969	0	0
T25	1848	322	0	0
T26	3619	0	0	0
T27	8792	21	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	494	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	43	0	0
T57	0	176	0	0
T58	0	13	0	0
T59	0	43	0	0
T76	0	151	0	0
T77	406	0	0	0
T109	0	178	0	0
T110	0	325	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	83681	0	0
T25	1848	149	0	0
T26	3619	0	0	0
T27	8792	92	0	0
T36	674	0	0	0
T38	55140	0	0	0
T40	0	397	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T56	0	252	0	0
T57	0	52	0	0
T58	0	218	0	0
T59	0	505	0	0
T76	0	103	0	0
T77	406	0	0	0
T109	0	78	0	0
T110	0	565	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T3,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T35
1	0	Covered	T5,T6,T1
1	1	Covered	T3,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T35,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T35,T36
0	1	Covered	T3,T133,T134
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T35,T36
1	-	Covered	T3,T133,T134

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T35,T36
DetectSt	168	Covered	T3,T35,T36
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T35,T36
DebounceSt->IdleSt	163	Covered	T60,T75,T79
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T35,T36
IdleSt->DebounceSt	148	Covered	T3,T35,T36
StableSt->IdleSt	206	Covered	T3,T35,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T35,T36
0	1	Covered	T3,T35,T36
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T35,T36
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T35,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T35,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T133,T134
StableSt	-	-	-	-	-	-	0	Covered	T3,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	84	0	0
CntIncr_A	6427592	61332	0	0
CntNoWrap_A	6427592	5751509	0	0
DetectStDropOut_A	6427592	0	0	0
DetectedOut_A	6427592	3421	0	0
DetectedPulseOut_A	6427592	41	0	0
DisabledIdleSt_A	6427592	5298363	0	0
DisabledNoDetection_A	6427592	5300754	0	0
EnterDebounceSt_A	6427592	44	0	0
EnterDetectSt_A	6427592	41	0	0
EnterStableSt_A	6427592	41	0	0
PulseIsPulse_A	6427592	41	0	0
StayInStableSt	6427592	3357	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	84	0	0
T3	927	2	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T51	414	0	0	0
T75	0	1	0	0
T112	0	2	0	0
T114	0	2	0	0
T133	0	4	0	0
T135	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	61332	0	0
T3	927	56	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	57086	0	0
T36	0	30	0	0
T40	0	77	0	0
T41	0	16	0	0
T51	414	0	0	0
T60	0	1839	0	0
T75	0	41	0	0
T114	0	14	0	0
T133	0	76	0	0
T135	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751509	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	524	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3421	0	0
T3	927	209	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	39	0	0
T36	0	38	0	0
T40	0	42	0	0
T41	0	48	0	0
T51	414	0	0	0
T112	0	42	0	0
T114	0	115	0	0
T133	0	90	0	0
T135	0	331	0	0
T136	0	285	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	41	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	414	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	2	0	0
T135	0	1	0	0
T136	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5298363	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	3	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5300754	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	3	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	44	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	414	0	0	0
T60	0	1	0	0
T75	0	1	0	0
T114	0	1	0	0
T133	0	2	0	0
T135	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	41	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	414	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	2	0	0
T135	0	1	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	41	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	414	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	2	0	0
T135	0	1	0	0
T136	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	41	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T51	414	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	2	0	0
T135	0	1	0	0
T136	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3357	0	0
T3	927	208	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	37	0	0
T36	0	36	0	0
T40	0	40	0	0
T41	0	46	0	0
T51	414	0	0	0
T112	0	40	0	0
T114	0	113	0	0
T133	0	87	0	0
T135	0	329	0	0
T136	0	283	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	18	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T51	414	0	0	0
T133	0	1	0	0
T134	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	3	0	0
T142	0	1	0	0
T143	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T9,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T3,T9,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T9,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T35
1	0	Covered	T5,T1,T2
1	1	Covered	T3,T9,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T35
0	1	Covered	T144,T145
1	0	Covered	T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T35
0	1	Covered	T3,T35,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T35
1	-	Covered	T3,T35,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T35
DetectSt	168	Covered	T3,T9,T35
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T9,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T35
DebounceSt->IdleSt	163	Covered	T26,T133,T110
DetectSt->IdleSt	186	Covered	T75,T144,T145
DetectSt->StableSt	191	Covered	T3,T9,T35
IdleSt->DebounceSt	148	Covered	T3,T9,T35
StableSt->IdleSt	206	Covered	T3,T35,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T35
0	1	Covered	T3,T9,T35
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T35
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T26,T133,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T35
DetectSt	-	-	-	-	1	-	-	Covered	T75,T144,T145
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T35,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	151	0	0
CntIncr_A	6427592	111815	0	0
CntNoWrap_A	6427592	5751442	0	0
DetectStDropOut_A	6427592	2	0	0
DetectedOut_A	6427592	262756	0	0
DetectedPulseOut_A	6427592	67	0	0
DisabledIdleSt_A	6427592	5148597	0	0
DisabledNoDetection_A	6427592	5150976	0	0
EnterDebounceSt_A	6427592	81	0	0
EnterDetectSt_A	6427592	70	0	0
EnterStableSt_A	6427592	67	0	0
PulseIsPulse_A	6427592	67	0	0
StayInStableSt	6427592	262664	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6427592	2637	0	0
gen_low_level_sva.LowLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	151	0	0
T3	927	4	0	0
T4	14720	0	0	0
T9	0	2	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T32	12832	0	0	0
T35	0	2	0	0
T37	0	2	0	0
T40	0	2	0	0
T51	414	0	0	0
T60	0	2	0	0
T114	0	2	0	0
T126	0	2	0	0
T146	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	111815	0	0
T3	927	112	0	0
T4	14720	0	0	0
T9	0	89	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	27	0	0
T32	12832	0	0	0
T35	0	57086	0	0
T37	0	14	0	0
T40	0	77	0	0
T51	414	0	0	0
T60	0	11803	0	0
T114	0	14	0	0
T126	0	96	0	0
T146	0	38441	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751442	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	522	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2	0	0
T121	1566	0	0	0
T144	641	1	0	0
T145	0	1	0	0
T147	1399	0	0	0
T148	422	0	0	0
T149	522	0	0	0
T150	423	0	0	0
T151	14202	0	0	0
T152	571	0	0	0
T153	630	0	0	0
T154	112607	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	262756	0	0
T3	927	139	0	0
T4	14720	0	0	0
T9	0	51	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	179133	0	0
T37	0	13	0	0
T40	0	68	0	0
T51	414	0	0	0
T60	0	16562	0	0
T114	0	12	0	0
T126	0	347	0	0
T133	0	29	0	0
T146	0	62164	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	67	0	0
T3	927	2	0	0
T4	14720	0	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T60	0	1	0	0
T114	0	1	0	0
T126	0	1	0	0
T133	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5148597	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	3	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5150976	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	3	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	81	0	0
T3	927	2	0	0
T4	14720	0	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T32	12832	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T60	0	1	0	0
T114	0	1	0	0
T126	0	1	0	0
T146	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	70	0	0
T3	927	2	0	0
T4	14720	0	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T60	0	1	0	0
T75	0	1	0	0
T114	0	1	0	0
T126	0	1	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	67	0	0
T3	927	2	0	0
T4	14720	0	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T60	0	1	0	0
T114	0	1	0	0
T126	0	1	0	0
T133	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	67	0	0
T3	927	2	0	0
T4	14720	0	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T60	0	1	0	0
T114	0	1	0	0
T126	0	1	0	0
T133	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	262664	0	0
T3	927	136	0	0
T4	14720	0	0	0
T9	0	49	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	179132	0	0
T37	0	12	0	0
T40	0	67	0	0
T51	414	0	0	0
T60	0	16561	0	0
T114	0	11	0	0
T126	0	345	0	0
T133	0	28	0	0
T146	0	62163	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2637	0	0
T1	17586	15	0	0
T2	33828	0	0	0
T3	927	2	0	0
T5	426	4	0	0
T6	735	0	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T19	0	5	0	0
T28	0	4	0	0
T29	0	6	0	0
T30	0	5	0	0
T43	0	5	0	0
T51	0	2	0	0
T66	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	42	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T35	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T60	0	1	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	1	0	0
T136	0	1	0	0
T146	0	1	0	0