Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	89.17	93.48	85.71		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	95.41	97.83	90.48		100.00	95.00	93.75
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
95.41	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
89.17	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T27,T78
1	0	Covered	T75,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T80,T75,T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T4
1	-	Covered	T1,T2,T4

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
95.41	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T6,T3,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T6,T3,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T6,T3,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T3,T17
1	0	Covered	T5,T6,T1
1	1	Covered	T6,T3,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T17
0	1	Covered	T6,T82,T83
1	0	Covered	T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T3,T17
0	1	Covered	T6,T3,T17
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T3,T17
1	-	Covered	T6,T3,T17

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T18,T32
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T32
1	0	Covered	T2,T32,T12
1	1	Covered	T2,T18,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T32
0	1	Covered	T32,T55,T71
1	0	Covered	T32,T12,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T32
0	1	Covered	T2,T18,T32
1	0	Covered	T75,T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T18,T32
1	-	Covered	T2,T18,T32

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T27,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T5,T1,T2
1	1	Covered	T25,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T27,T40
0	1	Covered	T58,T86,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T27,T40
0	1	Unreachable
1	0	Covered	T25,T27,T40

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
89.17	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T5,T6,T1
1	1	Covered	T3,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T8,T36,T27
1	0	Covered	T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T8,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T9
1	-	Covered	T3,T8,T35

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T3
1	1	Covered	T5,T1,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T5,T1,T3
1	1	Covered	T25,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T40
0	1	Covered	T25,T40,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T40
0	1	Unreachable
1	0	Covered	T26,T27,T40

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T25,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T26,T27,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T27
1	0	Covered	T5,T6,T1
1	1	Covered	T25,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T40,T56
0	1	Covered	T26,T27,T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T40,T56
0	1	Unreachable
1	0	Covered	T26,T40,T56

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T3,T17
DetectSt	168	Covered	T6,T3,T17
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T6,T3,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T3,T17
DebounceSt->IdleSt	163	Covered	T47,T26,T36
DetectSt->IdleSt	186	Covered	T6,T26,T27
DetectSt->StableSt	191	Covered	T6,T3,T17
IdleSt->DebounceSt	148	Covered	T6,T3,T17
StableSt->IdleSt	206	Covered	T6,T3,T17

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
95.41	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
89.17	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T3,T17
0	1	Covered	T6,T3,T17
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T3,T17
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T3,T17
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T3,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T26,T36
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T3,T17
DetectSt	-	-	-	-	1	-	-	Covered	T6,T26,T27
DetectSt	-	-	-	-	0	1	-	Covered	T6,T3,T17
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T4
StableSt	-	-	-	-	-	-	1	Covered	T6,T3,T17
StableSt	-	-	-	-	-	-	0	Covered	T6,T3,T17
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T18,T32
0	1	Covered	T2,T18,T32
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T18,T32
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T18,T32
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T18,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T26,T27
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T18,T32
DetectSt	-	-	-	-	1	-	-	Covered	T32,T12,T55
DetectSt	-	-	-	-	0	1	-	Covered	T2,T18,T32
DetectSt	-	-	-	-	0	0	-	Covered	T2,T18,T32
StableSt	-	-	-	-	-	-	1	Covered	T2,T18,T32
StableSt	-	-	-	-	-	-	0	Covered	T2,T18,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	167117392	18375	0	0
CntIncr_A	167117392	2094906	0	0
CntNoWrap_A	167117392	149523043	0	0
DetectStDropOut_A	167117392	1640	0	0
DetectedOut_A	167117392	1948929	0	0
DetectedPulseOut_A	167117392	6287	0	0
DisabledIdleSt_A	167117392	139224672	0	0
DisabledNoDetection_A	167117392	139283681	0	0
EnterDebounceSt_A	167117392	9486	0	0
EnterDetectSt_A	167117392	8912	0	0
EnterStableSt_A	167117392	6287	0	0
PulseIsPulse_A	167117392	6287	0	0
StayInStableSt	167117392	1941813	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	57848328	52415	0	0
gen_high_event_sva.HighLevelEvent_A	32137960	28770150	0	0
gen_high_level_sva.HighLevelEvent_A	109269064	97818510	0	0
gen_low_level_sva.LowLevelEvent_A	57848328	51786270	0	0
gen_not_sticky_sva.StableStDropOut_A	147834616	5252	0	0
gen_sticky_sva.StableStDropOut_A	19282776	184501	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	18375	0	0
T1	87930	8	0	0
T2	304452	80	0	0
T3	10197	0	0	0
T4	88320	9	0	0
T6	735	4	0	0
T7	0	6	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	8	0	0
T11	0	13	0	0
T13	2020	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	2	0	0
T18	52503	13	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	2	0	0
T32	25664	42	0	0
T36	674	0	0	0
T43	0	1	0	0
T44	0	6	0	0
T45	0	2	0	0
T46	0	4	0	0
T47	0	3	0	0
T48	86911	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	2484	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	2094906	0	0
T1	87930	337	0	0
T2	304452	2880	0	0
T3	10197	0	0	0
T4	88320	515	0	0
T6	735	160	0	0
T7	0	315	0	0
T8	0	146	0	0
T9	0	25	0	0
T10	0	676	0	0
T11	0	618	0	0
T13	2020	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	44	0	0
T18	52503	587	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	72	0	0
T32	25664	1155	0	0
T36	674	0	0	0
T43	0	20	0	0
T44	0	188	0	0
T45	0	89	0	0
T46	0	97	0	0
T47	0	88	0	0
T48	86911	99	0	0
T49	0	130	0	0
T50	0	66	0	0
T51	2484	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	149523043	0	0
T1	457236	299762	0	0
T2	879528	866422	0	0
T3	24102	13660	0	0
T5	11076	650	0	0
T6	19110	8680	0	0
T13	10504	78	0	0
T14	13416	2990	0	0
T15	10530	104	0	0
T16	10530	104	0	0
T17	18044	7616	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	1640	0	0
T1	17586	0	0	0
T2	33828	0	0	0
T3	927	0	0	0
T6	735	1	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T56	745	0	0	0
T57	746	0	0	0
T71	5318	13	0	0
T73	0	14	0	0
T78	17668	1	0	0
T82	764	1	0	0
T83	0	1	0	0
T89	0	2	0	0
T90	25841	2	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	23	0	0
T94	0	7	0	0
T95	0	12	0	0
T96	0	2	0	0
T97	0	6	0	0
T98	0	6	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	12	0	0
T102	0	1	0	0
T103	0	9	0	0
T104	1326	0	0	0
T105	422	0	0	0
T106	2820	0	0	0
T107	407	0	0	0
T108	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	1948929	0	0
T1	70344	199	0	0
T2	304452	3463	0	0
T3	10197	0	0	0
T4	103040	189	0	0
T6	735	5	0	0
T7	0	28	0	0
T8	0	90	0	0
T9	0	3	0	0
T10	0	45	0	0
T11	0	498	0	0
T12	0	2565	0	0
T13	1616	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	8	0	0
T18	52503	31	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	7	0	0
T32	25664	1641	0	0
T36	674	0	0	0
T44	0	23	0	0
T45	0	7	0	0
T46	0	9	0	0
T47	0	12	0	0
T48	86911	11	0	0
T49	0	23	0	0
T50	0	6	0	0
T51	2898	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	6287	0	0
T1	70344	4	0	0
T2	304452	40	0	0
T3	10197	0	0	0
T4	103040	4	0	0
T6	735	1	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	37	0	0
T13	1616	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	1	0	0
T18	52503	3	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	1	0	0
T32	25664	21	0	0
T36	674	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	86911	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	2898	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	139224672	0	0
T1	457236	293418	0	0
T2	879528	835669	0	0
T3	24102	10538	0	0
T5	11076	650	0	0
T6	19110	8458	0	0
T13	10504	78	0	0
T14	13416	2990	0	0
T15	10530	104	0	0
T16	10530	104	0	0
T17	18044	7532	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	139283681	0	0
T1	457236	293899	0	0
T2	879528	835953	0	0
T3	24102	10558	0	0
T5	11076	676	0	0
T6	19110	8483	0	0
T13	10504	104	0	0
T14	13416	3016	0	0
T15	10530	130	0	0
T16	10530	130	0	0
T17	18044	7558	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	9486	0	0
T1	87930	4	0	0
T2	304452	40	0	0
T3	10197	0	0	0
T4	88320	5	0	0
T6	735	2	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	7	0	0
T13	2020	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	1	0	0
T18	52503	10	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	1	0	0
T32	25664	21	0	0
T36	674	0	0	0
T43	0	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	86911	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	2484	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	8912	0	0
T1	87930	4	0	0
T2	304452	40	0	0
T3	10197	0	0	0
T4	88320	4	0	0
T6	735	2	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	37	0	0
T13	2020	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	1	0	0
T18	52503	3	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	1	0	0
T32	25664	21	0	0
T36	674	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	86911	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	2484	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	6287	0	0
T1	70344	4	0	0
T2	304452	40	0	0
T3	10197	0	0	0
T4	103040	4	0	0
T6	735	1	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	37	0	0
T13	1616	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	1	0	0
T18	52503	3	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	1	0	0
T32	25664	21	0	0
T36	674	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	86911	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	2898	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	6287	0	0
T1	70344	4	0	0
T2	304452	40	0	0
T3	10197	0	0	0
T4	103040	4	0	0
T6	735	1	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	37	0	0
T13	1616	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	1	0	0
T18	52503	3	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	1	0	0
T32	25664	21	0	0
T36	674	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	86911	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	2898	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	167117392	1941813	0	0
T1	70344	195	0	0
T2	304452	3412	0	0
T3	10197	0	0	0
T4	103040	185	0	0
T6	735	4	0	0
T7	0	25	0	0
T8	0	89	0	0
T9	0	2	0	0
T10	0	41	0	0
T11	0	492	0	0
T12	0	2514	0	0
T13	1616	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	7	0	0
T18	52503	28	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	6	0	0
T32	25664	1614	0	0
T36	674	0	0	0
T44	0	20	0	0
T45	0	6	0	0
T46	0	7	0	0
T47	0	11	0	0
T48	86911	10	0	0
T49	0	21	0	0
T50	0	5	0	0
T51	2898	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57848328	52415	0	0
T1	158274	188	0	0
T2	304452	211	0	0
T3	8343	12	0	0
T4	0	74	0	0
T5	3834	18	0	0
T6	6615	9	0	0
T13	3636	0	0	0
T14	4644	2	0	0
T15	3645	0	0	0
T16	3645	0	0	0
T17	6246	9	0	0
T18	0	179	0	0
T19	0	39	0	0
T28	0	41	0	0
T29	0	25	0	0
T30	0	10	0	0
T32	0	200	0	0
T43	0	11	0	0
T51	0	7	0	0
T66	0	6	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32137960	28770150	0	0
T1	87930	57745	0	0
T2	169140	166720	0	0
T3	4635	2635	0	0
T5	2130	130	0	0
T6	3675	1675	0	0
T13	2020	20	0	0
T14	2580	580	0	0
T15	2025	25	0	0
T16	2025	25	0	0
T17	3470	1470	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109269064	97818510	0	0
T1	298962	196333	0	0
T2	575076	566848	0	0
T3	15759	8959	0	0
T5	7242	442	0	0
T6	12495	5695	0	0
T13	6868	68	0	0
T14	8772	1972	0	0
T15	6885	85	0	0
T16	6885	85	0	0
T17	11798	4998	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57848328	51786270	0	0
T1	158274	103941	0	0
T2	304452	300096	0	0
T3	8343	4743	0	0
T5	3834	234	0	0
T6	6615	3015	0	0
T13	3636	36	0	0
T14	4644	1044	0	0
T15	3645	45	0	0
T16	3645	45	0	0
T17	6246	2646	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147834616	5252	0	0
T1	70344	4	0	0
T2	304452	29	0	0
T3	10197	0	0	0
T4	103040	4	0	0
T6	735	1	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	23	0	0
T13	1616	0	0	0
T14	5676	0	0	0
T15	4455	0	0	0
T16	4455	0	0	0
T17	7634	1	0	0
T18	52503	3	0	0
T19	5030	0	0	0
T26	3619	0	0	0
T27	8792	0	0	0
T31	0	1	0	0
T32	25664	0	0	0
T35	0	4	0	0
T36	674	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	86911	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	2898	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19282776	184501	0	0
T25	1848	149	0	0
T26	10857	273	0	0
T27	26376	121	0	0
T36	2022	0	0	0
T38	165420	0	0	0
T40	0	950	0	0
T48	260733	0	0	0
T52	53922	0	0	0
T53	1653	0	0	0
T54	1572	0	0	0
T56	0	432	0	0
T57	0	340	0	0
T58	0	476	0	0
T59	0	1077	0	0
T76	0	287	0	0
T77	1218	0	0	0
T109	0	365	0	0
T110	0	1773	0	0
T111	0	55	0	0
T112	0	577	0	0
T113	1044	0	0	0