Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T9,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T8,T9,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T9,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T35
1	0	Covered	T5,T6,T1
1	1	Covered	T8,T9,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T35
0	1	Covered	T155,T124,T156
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T35
0	1	Covered	T8,T35,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T35
1	-	Covered	T8,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T35
DetectSt	168	Covered	T8,T9,T35
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T8,T9,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T35
DebounceSt->IdleSt	163	Covered	T75,T140,T157
DetectSt->IdleSt	186	Covered	T155,T124,T156
DetectSt->StableSt	191	Covered	T8,T9,T35
IdleSt->DebounceSt	148	Covered	T8,T9,T35
StableSt->IdleSt	206	Covered	T8,T35,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T35
0	1	Covered	T8,T9,T35
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T35
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T140,T157,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T35
DetectSt	-	-	-	-	1	-	-	Covered	T155,T124,T156
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	95	0	0
CntIncr_A	6427592	84017	0	0
CntNoWrap_A	6427592	5751498	0	0
DetectStDropOut_A	6427592	3	0	0
DetectedOut_A	6427592	25954	0	0
DetectedPulseOut_A	6427592	42	0	0
DisabledIdleSt_A	6427592	5206097	0	0
DisabledNoDetection_A	6427592	5208485	0	0
EnterDebounceSt_A	6427592	50	0	0
EnterDetectSt_A	6427592	45	0	0
EnterStableSt_A	6427592	42	0	0
PulseIsPulse_A	6427592	42	0	0
StayInStableSt	6427592	25890	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	95	0	0
T8	13249	2	0	0
T9	1569	2	0	0
T10	12980	0	0	0
T26	0	2	0	0
T31	791	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T40	0	2	0	0
T41	0	4	0	0
T68	521	0	0	0
T69	506	0	0	0
T159	0	2	0	0
T160	0	4	0	0
T161	0	2	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	84017	0	0
T8	13249	78	0	0
T9	1569	89	0	0
T10	12980	0	0	0
T26	0	27	0	0
T31	791	0	0	0
T35	0	57086	0	0
T36	0	60	0	0
T40	0	77	0	0
T41	0	32	0	0
T68	521	0	0	0
T69	506	0	0	0
T159	0	98	0	0
T160	0	32	0	0
T161	0	24580	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751498	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3	0	0
T88	1078	0	0	0
T124	0	1	0	0
T155	1011	1	0	0
T156	0	1	0	0
T166	9621	0	0	0
T167	17710	0	0	0
T168	521	0	0	0
T169	644	0	0	0
T170	514	0	0	0
T171	6417	0	0	0
T172	426	0	0	0
T173	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	25954	0	0
T8	13249	63	0	0
T9	1569	51	0	0
T10	12980	0	0	0
T26	0	37	0	0
T31	791	0	0	0
T35	0	41	0	0
T36	0	112	0	0
T40	0	41	0	0
T41	0	162	0	0
T68	521	0	0	0
T69	506	0	0	0
T159	0	39	0	0
T160	0	84	0	0
T161	0	23376	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	42	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T159	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5206097	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5208485	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	50	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T159	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	45	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T159	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	42	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T159	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	42	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T159	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	25890	0	0
T8	13249	62	0	0
T9	1569	49	0	0
T10	12980	0	0	0
T26	0	35	0	0
T31	791	0	0	0
T35	0	40	0	0
T36	0	109	0	0
T40	0	39	0	0
T41	0	159	0	0
T68	521	0	0	0
T69	506	0	0	0
T159	0	37	0	0
T160	0	82	0	0
T161	0	23375	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	20	0	0
T8	13249	1	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T41	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T134	0	3	0	0
T136	0	1	0	0
T155	0	1	0	0
T160	0	2	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T26,T36,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T26,T36,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T26,T36,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T26
1	0	Covered	T5,T1,T2
1	1	Covered	T26,T36,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T36,T39
0	1	Covered	T112
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T36,T39
0	1	Covered	T26,T36,T135
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T26,T36,T39
1	-	Covered	T26,T36,T135

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T36,T39
DetectSt	168	Covered	T26,T36,T39
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T26,T36,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T36,T39
DebounceSt->IdleSt	163	Covered	T36,T75,T139
DetectSt->IdleSt	186	Covered	T112
DetectSt->StableSt	191	Covered	T26,T36,T39
IdleSt->DebounceSt	148	Covered	T26,T36,T39
StableSt->IdleSt	206	Covered	T26,T36,T110

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T36,T39
0	1	Covered	T26,T36,T39
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T36,T39
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T36,T39
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T36,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T36
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T36,T39
DetectSt	-	-	-	-	1	-	-	Covered	T112
DetectSt	-	-	-	-	0	1	-	Covered	T26,T36,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T26,T36,T135
StableSt	-	-	-	-	-	-	0	Covered	T26,T36,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	111	0	0
CntIncr_A	6427592	8170	0	0
CntNoWrap_A	6427592	5751482	0	0
DetectStDropOut_A	6427592	1	0	0
DetectedOut_A	6427592	4910	0	0
DetectedPulseOut_A	6427592	53	0	0
DisabledIdleSt_A	6427592	5732063	0	0
DisabledNoDetection_A	6427592	5734454	0	0
EnterDebounceSt_A	6427592	58	0	0
EnterDetectSt_A	6427592	54	0	0
EnterStableSt_A	6427592	53	0	0
PulseIsPulse_A	6427592	53	0	0
StayInStableSt	6427592	4834	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6427592	3076	0	0
gen_low_level_sva.LowLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	111	0	0
T26	3619	2	0	0
T27	8792	0	0	0
T36	674	3	0	0
T38	55140	0	0	0
T39	0	2	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T75	0	1	0	0
T77	406	0	0	0
T110	0	2	0	0
T112	0	6	0	0
T113	522	0	0	0
T134	0	6	0	0
T135	0	4	0	0
T175	0	2	0	0
T176	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	8170	0	0
T26	3619	27	0	0
T27	8792	0	0	0
T36	674	60	0	0
T38	55140	0	0	0
T39	0	42	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T75	0	42	0	0
T77	406	0	0	0
T110	0	79	0	0
T112	0	57	0	0
T113	522	0	0	0
T134	0	132	0	0
T135	0	178	0	0
T175	0	39	0	0
T176	0	172	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751482	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1	0	0
T96	26044	0	0	0
T112	14267	1	0	0
T136	37825	0	0	0
T177	21598	0	0	0
T178	422	0	0	0
T179	505	0	0	0
T180	20896	0	0	0
T181	628	0	0	0
T182	510	0	0	0
T183	441	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	4910	0	0
T26	3619	205	0	0
T27	8792	0	0	0
T36	674	55	0	0
T38	55140	0	0	0
T39	0	177	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T77	406	0	0	0
T110	0	126	0	0
T112	0	155	0	0
T113	522	0	0	0
T134	0	95	0	0
T135	0	209	0	0
T175	0	64	0	0
T176	0	86	0	0
T184	0	184	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	53	0	0
T26	3619	1	0	0
T27	8792	0	0	0
T36	674	1	0	0
T38	55140	0	0	0
T39	0	1	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T77	406	0	0	0
T110	0	1	0	0
T112	0	2	0	0
T113	522	0	0	0
T134	0	3	0	0
T135	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5732063	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5734454	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	58	0	0
T26	3619	1	0	0
T27	8792	0	0	0
T36	674	2	0	0
T38	55140	0	0	0
T39	0	1	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T75	0	1	0	0
T77	406	0	0	0
T110	0	1	0	0
T112	0	3	0	0
T113	522	0	0	0
T134	0	3	0	0
T135	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	54	0	0
T26	3619	1	0	0
T27	8792	0	0	0
T36	674	1	0	0
T38	55140	0	0	0
T39	0	1	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T77	406	0	0	0
T110	0	1	0	0
T112	0	3	0	0
T113	522	0	0	0
T134	0	3	0	0
T135	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	53	0	0
T26	3619	1	0	0
T27	8792	0	0	0
T36	674	1	0	0
T38	55140	0	0	0
T39	0	1	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T77	406	0	0	0
T110	0	1	0	0
T112	0	2	0	0
T113	522	0	0	0
T134	0	3	0	0
T135	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	53	0	0
T26	3619	1	0	0
T27	8792	0	0	0
T36	674	1	0	0
T38	55140	0	0	0
T39	0	1	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T77	406	0	0	0
T110	0	1	0	0
T112	0	2	0	0
T113	522	0	0	0
T134	0	3	0	0
T135	0	2	0	0
T175	0	1	0	0
T176	0	2	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	4834	0	0
T26	3619	204	0	0
T27	8792	0	0	0
T36	674	54	0	0
T38	55140	0	0	0
T39	0	175	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T77	406	0	0	0
T110	0	124	0	0
T112	0	152	0	0
T113	522	0	0	0
T134	0	91	0	0
T135	0	206	0	0
T175	0	62	0	0
T176	0	83	0	0
T184	0	182	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3076	0	0
T1	17586	24	0	0
T2	33828	0	0	0
T3	927	3	0	0
T5	426	3	0	0
T6	735	0	0	0
T13	404	0	0	0
T14	516	2	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T19	0	3	0	0
T28	0	5	0	0
T29	0	5	0	0
T30	0	5	0	0
T43	0	6	0	0
T51	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	30	0	0
T26	3619	1	0	0
T27	8792	0	0	0
T36	674	1	0	0
T38	55140	0	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T77	406	0	0	0
T112	0	1	0	0
T113	522	0	0	0
T134	0	2	0	0
T135	0	1	0	0
T155	0	2	0	0
T174	0	2	0	0
T176	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T8,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T3,T8,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T8,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T37
1	0	Covered	T5,T1,T2
1	1	Covered	T3,T8,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T27
0	1	Covered	T8,T145
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T27
0	1	Covered	T3,T8,T159
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T27
1	-	Covered	T3,T8,T159

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T27
DetectSt	168	Covered	T3,T8,T27
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T8,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T27
DebounceSt->IdleSt	163	Covered	T40,T75,T117
DetectSt->IdleSt	186	Covered	T8,T145
DetectSt->StableSt	191	Covered	T3,T8,T27
IdleSt->DebounceSt	148	Covered	T3,T8,T27
StableSt->IdleSt	206	Covered	T3,T8,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T27
0	1	Covered	T3,T8,T27
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T27
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T117,T144
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T27
DetectSt	-	-	-	-	1	-	-	Covered	T8,T145
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T159
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	100	0	0
CntIncr_A	6427592	156484	0	0
CntNoWrap_A	6427592	5751493	0	0
DetectStDropOut_A	6427592	2	0	0
DetectedOut_A	6427592	94185	0	0
DetectedPulseOut_A	6427592	45	0	0
DisabledIdleSt_A	6427592	5360912	0	0
DisabledNoDetection_A	6427592	5363307	0	0
EnterDebounceSt_A	6427592	53	0	0
EnterDetectSt_A	6427592	47	0	0
EnterStableSt_A	6427592	45	0	0
PulseIsPulse_A	6427592	45	0	0
StayInStableSt	6427592	94119	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	100	0	0
T3	927	4	0	0
T4	14720	0	0	0
T8	0	4	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	2	0	0
T32	12832	0	0	0
T38	0	2	0	0
T40	0	3	0	0
T51	414	0	0	0
T114	0	2	0	0
T126	0	2	0	0
T146	0	4	0	0
T159	0	4	0	0
T161	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	156484	0	0
T3	927	112	0	0
T4	14720	0	0	0
T8	0	156	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	60	0	0
T32	12832	0	0	0
T38	0	27768	0	0
T40	0	26	0	0
T51	414	0	0	0
T114	0	14	0	0
T126	0	96	0	0
T146	0	76882	0	0
T159	0	196	0	0
T161	0	49160	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751493	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	522	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2	0	0
T8	13249	1	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T68	521	0	0	0
T69	506	0	0	0
T145	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	94185	0	0
T3	927	255	0	0
T4	14720	0	0	0
T8	0	39	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	104	0	0
T32	12832	0	0	0
T38	0	26963	0	0
T40	0	37	0	0
T51	414	0	0	0
T114	0	66	0	0
T126	0	474	0	0
T146	0	62211	0	0
T159	0	246	0	0
T161	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	45	0	0
T3	927	2	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	1	0	0
T32	12832	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T114	0	1	0	0
T126	0	1	0	0
T146	0	2	0	0
T159	0	2	0	0
T161	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5360912	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	3	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5363307	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	3	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	53	0	0
T3	927	2	0	0
T4	14720	0	0	0
T8	0	2	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	1	0	0
T32	12832	0	0	0
T38	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T114	0	1	0	0
T126	0	1	0	0
T146	0	2	0	0
T159	0	2	0	0
T161	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	47	0	0
T3	927	2	0	0
T4	14720	0	0	0
T8	0	2	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	1	0	0
T32	12832	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T114	0	1	0	0
T126	0	1	0	0
T146	0	2	0	0
T159	0	2	0	0
T161	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	45	0	0
T3	927	2	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	1	0	0
T32	12832	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T114	0	1	0	0
T126	0	1	0	0
T146	0	2	0	0
T159	0	2	0	0
T161	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	45	0	0
T3	927	2	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	1	0	0
T32	12832	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T51	414	0	0	0
T114	0	1	0	0
T126	0	1	0	0
T146	0	2	0	0
T159	0	2	0	0
T161	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	94119	0	0
T3	927	252	0	0
T4	14720	0	0	0
T8	0	38	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	102	0	0
T32	12832	0	0	0
T38	0	26961	0	0
T40	0	35	0	0
T51	414	0	0	0
T114	0	65	0	0
T126	0	472	0	0
T146	0	62208	0	0
T159	0	243	0	0
T161	0	77	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	24	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T51	414	0	0	0
T114	0	1	0	0
T117	0	1	0	0
T133	0	1	0	0
T135	0	1	0	0
T137	0	1	0	0
T146	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T26,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T8,T26,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T26,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T26
1	0	Covered	T5,T1,T2
1	1	Covered	T8,T26,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T26,T40
0	1	Covered	T8,T26,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T26,T40
1	-	Covered	T8,T26,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T26,T36
DetectSt	168	Covered	T8,T26,T40
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T8,T26,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T26,T40
DebounceSt->IdleSt	163	Covered	T36,T75,T79
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T26,T40
IdleSt->DebounceSt	148	Covered	T8,T26,T36
StableSt->IdleSt	206	Covered	T8,T26,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T26,T36
0	1	Covered	T8,T26,T36
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T26,T40
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T26,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T26,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T36
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T26,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T26,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T26,T40
StableSt	-	-	-	-	-	-	0	Covered	T8,T26,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	87	0	0
CntIncr_A	6427592	2492	0	0
CntNoWrap_A	6427592	5751506	0	0
DetectStDropOut_A	6427592	0	0	0
DetectedOut_A	6427592	2687	0	0
DetectedPulseOut_A	6427592	42	0	0
DisabledIdleSt_A	6427592	5727517	0	0
DisabledNoDetection_A	6427592	5729899	0	0
EnterDebounceSt_A	6427592	45	0	0
EnterDetectSt_A	6427592	42	0	0
EnterStableSt_A	6427592	42	0	0
PulseIsPulse_A	6427592	42	0	0
StayInStableSt	6427592	2624	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6427592	6712	0	0
gen_low_level_sva.LowLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	87	0	0
T8	13249	4	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	2	0	0
T31	791	0	0	0
T36	0	1	0	0
T40	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	1	0	0
T112	0	2	0	0
T114	0	2	0	0
T133	0	2	0	0
T136	0	4	0	0
T159	0	2	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2492	0	0
T8	13249	156	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	27	0	0
T31	791	0	0	0
T36	0	30	0	0
T40	0	13	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	42	0	0
T112	0	21	0	0
T114	0	14	0	0
T133	0	38	0	0
T136	0	154	0	0
T159	0	98	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751506	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2687	0	0
T8	13249	330	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	133	0	0
T31	791	0	0	0
T40	0	61	0	0
T68	521	0	0	0
T69	506	0	0	0
T112	0	15	0	0
T114	0	60	0	0
T133	0	46	0	0
T136	0	197	0	0
T159	0	42	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T176	0	42	0	0
T187	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	42	0	0
T8	13249	2	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	1	0	0
T136	0	2	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T176	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5727517	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5729899	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	45	0	0
T8	13249	2	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	1	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	1	0	0
T136	0	2	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	42	0	0
T8	13249	2	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	1	0	0
T136	0	2	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T176	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	42	0	0
T8	13249	2	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	1	0	0
T136	0	2	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T176	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	42	0	0
T8	13249	2	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T112	0	1	0	0
T114	0	1	0	0
T133	0	1	0	0
T136	0	2	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T176	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2624	0	0
T8	13249	327	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	132	0	0
T31	791	0	0	0
T40	0	60	0	0
T68	521	0	0	0
T69	506	0	0	0
T112	0	14	0	0
T114	0	58	0	0
T133	0	44	0	0
T136	0	194	0	0
T159	0	41	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T176	0	40	0	0
T187	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	6712	0	0
T1	17586	22	0	0
T2	33828	35	0	0
T3	927	1	0	0
T4	0	10	0	0
T5	426	2	0	0
T6	735	0	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	0	18	0	0
T19	0	5	0	0
T28	0	9	0	0
T32	0	17	0	0
T51	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	21	0	0
T8	13249	1	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T26	0	1	0	0
T31	791	0	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T112	0	1	0	0
T134	0	2	0	0
T136	0	1	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T174	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T3,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T5,T1,T2
1	1	Covered	T3,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T27
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T8,T26
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T9
1	-	Covered	T3,T8,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T9
DetectSt	168	Covered	T3,T8,T9
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T9
DebounceSt->IdleSt	163	Covered	T36,T60,T75
DetectSt->IdleSt	186	Covered	T27
DetectSt->StableSt	191	Covered	T3,T8,T9
IdleSt->DebounceSt	148	Covered	T3,T8,T9
StableSt->IdleSt	206	Covered	T3,T8,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T186,T189
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T27
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T26
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	123	0	0
CntIncr_A	6427592	43714	0	0
CntNoWrap_A	6427592	5751470	0	0
DetectStDropOut_A	6427592	1	0	0
DetectedOut_A	6427592	28252	0	0
DetectedPulseOut_A	6427592	56	0	0
DisabledIdleSt_A	6427592	5504931	0	0
DisabledNoDetection_A	6427592	5507314	0	0
EnterDebounceSt_A	6427592	67	0	0
EnterDetectSt_A	6427592	57	0	0
EnterStableSt_A	6427592	56	0	0
PulseIsPulse_A	6427592	56	0	0
StayInStableSt	6427592	28170	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	123	0	0
T3	927	2	0	0
T4	14720	0	0	0
T8	0	4	0	0
T9	0	2	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	2	0	0
T27	0	2	0	0
T32	12832	0	0	0
T36	0	3	0	0
T40	0	4	0	0
T51	414	0	0	0
T75	0	1	0	0
T114	0	2	0	0
T146	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	43714	0	0
T3	927	56	0	0
T4	14720	0	0	0
T8	0	156	0	0
T9	0	89	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	27	0	0
T27	0	60	0	0
T32	12832	0	0	0
T36	0	60	0	0
T40	0	26	0	0
T51	414	0	0	0
T60	0	1838	0	0
T114	0	14	0	0
T146	0	38441	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751470	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	524	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1	0	0
T27	8792	1	0	0
T38	55140	0	0	0
T39	837	0	0	0
T49	687	0	0	0
T65	1917	0	0	0
T74	8598	0	0	0
T77	406	0	0	0
T113	522	0	0	0
T190	428	0	0	0
T191	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	28252	0	0
T3	927	305	0	0
T4	14720	0	0	0
T8	0	162	0	0
T9	0	187	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	161	0	0
T32	12832	0	0	0
T36	0	154	0	0
T40	0	97	0	0
T51	414	0	0	0
T114	0	87	0	0
T146	0	23117	0	0
T192	0	84	0	0
T193	0	132	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	56	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	2	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T32	12832	0	0	0
T36	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T114	0	1	0	0
T146	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5504931	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	3	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5507314	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	3	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	67	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	2	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	12832	0	0	0
T36	0	2	0	0
T40	0	2	0	0
T51	414	0	0	0
T60	0	1	0	0
T114	0	1	0	0
T146	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	57	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	2	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	12832	0	0	0
T36	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T114	0	1	0	0
T146	0	1	0	0
T192	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	56	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	2	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T32	12832	0	0	0
T36	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T114	0	1	0	0
T146	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	56	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	2	0	0
T9	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T32	12832	0	0	0
T36	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T114	0	1	0	0
T146	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	28170	0	0
T3	927	304	0	0
T4	14720	0	0	0
T8	0	159	0	0
T9	0	185	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	160	0	0
T32	12832	0	0	0
T36	0	152	0	0
T40	0	94	0	0
T51	414	0	0	0
T114	0	86	0	0
T146	0	23116	0	0
T192	0	82	0	0
T193	0	131	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	30	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T32	12832	0	0	0
T40	0	1	0	0
T51	414	0	0	0
T110	0	2	0	0
T114	0	1	0	0
T135	0	1	0	0
T146	0	1	0	0
T155	0	1	0	0
T193	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T8,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T3,T8,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T8,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T35
1	0	Covered	T5,T1,T2
1	1	Covered	T3,T8,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T35
0	1	Covered	T142
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T35
0	1	Covered	T8,T35,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T35
1	-	Covered	T8,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T35
DetectSt	168	Covered	T3,T8,T35
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T8,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T35
DebounceSt->IdleSt	163	Covered	T75,T110,T194
DetectSt->IdleSt	186	Covered	T142
DetectSt->StableSt	191	Covered	T3,T8,T35
IdleSt->DebounceSt	148	Covered	T3,T8,T35
StableSt->IdleSt	206	Covered	T8,T35,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T35
0	1	Covered	T3,T8,T35
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T35
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T110,T194,T142
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T35
DetectSt	-	-	-	-	1	-	-	Covered	T142
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	95	0	0
CntIncr_A	6427592	179503	0	0
CntNoWrap_A	6427592	5751498	0	0
DetectStDropOut_A	6427592	1	0	0
DetectedOut_A	6427592	173546	0	0
DetectedPulseOut_A	6427592	44	0	0
DisabledIdleSt_A	6427592	5003940	0	0
DisabledNoDetection_A	6427592	5006321	0	0
EnterDebounceSt_A	6427592	50	0	0
EnterDetectSt_A	6427592	45	0	0
EnterStableSt_A	6427592	44	0	0
PulseIsPulse_A	6427592	44	0	0
StayInStableSt	6427592	173479	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6427592	6423	0	0
gen_low_level_sva.LowLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	95	0	0
T3	927	2	0	0
T4	14720	0	0	0
T8	0	2	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	2	0	0
T27	0	2	0	0
T32	12832	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	6	0	0
T51	414	0	0	0
T160	0	2	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	179503	0	0
T3	927	56	0	0
T4	14720	0	0	0
T8	0	78	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	27	0	0
T27	0	60	0	0
T32	12832	0	0	0
T35	0	114172	0	0
T36	0	30	0	0
T39	0	42	0	0
T41	0	48	0	0
T51	414	0	0	0
T160	0	16	0	0
T161	0	24580	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751498	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	524	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1	0	0
T119	18405	0	0	0
T142	1101	1	0	0
T195	692	0	0	0
T196	787	0	0	0
T197	17032	0	0	0
T198	502	0	0	0
T199	42206	0	0	0
T200	660	0	0	0
T201	492	0	0	0
T202	557	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	173546	0	0
T3	927	40	0	0
T4	14720	0	0	0
T8	0	287	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	92	0	0
T27	0	42	0	0
T32	12832	0	0	0
T35	0	122087	0	0
T36	0	44	0	0
T39	0	12	0	0
T41	0	128	0	0
T51	414	0	0	0
T160	0	137	0	0
T161	0	47999	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	44	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	12832	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	3	0	0
T51	414	0	0	0
T160	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5003940	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	3	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5006321	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	3	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	50	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	12832	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	3	0	0
T51	414	0	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	45	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	12832	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	3	0	0
T51	414	0	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	44	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	12832	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	3	0	0
T51	414	0	0	0
T160	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	44	0	0
T3	927	1	0	0
T4	14720	0	0	0
T8	0	1	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	1	0	0
T27	0	1	0	0
T32	12832	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	3	0	0
T51	414	0	0	0
T160	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	173479	0	0
T3	927	38	0	0
T4	14720	0	0	0
T8	0	286	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T26	0	90	0	0
T27	0	40	0	0
T32	12832	0	0	0
T35	0	122084	0	0
T36	0	43	0	0
T39	0	11	0	0
T41	0	124	0	0
T51	414	0	0	0
T160	0	136	0	0
T161	0	47997	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	6423	0	0
T1	17586	18	0	0
T2	33828	34	0	0
T3	927	1	0	0
T4	0	11	0	0
T5	426	2	0	0
T6	735	0	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	0	28	0	0
T19	0	5	0	0
T28	0	7	0	0
T29	0	7	0	0
T32	0	37	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	21	0	0
T8	13249	1	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T112	0	1	0	0
T134	0	2	0	0
T155	0	1	0	0
T160	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T174	0	1	0	0