Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.41	97.83	90.48		100.00	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.41	97.83	90.48		100.00	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T35,T36,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T35,T36,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T35,T36,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T41
1	0	Covered	T5,T1,T2
1	1	Covered	T35,T36,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T41
0	1	Covered	T160,T110,T203
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T41
0	1	Covered	T35,T36,T159
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T41
1	-	Covered	T35,T36,T159

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T41
DetectSt	168	Covered	T35,T36,T41
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T35,T36,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T41
DebounceSt->IdleSt	163	Covered	T36,T41,T75
DetectSt->IdleSt	186	Covered	T160,T110,T203
DetectSt->StableSt	191	Covered	T35,T36,T41
IdleSt->DebounceSt	148	Covered	T35,T36,T41
StableSt->IdleSt	206	Covered	T35,T36,T159

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T36,T41
0	1	Covered	T35,T36,T41
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T41
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T41,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T41
DetectSt	-	-	-	-	1	-	-	Covered	T160,T110,T203
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T159
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	104	0	0
CntIncr_A	6427592	173936	0	0
CntNoWrap_A	6427592	5751489	0	0
DetectStDropOut_A	6427592	3	0	0
DetectedOut_A	6427592	13790	0	0
DetectedPulseOut_A	6427592	46	0	0
DisabledIdleSt_A	6427592	5385299	0	0
DisabledNoDetection_A	6427592	5387696	0	0
EnterDebounceSt_A	6427592	55	0	0
EnterDetectSt_A	6427592	49	0	0
EnterStableSt_A	6427592	46	0	0
PulseIsPulse_A	6427592	46	0	0
StayInStableSt	6427592	13723	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	104	0	0
T35	371837	6	0	0
T36	0	5	0	0
T37	494	0	0	0
T41	0	3	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T75	0	1	0	0
T110	0	6	0	0
T159	0	2	0	0
T160	0	4	0	0
T175	0	2	0	0
T205	0	2	0	0
T206	0	2	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	173936	0	0
T35	371837	171258	0	0
T36	0	90	0	0
T37	494	0	0	0
T41	0	32	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T75	0	42	0	0
T110	0	109	0	0
T159	0	98	0	0
T160	0	32	0	0
T175	0	39	0	0
T205	0	21	0	0
T206	0	66	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751489	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3	0	0
T58	1296	0	0	0
T93	4516	0	0	0
T110	0	1	0	0
T126	980	0	0	0
T160	639	1	0	0
T203	0	1	0	0
T212	504	0	0	0
T213	402	0	0	0
T214	490	0	0	0
T215	434	0	0	0
T216	402	0	0	0
T217	34801	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	13790	0	0
T35	371837	10550	0	0
T36	0	91	0	0
T37	494	0	0	0
T41	0	49	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	54	0	0
T136	0	78	0	0
T159	0	152	0	0
T160	0	40	0	0
T175	0	65	0	0
T205	0	17	0	0
T206	0	35	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T35	371837	3	0	0
T36	0	2	0	0
T37	494	0	0	0
T41	0	1	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	2	0	0
T136	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T175	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5385299	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5387696	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	55	0	0
T35	371837	3	0	0
T36	0	3	0	0
T37	494	0	0	0
T41	0	2	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T75	0	1	0	0
T110	0	3	0	0
T159	0	1	0	0
T160	0	2	0	0
T175	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	49	0	0
T35	371837	3	0	0
T36	0	2	0	0
T37	494	0	0	0
T41	0	1	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	3	0	0
T136	0	2	0	0
T159	0	1	0	0
T160	0	2	0	0
T175	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T35	371837	3	0	0
T36	0	2	0	0
T37	494	0	0	0
T41	0	1	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	2	0	0
T136	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T175	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T35	371837	3	0	0
T36	0	2	0	0
T37	494	0	0	0
T41	0	1	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	2	0	0
T136	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T175	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	13723	0	0
T35	371837	10546	0	0
T36	0	88	0	0
T37	494	0	0	0
T41	0	47	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	51	0	0
T136	0	75	0	0
T159	0	151	0	0
T160	0	39	0	0
T175	0	63	0	0
T205	0	16	0	0
T206	0	34	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	25	0	0
T35	371837	2	0	0
T36	0	1	0	0
T37	494	0	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	1	0	0
T136	0	1	0	0
T138	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0
T218	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T3,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T3,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T26
1	0	Covered	T5,T1,T2
1	1	Covered	T3,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T38,T39
0	1	Covered	T140
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T38,T39
0	1	Covered	T40,T160,T133
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T38,T39
1	-	Covered	T40,T160,T133

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T38,T39
DetectSt	168	Covered	T3,T38,T39
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T3,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T38,T39
DebounceSt->IdleSt	163	Covered	T75,T134,T124
DetectSt->IdleSt	186	Covered	T140
DetectSt->StableSt	191	Covered	T3,T38,T39
IdleSt->DebounceSt	148	Covered	T3,T38,T39
StableSt->IdleSt	206	Covered	T40,T160,T133

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T38,T39
0	1	Covered	T3,T38,T39
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T38,T39
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T134,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T140
DetectSt	-	-	-	-	0	1	-	Covered	T3,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T160,T133
StableSt	-	-	-	-	-	-	0	Covered	T3,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	66	0	0
CntIncr_A	6427592	67854	0	0
CntNoWrap_A	6427592	5751527	0	0
DetectStDropOut_A	6427592	1	0	0
DetectedOut_A	6427592	63490	0	0
DetectedPulseOut_A	6427592	30	0	0
DisabledIdleSt_A	6427592	5477571	0	0
DisabledNoDetection_A	6427592	5479962	0	0
EnterDebounceSt_A	6427592	35	0	0
EnterDetectSt_A	6427592	31	0	0
EnterStableSt_A	6427592	30	0	0
PulseIsPulse_A	6427592	30	0	0
StayInStableSt	6427592	63443	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6427592	6230	0	0
gen_low_level_sva.LowLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	66	0	0
T3	927	2	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	4	0	0
T51	414	0	0	0
T75	0	1	0	0
T110	0	2	0	0
T133	0	2	0	0
T146	0	2	0	0
T160	0	4	0	0
T205	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	67854	0	0
T3	927	56	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T38	0	27768	0	0
T39	0	42	0	0
T40	0	26	0	0
T51	414	0	0	0
T75	0	41	0	0
T110	0	79	0	0
T133	0	38	0	0
T146	0	38441	0	0
T160	0	32	0	0
T205	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751527	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	524	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1	0	0
T140	2185	1	0	0
T219	992	0	0	0
T220	5516	0	0	0
T221	424	0	0	0
T222	443	0	0	0
T223	9638	0	0	0
T224	888	0	0	0
T225	703	0	0	0
T226	525	0	0	0
T227	41453	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	63490	0	0
T3	927	130	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T38	0	41	0	0
T39	0	38	0	0
T40	0	155	0	0
T51	414	0	0	0
T110	0	46	0	0
T133	0	31	0	0
T134	0	39	0	0
T146	0	61607	0	0
T160	0	122	0	0
T205	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	30	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T110	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T146	0	1	0	0
T160	0	2	0	0
T205	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5477571	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	3	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5479962	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	3	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	35	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T75	0	1	0	0
T110	0	1	0	0
T133	0	1	0	0
T146	0	1	0	0
T160	0	2	0	0
T205	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	31	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T110	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T146	0	1	0	0
T160	0	2	0	0
T205	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	30	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T110	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T146	0	1	0	0
T160	0	2	0	0
T205	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	30	0	0
T3	927	1	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T51	414	0	0	0
T110	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T146	0	1	0	0
T160	0	2	0	0
T205	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	63443	0	0
T3	927	128	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	12832	0	0	0
T38	0	39	0	0
T39	0	36	0	0
T40	0	152	0	0
T51	414	0	0	0
T110	0	44	0	0
T133	0	30	0	0
T134	0	38	0	0
T146	0	61605	0	0
T160	0	119	0	0
T205	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	6230	0	0
T1	17586	19	0	0
T2	33828	30	0	0
T3	927	1	0	0
T4	0	9	0	0
T5	426	1	0	0
T6	735	0	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	0	24	0	0
T19	0	8	0	0
T28	0	8	0	0
T29	0	7	0	0
T32	0	18	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	13	0	0
T40	29659	1	0	0
T56	745	0	0	0
T57	746	0	0	0
T78	17668	0	0	0
T99	0	1	0	0
T104	1326	0	0	0
T105	422	0	0	0
T106	2820	0	0	0
T107	407	0	0	0
T117	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T155	0	1	0	0
T160	0	1	0	0
T186	0	2	0	0
T189	0	1	0	0
T228	0	1	0	0
T229	508	0	0	0
T230	494	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T1,T2
1	1	Covered	T5,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T35,T36,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T35,T36,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T35,T36,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T35,T36
1	0	Covered	T5,T1,T2
1	1	Covered	T35,T36,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T39,T40
0	1	Covered	T36,T193
1	0	Covered	T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T39,T40
0	1	Covered	T35,T160,T135
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T39,T40
1	-	Covered	T35,T160,T135

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T39
DetectSt	168	Covered	T35,T36,T39
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T35,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T39
DebounceSt->IdleSt	163	Covered	T36,T106,T110
DetectSt->IdleSt	186	Covered	T36,T75,T193
DetectSt->StableSt	191	Covered	T35,T39,T40
IdleSt->DebounceSt	148	Covered	T35,T36,T39
StableSt->IdleSt	206	Covered	T35,T40,T160

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T36,T39
0	1	Covered	T35,T36,T39
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T39
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T39
IdleSt	0	-	-	-	-	-	-	Covered	T5,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T106,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T39
DetectSt	-	-	-	-	1	-	-	Covered	T36,T75,T193
DetectSt	-	-	-	-	0	1	-	Covered	T35,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T160,T135
StableSt	-	-	-	-	-	-	0	Covered	T35,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	110	0	0
CntIncr_A	6427592	128675	0	0
CntNoWrap_A	6427592	5751483	0	0
DetectStDropOut_A	6427592	2	0	0
DetectedOut_A	6427592	401343	0	0
DetectedPulseOut_A	6427592	46	0	0
DisabledIdleSt_A	6427592	5053150	0	0
DisabledNoDetection_A	6427592	5055533	0	0
EnterDebounceSt_A	6427592	62	0	0
EnterDetectSt_A	6427592	49	0	0
EnterStableSt_A	6427592	46	0	0
PulseIsPulse_A	6427592	46	0	0
StayInStableSt	6427592	401276	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	110	0	0
T35	371837	2	0	0
T36	0	4	0	0
T37	494	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T75	0	2	0	0
T106	0	1	0	0
T146	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0
T193	0	2	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	128675	0	0
T35	371837	57086	0	0
T36	0	90	0	0
T37	494	0	0	0
T39	0	42	0	0
T40	0	77	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T75	0	42	0	0
T106	0	45	0	0
T146	0	38441	0	0
T160	0	16	0	0
T161	0	24580	0	0
T193	0	87	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751483	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2	0	0
T27	8792	0	0	0
T36	674	1	0	0
T38	55140	0	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T74	8598	0	0	0
T77	406	0	0	0
T113	522	0	0	0
T193	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	401343	0	0
T35	371837	238940	0	0
T37	494	0	0	0
T39	0	91	0	0
T40	0	41	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	189	0	0
T112	0	43	0	0
T135	0	242	0	0
T146	0	61607	0	0
T160	0	62	0	0
T161	0	97200	0	0
T176	0	105	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T35	371837	1	0	0
T37	494	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	2	0	0
T112	0	1	0	0
T135	0	2	0	0
T146	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T176	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5053150	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5055533	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	62	0	0
T35	371837	1	0	0
T36	0	3	0	0
T37	494	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T75	0	1	0	0
T106	0	1	0	0
T146	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T193	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	49	0	0
T35	371837	1	0	0
T36	0	1	0	0
T37	494	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T75	0	1	0	0
T110	0	2	0	0
T146	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T193	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T35	371837	1	0	0
T37	494	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	2	0	0
T112	0	1	0	0
T135	0	2	0	0
T146	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T176	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T35	371837	1	0	0
T37	494	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	2	0	0
T112	0	1	0	0
T135	0	2	0	0
T146	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T176	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	401276	0	0
T35	371837	238939	0	0
T37	494	0	0	0
T39	0	89	0	0
T40	0	39	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T110	0	185	0	0
T112	0	42	0	0
T135	0	239	0	0
T146	0	61605	0	0
T160	0	61	0	0
T161	0	97198	0	0
T176	0	104	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	25	0	0
T35	371837	1	0	0
T37	494	0	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	0	0	0
T112	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T138	0	1	0	0
T160	0	1	0	0
T174	0	1	0	0
T176	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T1,T2
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T1,T2
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T37,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T8,T37,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T37,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T36
1	0	Covered	T5,T1,T2
1	1	Covered	T8,T37,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T37,T36
0	1	Covered	T36,T40,T231
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T37,T36
1	-	Covered	T36,T40,T231

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T37,T36
DetectSt	168	Covered	T8,T37,T36
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T8,T37,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T37,T36
DebounceSt->IdleSt	163	Covered	T41,T75,T79
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T37,T36
IdleSt->DebounceSt	148	Covered	T8,T37,T36
StableSt->IdleSt	206	Covered	T8,T36,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T37,T36
0	1	Covered	T8,T37,T36
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T37,T36
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T37,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T37,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T41
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T37,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T37,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T40,T231
StableSt	-	-	-	-	-	-	0	Covered	T8,T37,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	95	0	0
CntIncr_A	6427592	2633	0	0
CntNoWrap_A	6427592	5751498	0	0
DetectStDropOut_A	6427592	0	0	0
DetectedOut_A	6427592	3929	0	0
DetectedPulseOut_A	6427592	46	0	0
DisabledIdleSt_A	6427592	5606190	0	0
DisabledNoDetection_A	6427592	5608571	0	0
EnterDebounceSt_A	6427592	49	0	0
EnterDetectSt_A	6427592	46	0	0
EnterStableSt_A	6427592	46	0	0
PulseIsPulse_A	6427592	46	0	0
StayInStableSt	6427592	3853	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6427592	6307	0	0
gen_low_level_sva.LowLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	95	0	0
T8	13249	2	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	6	0	0
T37	0	2	0	0
T40	0	4	0	0
T41	0	3	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	1	0	0
T106	0	2	0	0
T159	0	2	0	0
T160	0	2	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T193	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2633	0	0
T8	13249	78	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	90	0	0
T37	0	14	0	0
T40	0	26	0	0
T41	0	32	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	42	0	0
T106	0	45	0	0
T159	0	98	0	0
T160	0	16	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T193	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751498	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3929	0	0
T8	13249	406	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	123	0	0
T37	0	43	0	0
T40	0	87	0	0
T41	0	48	0	0
T68	521	0	0	0
T69	506	0	0	0
T106	0	47	0	0
T133	0	46	0	0
T159	0	39	0	0
T160	0	44	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T193	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T8	13249	1	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T106	0	1	0	0
T133	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5606190	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5608571	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	49	0	0
T8	13249	1	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	1	0	0
T106	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T193	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T8	13249	1	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T106	0	1	0	0
T133	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T8	13249	1	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T106	0	1	0	0
T133	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T8	13249	1	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T106	0	1	0	0
T133	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3853	0	0
T8	13249	404	0	0
T9	1569	0	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	119	0	0
T37	0	41	0	0
T40	0	84	0	0
T41	0	46	0	0
T68	521	0	0	0
T69	506	0	0	0
T106	0	45	0	0
T133	0	44	0	0
T159	0	37	0	0
T160	0	42	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T193	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	6307	0	0
T1	17586	24	0	0
T2	33828	28	0	0
T3	927	1	0	0
T4	0	14	0	0
T5	426	3	0	0
T6	735	0	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	0	28	0	0
T19	0	4	0	0
T28	0	8	0	0
T32	0	32	0	0
T51	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	16	0	0
T27	8792	0	0	0
T36	674	2	0	0
T38	55140	0	0	0
T40	0	1	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T74	8598	0	0	0
T77	406	0	0	0
T99	0	1	0	0
T113	522	0	0	0
T135	0	1	0	0
T136	0	1	0	0
T155	0	1	0	0
T188	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T231	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T9,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T8,T9,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T9,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T37
1	0	Covered	T5,T6,T1
1	1	Covered	T8,T9,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T37
0	1	Covered	T189,T142
1	0	Covered	T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T37
0	1	Covered	T8,T9,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T37
1	-	Covered	T8,T9,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T37
DetectSt	168	Covered	T8,T9,T37
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T8,T9,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T37
DebounceSt->IdleSt	163	Covered	T36,T27,T110
DetectSt->IdleSt	186	Covered	T75,T189,T142
DetectSt->StableSt	191	Covered	T8,T9,T37
IdleSt->DebounceSt	148	Covered	T8,T9,T37
StableSt->IdleSt	206	Covered	T8,T9,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T37
0	1	Covered	T8,T9,T37
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T37
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T37
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T27,T110
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T37
DetectSt	-	-	-	-	1	-	-	Covered	T75,T189,T142
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	138	0	0
CntIncr_A	6427592	72007	0	0
CntNoWrap_A	6427592	5751455	0	0
DetectStDropOut_A	6427592	2	0	0
DetectedOut_A	6427592	168489	0	0
DetectedPulseOut_A	6427592	63	0	0
DisabledIdleSt_A	6427592	5320775	0	0
DisabledNoDetection_A	6427592	5323156	0	0
EnterDebounceSt_A	6427592	73	0	0
EnterDetectSt_A	6427592	66	0	0
EnterStableSt_A	6427592	63	0	0
PulseIsPulse_A	6427592	63	0	0
StayInStableSt	6427592	168395	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	138	0	0
T8	13249	2	0	0
T9	1569	2	0	0
T10	12980	0	0	0
T27	0	1	0	0
T31	791	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T39	0	4	0	0
T41	0	4	0	0
T68	521	0	0	0
T69	506	0	0	0
T126	0	4	0	0
T159	0	2	0	0
T160	0	2	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	72007	0	0
T8	13249	78	0	0
T9	1569	89	0	0
T10	12980	0	0	0
T27	0	60	0	0
T31	791	0	0	0
T36	0	60	0	0
T37	0	14	0	0
T39	0	84	0	0
T41	0	32	0	0
T68	521	0	0	0
T69	506	0	0	0
T126	0	192	0	0
T159	0	98	0	0
T160	0	16	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751455	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2	0	0
T117	13925	0	0	0
T142	0	1	0	0
T189	975	1	0	0
T194	562	0	0	0
T232	5920	0	0	0
T233	412	0	0	0
T234	437	0	0	0
T235	426	0	0	0
T236	721	0	0	0
T237	717	0	0	0
T238	24080	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	168489	0	0
T8	13249	382	0	0
T9	1569	47	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	43	0	0
T37	0	70	0	0
T39	0	257	0	0
T41	0	121	0	0
T68	521	0	0	0
T69	506	0	0	0
T126	0	78	0	0
T159	0	349	0	0
T160	0	196	0	0
T161	0	41	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	63	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T126	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5320775	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5323156	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	73	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T27	0	1	0	0
T31	791	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T126	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	66	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T126	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	63	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T126	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	63	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T126	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	168395	0	0
T8	13249	381	0	0
T9	1569	46	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	42	0	0
T37	0	68	0	0
T39	0	254	0	0
T41	0	118	0	0
T68	521	0	0	0
T69	506	0	0	0
T126	0	75	0	0
T159	0	348	0	0
T160	0	194	0	0
T161	0	39	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	32	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T112	0	1	0	0
T126	0	1	0	0
T133	0	1	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T231	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T9,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T8,T9,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T8,T9,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T37
1	0	Covered	T5,T6,T1
1	1	Covered	T8,T9,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T36
0	1	Not Covered
1	0	Covered	T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T36
0	1	Covered	T36,T39,T112
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T36
1	-	Covered	T36,T39,T112

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T36
DetectSt	168	Covered	T8,T9,T36
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T8,T9,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T36
DebounceSt->IdleSt	163	Covered	T79
DetectSt->IdleSt	186	Covered	T75
DetectSt->StableSt	191	Covered	T8,T9,T36
IdleSt->DebounceSt	148	Covered	T8,T9,T36
StableSt->IdleSt	206	Covered	T8,T36,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T36
0	1	Covered	T8,T9,T36
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T36
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T36
DetectSt	-	-	-	-	1	-	-	Covered	T75
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T39,T112
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	95	0	0
CntIncr_A	6427592	2240	0	0
CntNoWrap_A	6427592	5751498	0	0
DetectStDropOut_A	6427592	0	0	0
DetectedOut_A	6427592	4027	0	0
DetectedPulseOut_A	6427592	46	0	0
DisabledIdleSt_A	6427592	5320342	0	0
DisabledNoDetection_A	6427592	5322720	0	0
EnterDebounceSt_A	6427592	48	0	0
EnterDetectSt_A	6427592	47	0	0
EnterStableSt_A	6427592	46	0	0
PulseIsPulse_A	6427592	46	0	0
StayInStableSt	6427592	3958	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6427592	7010	0	0
gen_low_level_sva.LowLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	95	0	0
T8	13249	2	0	0
T9	1569	2	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	4	0	0
T39	0	2	0	0
T40	0	2	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	2	0	0
T110	0	2	0	0
T133	0	2	0	0
T159	0	2	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T175	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2240	0	0
T8	13249	78	0	0
T9	1569	89	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	60	0	0
T39	0	42	0	0
T40	0	13	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	42	0	0
T110	0	15	0	0
T133	0	38	0	0
T159	0	98	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T175	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5751498	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	4027	0	0
T8	13249	145	0	0
T9	1569	51	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	123	0	0
T39	0	43	0	0
T40	0	38	0	0
T68	521	0	0	0
T69	506	0	0	0
T110	0	47	0	0
T112	0	47	0	0
T133	0	47	0	0
T159	0	38	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T175	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T110	0	1	0	0
T112	0	2	0	0
T133	0	1	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5320342	0	0
T1	17586	11530	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5322720	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	48	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	1	0	0
T110	0	1	0	0
T133	0	1	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T175	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	47	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T75	0	1	0	0
T110	0	1	0	0
T133	0	1	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T110	0	1	0	0
T112	0	2	0	0
T133	0	1	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	46	0	0
T8	13249	1	0	0
T9	1569	1	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T68	521	0	0	0
T69	506	0	0	0
T110	0	1	0	0
T112	0	2	0	0
T133	0	1	0	0
T159	0	1	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3958	0	0
T8	13249	143	0	0
T9	1569	49	0	0
T10	12980	0	0	0
T31	791	0	0	0
T36	0	120	0	0
T39	0	42	0	0
T40	0	36	0	0
T68	521	0	0	0
T69	506	0	0	0
T110	0	45	0	0
T112	0	44	0	0
T133	0	45	0	0
T159	0	36	0	0
T162	425	0	0	0
T163	422	0	0	0
T164	427	0	0	0
T165	423	0	0	0
T175	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	7010	0	0
T1	17586	22	0	0
T2	33828	28	0	0
T3	927	1	0	0
T4	0	10	0	0
T5	426	1	0	0
T6	735	3	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	3	0	0
T18	0	27	0	0
T19	0	3	0	0
T32	0	32	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	23	0	0
T27	8792	0	0	0
T36	674	1	0	0
T38	55140	0	0	0
T39	0	1	0	0
T48	86911	0	0	0
T52	17974	0	0	0
T53	551	0	0	0
T54	524	0	0	0
T74	8598	0	0	0
T77	406	0	0	0
T112	0	1	0	0
T113	522	0	0	0
T134	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T141	0	2	0	0
T142	0	2	0	0
T189	0	1	0	0
T239	0	1	0	0