Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T18,T32
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T32
1	0	Covered	T2,T32,T12
1	1	Covered	T2,T18,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T32
0	1	Covered	T71,T73,T89
1	0	Covered	T55,T94,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T32
0	1	Covered	T2,T18,T32
1	0	Covered	T75,T197

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T18,T32
1	-	Covered	T2,T18,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T18,T32
DetectSt	168	Covered	T2,T18,T32
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T2,T18,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T18,T32
DebounceSt->IdleSt	163	Covered	T18,T75,T240
DetectSt->IdleSt	186	Covered	T55,T71,T73
DetectSt->StableSt	191	Covered	T2,T18,T32
IdleSt->DebounceSt	148	Covered	T2,T18,T32
StableSt->IdleSt	206	Covered	T2,T18,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T18,T32
0	1	Covered	T2,T18,T32
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T18,T32
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T18,T32
IdleSt	0	-	-	-	-	-	-	Covered	T2,T18,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T18,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T75,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T18,T32
DetectSt	-	-	-	-	1	-	-	Covered	T55,T71,T73
DetectSt	-	-	-	-	0	1	-	Covered	T2,T18,T32
DetectSt	-	-	-	-	0	0	-	Covered	T2,T18,T32
StableSt	-	-	-	-	-	-	1	Covered	T2,T18,T32
StableSt	-	-	-	-	-	-	0	Covered	T2,T18,T32
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	3177	0	0
CntIncr_A	6427592	99950	0	0
CntNoWrap_A	6427592	5748416	0	0
DetectStDropOut_A	6427592	347	0	0
DetectedOut_A	6427592	70790	0	0
DetectedPulseOut_A	6427592	993	0	0
DisabledIdleSt_A	6427592	5343291	0	0
DisabledNoDetection_A	6427592	5345531	0	0
EnterDebounceSt_A	6427592	1598	0	0
EnterDetectSt_A	6427592	1579	0	0
EnterStableSt_A	6427592	993	0	0
PulseIsPulse_A	6427592	993	0	0
StayInStableSt	6427592	69690	0	0
gen_high_event_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	876	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3177	0	0
T2	33828	60	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	58	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	13	0	0
T19	503	0	0	0
T32	0	36	0	0
T42	0	34	0	0
T51	414	0	0	0
T55	0	36	0	0
T71	0	26	0	0
T72	0	40	0	0
T73	0	28	0	0
T74	0	42	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	99950	0	0
T2	33828	2070	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	1015	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	587	0	0
T19	503	0	0	0
T32	0	918	0	0
T42	0	1666	0	0
T51	414	0	0	0
T55	0	1257	0	0
T71	0	696	0	0
T72	0	1660	0	0
T73	0	578	0	0
T74	0	1785	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5748416	0	0
T1	17586	11530	0	0
T2	33828	33271	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	347	0	0
T42	21816	0	0	0
T46	720	0	0	0
T47	705	0	0	0
T71	5318	13	0	0
T72	19932	0	0	0
T73	4760	14	0	0
T75	0	1	0	0
T89	0	2	0	0
T93	0	23	0	0
T94	0	7	0	0
T95	0	12	0	0
T241	0	15	0	0
T242	0	5	0	0
T243	0	4	0	0
T244	402	0	0	0
T245	426	0	0	0
T246	422	0	0	0
T247	25472	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	70790	0	0
T2	33828	3085	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	2294	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	31	0	0
T19	503	0	0	0
T32	0	1551	0	0
T42	0	2221	0	0
T51	414	0	0	0
T72	0	1073	0	0
T74	0	345	0	0
T132	0	2034	0	0
T248	0	1960	0	0
T249	0	2074	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	993	0	0
T2	33828	30	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	29	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	3	0	0
T19	503	0	0	0
T32	0	18	0	0
T42	0	17	0	0
T51	414	0	0	0
T72	0	20	0	0
T74	0	21	0	0
T132	0	25	0	0
T248	0	11	0	0
T249	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5343291	0	0
T1	17586	11530	0	0
T2	33828	26326	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5345531	0	0
T1	17586	11549	0	0
T2	33828	26327	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1598	0	0
T2	33828	30	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	29	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	10	0	0
T19	503	0	0	0
T32	0	18	0	0
T42	0	17	0	0
T51	414	0	0	0
T55	0	18	0	0
T71	0	13	0	0
T72	0	20	0	0
T73	0	14	0	0
T74	0	21	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1579	0	0
T2	33828	30	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	29	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	3	0	0
T19	503	0	0	0
T32	0	18	0	0
T42	0	17	0	0
T51	414	0	0	0
T55	0	18	0	0
T71	0	13	0	0
T72	0	20	0	0
T73	0	14	0	0
T74	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	993	0	0
T2	33828	30	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	29	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	3	0	0
T19	503	0	0	0
T32	0	18	0	0
T42	0	17	0	0
T51	414	0	0	0
T72	0	20	0	0
T74	0	21	0	0
T132	0	25	0	0
T248	0	11	0	0
T249	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	993	0	0
T2	33828	30	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	29	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	3	0	0
T19	503	0	0	0
T32	0	18	0	0
T42	0	17	0	0
T51	414	0	0	0
T72	0	20	0	0
T74	0	21	0	0
T132	0	25	0	0
T248	0	11	0	0
T249	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	69690	0	0
T2	33828	3044	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	2257	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	28	0	0
T19	503	0	0	0
T32	0	1530	0	0
T42	0	2200	0	0
T51	414	0	0	0
T72	0	1052	0	0
T74	0	324	0	0
T132	0	2009	0	0
T248	0	1943	0	0
T249	0	2055	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	876	0	0
T2	33828	19	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	21	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	3	0	0
T19	503	0	0	0
T32	0	15	0	0
T42	0	13	0	0
T51	414	0	0	0
T72	0	19	0	0
T74	0	21	0	0
T132	0	25	0	0
T248	0	5	0	0
T249	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T1,T2,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T78,T90,T92
1	0	Covered	T75,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T80,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T4
1	-	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T4
DetectSt	168	Covered	T1,T2,T4
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T4
DebounceSt->IdleSt	163	Covered	T4,T43,T11
DetectSt->IdleSt	186	Covered	T78,T90,T92
DetectSt->StableSt	191	Covered	T1,T2,T4
IdleSt->DebounceSt	148	Covered	T1,T2,T4
StableSt->IdleSt	206	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T43,T11
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T4
DetectSt	-	-	-	-	1	-	-	Covered	T78,T90,T92
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	1061	0	0
CntIncr_A	6427592	52329	0	0
CntNoWrap_A	6427592	5750532	0	0
DetectStDropOut_A	6427592	68	0	0
DetectedOut_A	6427592	18643	0	0
DetectedPulseOut_A	6427592	414	0	0
DisabledIdleSt_A	6427592	5345564	0	0
DisabledNoDetection_A	6427592	5347233	0	0
EnterDebounceSt_A	6427592	577	0	0
EnterDetectSt_A	6427592	486	0	0
EnterStableSt_A	6427592	414	0	0
PulseIsPulse_A	6427592	414	0	0
StayInStableSt	6427592	18192	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	373	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1061	0	0
T1	17586	8	0	0
T2	33828	20	0	0
T3	927	0	0	0
T4	0	9	0	0
T7	0	6	0	0
T8	0	2	0	0
T9	0	2	0	0
T10	0	8	0	0
T11	0	13	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	0	6	0	0
T43	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	52329	0	0
T1	17586	337	0	0
T2	33828	810	0	0
T3	927	0	0	0
T4	0	515	0	0
T7	0	315	0	0
T8	0	146	0	0
T9	0	25	0	0
T10	0	676	0	0
T11	0	618	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	0	237	0	0
T43	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5750532	0	0
T1	17586	11522	0	0
T2	33828	33311	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	68	0	0
T56	745	0	0	0
T57	746	0	0	0
T78	17668	1	0	0
T82	764	0	0	0
T90	25841	2	0	0
T92	0	2	0	0
T96	0	2	0	0
T97	0	6	0	0
T98	0	6	0	0
T99	0	1	0	0
T100	0	3	0	0
T101	0	12	0	0
T103	0	9	0	0
T104	1326	0	0	0
T105	422	0	0	0
T106	2820	0	0	0
T107	407	0	0	0
T108	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	18643	0	0
T1	17586	199	0	0
T2	33828	378	0	0
T3	927	0	0	0
T4	0	189	0	0
T7	0	28	0	0
T8	0	90	0	0
T9	0	3	0	0
T10	0	45	0	0
T11	0	498	0	0
T12	0	271	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	414	0	0
T1	17586	4	0	0
T2	33828	10	0	0
T3	927	0	0	0
T4	0	4	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	8	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5345564	0	0
T1	17586	9881	0	0
T2	33828	30257	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5347233	0	0
T1	17586	9896	0	0
T2	33828	30259	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	577	0	0
T1	17586	4	0	0
T2	33828	10	0	0
T3	927	0	0	0
T4	0	5	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	7	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	0	3	0	0
T43	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	486	0	0
T1	17586	4	0	0
T2	33828	10	0	0
T3	927	0	0	0
T4	0	4	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	8	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	414	0	0
T1	17586	4	0	0
T2	33828	10	0	0
T3	927	0	0	0
T4	0	4	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	8	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	414	0	0
T1	17586	4	0	0
T2	33828	10	0	0
T3	927	0	0	0
T4	0	4	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	8	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	18192	0	0
T1	17586	195	0	0
T2	33828	368	0	0
T3	927	0	0	0
T4	0	185	0	0
T7	0	25	0	0
T8	0	89	0	0
T9	0	2	0	0
T10	0	41	0	0
T11	0	492	0	0
T12	0	257	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T32	0	84	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	373	0	0
T1	17586	4	0	0
T2	33828	10	0	0
T3	927	0	0	0
T4	0	4	0	0
T7	0	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	4	0	0
T11	0	6	0	0
T12	0	2	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T18,T32
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T32
1	0	Covered	T2,T32,T12
1	1	Covered	T2,T18,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T32
0	1	Covered	T32,T55,T71
1	0	Covered	T32,T55,T248

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T42
0	1	Covered	T2,T18,T12
1	0	Covered	T84,T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T12,T42
1	-	Covered	T2,T18,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T18,T32
DetectSt	168	Covered	T2,T18,T32
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T2,T18,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T18,T32
DebounceSt->IdleSt	163	Covered	T18,T75,T240
DetectSt->IdleSt	186	Covered	T32,T55,T71
DetectSt->StableSt	191	Covered	T2,T18,T12
IdleSt->DebounceSt	148	Covered	T2,T18,T32
StableSt->IdleSt	206	Covered	T2,T18,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T18,T32
0	1	Covered	T2,T18,T32
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T18,T32
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T18,T32
IdleSt	0	-	-	-	-	-	-	Covered	T2,T18,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T18,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T75,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T18,T32
DetectSt	-	-	-	-	1	-	-	Covered	T32,T55,T71
DetectSt	-	-	-	-	0	1	-	Covered	T2,T18,T12
DetectSt	-	-	-	-	0	0	-	Covered	T2,T18,T32
StableSt	-	-	-	-	-	-	1	Covered	T2,T18,T12
StableSt	-	-	-	-	-	-	0	Covered	T2,T12,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	2945	0	0
CntIncr_A	6427592	93666	0	0
CntNoWrap_A	6427592	5748648	0	0
DetectStDropOut_A	6427592	336	0	0
DetectedOut_A	6427592	62347	0	0
DetectedPulseOut_A	6427592	853	0	0
DisabledIdleSt_A	6427592	5353444	0	0
DisabledNoDetection_A	6427592	5355710	0	0
EnterDebounceSt_A	6427592	1480	0	0
EnterDetectSt_A	6427592	1466	0	0
EnterStableSt_A	6427592	853	0	0
PulseIsPulse_A	6427592	853	0	0
StayInStableSt	6427592	61414	0	0
gen_high_event_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	755	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	2945	0	0
T2	33828	32	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	32	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	5	0	0
T19	503	0	0	0
T32	0	52	0	0
T42	0	22	0	0
T51	414	0	0	0
T55	0	32	0	0
T71	0	38	0	0
T72	0	64	0	0
T73	0	50	0	0
T74	0	20	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	93666	0	0
T2	33828	720	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	864	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	239	0	0
T19	503	0	0	0
T32	0	1362	0	0
T42	0	836	0	0
T51	414	0	0	0
T55	0	1108	0	0
T71	0	1025	0	0
T72	0	2016	0	0
T73	0	1049	0	0
T74	0	650	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5748648	0	0
T1	17586	11530	0	0
T2	33828	33299	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	336	0	0
T7	18382	0	0	0
T8	13249	0	0	0
T28	492	0	0	0
T29	492	0	0	0
T30	505	0	0	0
T32	12832	19	0	0
T43	3322	0	0	0
T55	0	6	0	0
T61	491	0	0	0
T66	523	0	0	0
T67	505	0	0	0
T71	0	19	0	0
T73	0	25	0	0
T75	0	1	0	0
T89	0	3	0	0
T93	0	12	0	0
T95	0	7	0	0
T241	0	11	0	0
T248	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	62347	0	0
T2	33828	1871	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	726	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T42	0	2237	0	0
T51	414	0	0	0
T72	0	4937	0	0
T74	0	432	0	0
T94	0	701	0	0
T132	0	1495	0	0
T249	0	309	0	0
T250	0	4496	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	853	0	0
T2	33828	16	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	16	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T42	0	11	0	0
T51	414	0	0	0
T72	0	32	0	0
T74	0	10	0	0
T94	0	12	0	0
T132	0	27	0	0
T249	0	5	0	0
T250	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5353444	0	0
T1	17586	11530	0	0
T2	33828	27742	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5355710	0	0
T1	17586	11549	0	0
T2	33828	27749	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1480	0	0
T2	33828	16	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	16	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	4	0	0
T19	503	0	0	0
T32	0	26	0	0
T42	0	11	0	0
T51	414	0	0	0
T55	0	16	0	0
T71	0	19	0	0
T72	0	32	0	0
T73	0	25	0	0
T74	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1466	0	0
T2	33828	16	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	16	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T32	0	26	0	0
T42	0	11	0	0
T51	414	0	0	0
T55	0	16	0	0
T71	0	19	0	0
T72	0	32	0	0
T73	0	25	0	0
T74	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	853	0	0
T2	33828	16	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	16	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T42	0	11	0	0
T51	414	0	0	0
T72	0	32	0	0
T74	0	10	0	0
T94	0	12	0	0
T132	0	27	0	0
T249	0	5	0	0
T250	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	853	0	0
T2	33828	16	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	16	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T42	0	11	0	0
T51	414	0	0	0
T72	0	32	0	0
T74	0	10	0	0
T94	0	12	0	0
T132	0	27	0	0
T249	0	5	0	0
T250	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	61414	0	0
T2	33828	1850	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	708	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T42	0	2223	0	0
T51	414	0	0	0
T72	0	4901	0	0
T74	0	422	0	0
T80	0	893	0	0
T94	0	687	0	0
T132	0	1468	0	0
T249	0	303	0	0
T250	0	4471	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	755	0	0
T2	33828	11	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	14	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T42	0	8	0	0
T51	414	0	0	0
T72	0	28	0	0
T74	0	10	0	0
T94	0	10	0	0
T132	0	27	0	0
T249	0	4	0	0
T250	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T7,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T1,T7,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T7,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T7,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T10
0	1	Covered	T27,T98,T174
1	0	Covered	T75,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T10
0	1	Covered	T1,T7,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T10
1	-	Covered	T1,T7,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T10
DetectSt	168	Covered	T1,T7,T10
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T1,T7,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T10
DebounceSt->IdleSt	163	Covered	T7,T27,T78
DetectSt->IdleSt	186	Covered	T27,T75,T98
DetectSt->StableSt	191	Covered	T1,T7,T10
IdleSt->DebounceSt	148	Covered	T1,T7,T10
StableSt->IdleSt	206	Covered	T1,T7,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T10
0	1	Covered	T1,T7,T10
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T10
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T78,T251
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T10
DetectSt	-	-	-	-	1	-	-	Covered	T27,T75,T98
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	758	0	0
CntIncr_A	6427592	39947	0	0
CntNoWrap_A	6427592	5750835	0	0
DetectStDropOut_A	6427592	47	0	0
DetectedOut_A	6427592	14871	0	0
DetectedPulseOut_A	6427592	308	0	0
DisabledIdleSt_A	6427592	5341259	0	0
DisabledNoDetection_A	6427592	5343013	0	0
EnterDebounceSt_A	6427592	403	0	0
EnterDetectSt_A	6427592	359	0	0
EnterStableSt_A	6427592	308	0	0
PulseIsPulse_A	6427592	308	0	0
StayInStableSt	6427592	14543	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	286	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	758	0	0
T1	17586	2	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	13	0	0
T10	0	6	0	0
T11	0	8	0	0
T12	0	6	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	4	0	0
T42	0	4	0	0
T45	0	2	0	0
T72	0	8	0	0
T211	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	39947	0	0
T1	17586	164	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	469	0	0
T10	0	351	0	0
T11	0	464	0	0
T12	0	174	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	280	0	0
T42	0	150	0	0
T45	0	121	0	0
T72	0	284	0	0
T211	0	612	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5750835	0	0
T1	17586	11528	0	0
T2	33828	33331	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	47	0	0
T27	8792	2	0	0
T38	55140	0	0	0
T39	837	0	0	0
T49	687	0	0	0
T65	1917	0	0	0
T74	8598	0	0	0
T77	406	0	0	0
T98	0	3	0	0
T101	0	3	0	0
T113	522	0	0	0
T174	0	1	0	0
T190	428	0	0	0
T191	421	0	0	0
T238	0	4	0	0
T252	0	5	0	0
T253	0	1	0	0
T254	0	3	0	0
T255	0	3	0	0
T256	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	14871	0	0
T1	17586	4	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	264	0	0
T10	0	190	0	0
T11	0	226	0	0
T12	0	117	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	74	0	0
T42	0	160	0	0
T45	0	5	0	0
T72	0	531	0	0
T211	0	225	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	308	0	0
T1	17586	1	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	6	0	0
T10	0	3	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T72	0	4	0	0
T211	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5341259	0	0
T1	17586	9959	0	0
T2	33828	31465	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5343013	0	0
T1	17586	9975	0	0
T2	33828	31473	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	403	0	0
T1	17586	1	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	7	0	0
T10	0	3	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T72	0	4	0	0
T211	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	359	0	0
T1	17586	1	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	6	0	0
T10	0	3	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T72	0	4	0	0
T211	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	308	0	0
T1	17586	1	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	6	0	0
T10	0	3	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T72	0	4	0	0
T211	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	308	0	0
T1	17586	1	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	6	0	0
T10	0	3	0	0
T11	0	4	0	0
T12	0	3	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T72	0	4	0	0
T211	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	14543	0	0
T1	17586	3	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	258	0	0
T10	0	187	0	0
T11	0	222	0	0
T12	0	112	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	72	0	0
T42	0	158	0	0
T45	0	4	0	0
T72	0	527	0	0
T211	0	222	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	286	0	0
T1	17586	1	0	0
T2	33828	0	0	0
T3	927	0	0	0
T7	0	6	0	0
T10	0	3	0	0
T11	0	4	0	0
T12	0	1	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T72	0	4	0	0
T211	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T18,T32
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T32
1	0	Covered	T2,T32,T12
1	1	Covered	T2,T18,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T32
0	1	Covered	T55,T71,T73
1	0	Covered	T32,T12,T55

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T42
0	1	Covered	T2,T18,T42
1	0	Covered	T75,T257,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T18,T42
1	-	Covered	T2,T18,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T18,T32
DetectSt	168	Covered	T2,T18,T32
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T2,T18,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T18,T32
DebounceSt->IdleSt	163	Covered	T18,T75,T240
DetectSt->IdleSt	186	Covered	T32,T12,T55
DetectSt->StableSt	191	Covered	T2,T18,T42
IdleSt->DebounceSt	148	Covered	T2,T18,T32
StableSt->IdleSt	206	Covered	T2,T18,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T18,T32
0	1	Covered	T2,T18,T32
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T18,T32
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T18,T32
IdleSt	0	-	-	-	-	-	-	Covered	T2,T18,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T18,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T75,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T18,T32
DetectSt	-	-	-	-	1	-	-	Covered	T32,T12,T55
DetectSt	-	-	-	-	0	1	-	Covered	T2,T18,T42
DetectSt	-	-	-	-	0	0	-	Covered	T2,T18,T32
StableSt	-	-	-	-	-	-	1	Covered	T2,T18,T42
StableSt	-	-	-	-	-	-	0	Covered	T2,T18,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	3168	0	0
CntIncr_A	6427592	95998	0	0
CntNoWrap_A	6427592	5748425	0	0
DetectStDropOut_A	6427592	334	0	0
DetectedOut_A	6427592	79940	0	0
DetectedPulseOut_A	6427592	1017	0	0
DisabledIdleSt_A	6427592	5338344	0	0
DisabledNoDetection_A	6427592	5340586	0	0
EnterDebounceSt_A	6427592	1592	0	0
EnterDetectSt_A	6427592	1576	0	0
EnterStableSt_A	6427592	1017	0	0
PulseIsPulse_A	6427592	1017	0	0
StayInStableSt	6427592	78819	0	0
gen_high_event_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	902	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3168	0	0
T2	33828	34	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	10	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	4	0	0
T19	503	0	0	0
T32	0	14	0	0
T42	0	22	0	0
T51	414	0	0	0
T55	0	18	0	0
T71	0	40	0	0
T72	0	8	0	0
T73	0	52	0	0
T74	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	95998	0	0
T2	33828	1224	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	298	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	162	0	0
T19	503	0	0	0
T32	0	371	0	0
T42	0	957	0	0
T51	414	0	0	0
T55	0	620	0	0
T71	0	1080	0	0
T72	0	332	0	0
T73	0	1091	0	0
T74	0	1650	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5748425	0	0
T1	17586	11530	0	0
T2	33828	33297	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	334	0	0
T42	21816	0	0	0
T44	728	0	0	0
T45	15916	0	0	0
T55	9976	4	0	0
T64	490	0	0	0
T71	5318	20	0	0
T73	0	26	0	0
T89	0	2	0	0
T93	0	10	0	0
T95	0	2	0	0
T209	522	0	0	0
T210	502	0	0	0
T211	21574	0	0	0
T241	0	16	0	0
T243	0	12	0	0
T248	0	6	0	0
T258	0	10	0	0
T259	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	79940	0	0
T2	33828	1447	0	0
T3	927	0	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	27	0	0
T19	503	0	0	0
T42	0	2116	0	0
T51	414	0	0	0
T72	0	383	0	0
T74	0	1843	0	0
T80	0	2053	0	0
T94	0	1797	0	0
T132	0	2769	0	0
T249	0	507	0	0
T250	0	4181	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1017	0	0
T2	33828	17	0	0
T3	927	0	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T42	0	11	0	0
T51	414	0	0	0
T72	0	4	0	0
T74	0	25	0	0
T80	0	21	0	0
T94	0	14	0	0
T132	0	24	0	0
T249	0	9	0	0
T250	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5338344	0	0
T1	17586	11530	0	0
T2	33828	27743	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5340586	0	0
T1	17586	11549	0	0
T2	33828	27750	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1592	0	0
T2	33828	17	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	5	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	3	0	0
T19	503	0	0	0
T32	0	7	0	0
T42	0	11	0	0
T51	414	0	0	0
T55	0	9	0	0
T71	0	20	0	0
T72	0	4	0	0
T73	0	26	0	0
T74	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1576	0	0
T2	33828	17	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	5	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T32	0	7	0	0
T42	0	11	0	0
T51	414	0	0	0
T55	0	9	0	0
T71	0	20	0	0
T72	0	4	0	0
T73	0	26	0	0
T74	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1017	0	0
T2	33828	17	0	0
T3	927	0	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T42	0	11	0	0
T51	414	0	0	0
T72	0	4	0	0
T74	0	25	0	0
T80	0	21	0	0
T94	0	14	0	0
T132	0	24	0	0
T249	0	9	0	0
T250	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1017	0	0
T2	33828	17	0	0
T3	927	0	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T42	0	11	0	0
T51	414	0	0	0
T72	0	4	0	0
T74	0	25	0	0
T80	0	21	0	0
T94	0	14	0	0
T132	0	24	0	0
T249	0	9	0	0
T250	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	78819	0	0
T2	33828	1425	0	0
T3	927	0	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	26	0	0
T19	503	0	0	0
T42	0	2102	0	0
T51	414	0	0	0
T72	0	378	0	0
T74	0	1818	0	0
T80	0	2028	0	0
T94	0	1780	0	0
T132	0	2744	0	0
T249	0	496	0	0
T250	0	4156	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	902	0	0
T2	33828	12	0	0
T3	927	0	0	0
T4	14720	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	1	0	0
T19	503	0	0	0
T42	0	8	0	0
T51	414	0	0	0
T72	0	3	0	0
T74	0	25	0	0
T80	0	17	0	0
T94	0	11	0	0
T132	0	23	0	0
T249	0	7	0	0
T250	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T1,T2,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T27,T78
1	0	Covered	T75,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T7
0	1	Covered	T2,T4,T7
1	0	Covered	T75,T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T4,T7
1	-	Covered	T2,T4,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T4
DetectSt	168	Covered	T1,T2,T4
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T2,T4,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T4
DebounceSt->IdleSt	163	Covered	T1,T11,T211
DetectSt->IdleSt	186	Covered	T1,T27,T78
DetectSt->StableSt	191	Covered	T2,T4,T7
IdleSt->DebounceSt	148	Covered	T1,T2,T4
StableSt->IdleSt	206	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T11,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T4
DetectSt	-	-	-	-	1	-	-	Covered	T1,T27,T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T4,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T4,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	1001	0	0
CntIncr_A	6427592	56679	0	0
CntNoWrap_A	6427592	5750592	0	0
DetectStDropOut_A	6427592	63	0	0
DetectedOut_A	6427592	19349	0	0
DetectedPulseOut_A	6427592	408	0	0
DisabledIdleSt_A	6427592	5335445	0	0
DisabledNoDetection_A	6427592	5337186	0	0
EnterDebounceSt_A	6427592	528	0	0
EnterDetectSt_A	6427592	476	0	0
EnterStableSt_A	6427592	408	0	0
PulseIsPulse_A	6427592	408	0	0
StayInStableSt	6427592	18904	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	368	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1001	0	0
T1	17586	6	0	0
T2	33828	8	0	0
T3	927	0	0	0
T4	0	4	0	0
T7	0	2	0	0
T8	0	4	0	0
T10	0	6	0	0
T11	0	23	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	4	0	0
T211	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	56679	0	0
T1	17586	496	0	0
T2	33828	308	0	0
T3	927	0	0	0
T4	0	184	0	0
T7	0	66	0	0
T8	0	460	0	0
T10	0	345	0	0
T11	0	1519	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	150	0	0
T42	0	122	0	0
T211	0	1466	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5750592	0	0
T1	17586	11524	0	0
T2	33828	33323	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	63	0	0
T1	17586	2	0	0
T2	33828	0	0	0
T3	927	0	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T27	0	2	0	0
T75	0	1	0	0
T78	0	1	0	0
T99	0	2	0	0
T110	0	7	0	0
T143	0	1	0	0
T223	0	2	0	0
T260	0	14	0	0
T261	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	19349	0	0
T2	33828	166	0	0
T3	927	0	0	0
T4	14720	132	0	0
T7	0	48	0	0
T8	0	14	0	0
T10	0	195	0	0
T11	0	467	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	27	0	0
T42	0	188	0	0
T51	414	0	0	0
T72	0	119	0	0
T211	0	339	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	408	0	0
T2	33828	4	0	0
T3	927	0	0	0
T4	14720	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T10	0	3	0	0
T11	0	11	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	1	0	0
T42	0	2	0	0
T51	414	0	0	0
T72	0	1	0	0
T211	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5335445	0	0
T1	17586	9959	0	0
T2	33828	31889	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5337186	0	0
T1	17586	9975	0	0
T2	33828	31897	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	528	0	0
T1	17586	4	0	0
T2	33828	4	0	0
T3	927	0	0	0
T4	0	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T10	0	3	0	0
T11	0	12	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	1	0	0
T42	0	2	0	0
T211	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	476	0	0
T1	17586	2	0	0
T2	33828	4	0	0
T3	927	0	0	0
T4	0	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T10	0	3	0	0
T11	0	11	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	1	0	0
T42	0	2	0	0
T211	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	408	0	0
T2	33828	4	0	0
T3	927	0	0	0
T4	14720	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T10	0	3	0	0
T11	0	11	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	1	0	0
T42	0	2	0	0
T51	414	0	0	0
T72	0	1	0	0
T211	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	408	0	0
T2	33828	4	0	0
T3	927	0	0	0
T4	14720	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T10	0	3	0	0
T11	0	11	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	1	0	0
T42	0	2	0	0
T51	414	0	0	0
T72	0	1	0	0
T211	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	18904	0	0
T2	33828	162	0	0
T3	927	0	0	0
T4	14720	130	0	0
T7	0	47	0	0
T8	0	12	0	0
T10	0	192	0	0
T11	0	456	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	26	0	0
T42	0	186	0	0
T51	414	0	0	0
T72	0	118	0	0
T211	0	333	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	368	0	0
T2	33828	4	0	0
T3	927	0	0	0
T4	14720	2	0	0
T7	0	1	0	0
T8	0	2	0	0
T10	0	3	0	0
T11	0	11	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	1	0	0
T42	0	2	0	0
T51	414	0	0	0
T72	0	1	0	0
T211	0	6	0	0