Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T18,T32
1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T2,T18,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T18,T32
1	0	Covered	T2,T32,T12
1	1	Covered	T2,T18,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T32
0	1	Covered	T71,T72,T73
1	0	Covered	T32,T72,T248

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T18,T12
0	1	Covered	T2,T18,T12
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T18,T12
1	-	Covered	T2,T18,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T18,T32
DetectSt	168	Covered	T2,T18,T32
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T2,T18,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T18,T32
DebounceSt->IdleSt	163	Covered	T18,T75,T240
DetectSt->IdleSt	186	Covered	T32,T71,T72
DetectSt->StableSt	191	Covered	T2,T18,T12
IdleSt->DebounceSt	148	Covered	T2,T18,T32
StableSt->IdleSt	206	Covered	T2,T18,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T18,T32
0	1	Covered	T2,T18,T32
0	0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T18,T32
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T18,T32
IdleSt	0	-	-	-	-	-	-	Covered	T2,T18,T32
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T18,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T75,T240
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T18,T32
DetectSt	-	-	-	-	1	-	-	Covered	T32,T71,T72
DetectSt	-	-	-	-	0	1	-	Covered	T2,T18,T12
DetectSt	-	-	-	-	0	0	-	Covered	T2,T18,T32
StableSt	-	-	-	-	-	-	1	Covered	T2,T18,T12
StableSt	-	-	-	-	-	-	0	Covered	T2,T18,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	3021	0	0
CntIncr_A	6427592	92183	0	0
CntNoWrap_A	6427592	5748572	0	0
DetectStDropOut_A	6427592	317	0	0
DetectedOut_A	6427592	73820	0	0
DetectedPulseOut_A	6427592	964	0	0
DisabledIdleSt_A	6427592	5342495	0	0
DisabledNoDetection_A	6427592	5344753	0	0
EnterDebounceSt_A	6427592	1520	0	0
EnterDetectSt_A	6427592	1502	0	0
EnterStableSt_A	6427592	964	0	0
PulseIsPulse_A	6427592	964	0	0
StayInStableSt	6427592	72768	0	0
gen_high_event_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	875	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	3021	0	0
T2	33828	26	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	22	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	15	0	0
T19	503	0	0	0
T32	0	36	0	0
T42	0	14	0	0
T51	414	0	0	0
T55	0	60	0	0
T71	0	2	0	0
T72	0	50	0	0
T73	0	54	0	0
T74	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	92183	0	0
T2	33828	1040	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	550	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	598	0	0
T19	503	0	0	0
T32	0	961	0	0
T42	0	553	0	0
T51	414	0	0	0
T55	0	1800	0	0
T71	0	53	0	0
T72	0	3102	0	0
T73	0	1136	0	0
T74	0	882	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5748572	0	0
T1	17586	11530	0	0
T2	33828	33305	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	317	0	0
T42	21816	0	0	0
T46	720	0	0	0
T47	705	0	0	0
T71	5318	1	0	0
T72	19932	5	0	0
T73	4760	27	0	0
T75	0	1	0	0
T89	0	24	0	0
T93	0	3	0	0
T94	0	4	0	0
T95	0	4	0	0
T241	0	11	0	0
T244	402	0	0	0
T245	426	0	0	0
T246	422	0	0	0
T247	25472	0	0	0
T248	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	73820	0	0
T2	33828	1047	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	642	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	109	0	0
T19	503	0	0	0
T42	0	717	0	0
T51	414	0	0	0
T55	0	2138	0	0
T74	0	576	0	0
T80	0	541	0	0
T132	0	202	0	0
T249	0	2174	0	0
T250	0	2043	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	964	0	0
T2	33828	13	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	11	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	4	0	0
T19	503	0	0	0
T42	0	7	0	0
T51	414	0	0	0
T55	0	30	0	0
T74	0	14	0	0
T80	0	9	0	0
T132	0	3	0	0
T249	0	14	0	0
T250	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5342495	0	0
T1	17586	11530	0	0
T2	33828	28001	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5344753	0	0
T1	17586	11549	0	0
T2	33828	28009	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1520	0	0
T2	33828	13	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	11	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	11	0	0
T19	503	0	0	0
T32	0	18	0	0
T42	0	7	0	0
T51	414	0	0	0
T55	0	30	0	0
T71	0	1	0	0
T72	0	25	0	0
T73	0	27	0	0
T74	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	1502	0	0
T2	33828	13	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	11	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	4	0	0
T19	503	0	0	0
T32	0	18	0	0
T42	0	7	0	0
T51	414	0	0	0
T55	0	30	0	0
T71	0	1	0	0
T72	0	25	0	0
T73	0	27	0	0
T74	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	964	0	0
T2	33828	13	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	11	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	4	0	0
T19	503	0	0	0
T42	0	7	0	0
T51	414	0	0	0
T55	0	30	0	0
T74	0	14	0	0
T80	0	9	0	0
T132	0	3	0	0
T249	0	14	0	0
T250	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	964	0	0
T2	33828	13	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	11	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	4	0	0
T19	503	0	0	0
T42	0	7	0	0
T51	414	0	0	0
T55	0	30	0	0
T74	0	14	0	0
T80	0	9	0	0
T132	0	3	0	0
T249	0	14	0	0
T250	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	72768	0	0
T2	33828	1030	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	628	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	105	0	0
T19	503	0	0	0
T42	0	708	0	0
T51	414	0	0	0
T55	0	2107	0	0
T74	0	562	0	0
T80	0	532	0	0
T132	0	199	0	0
T249	0	2160	0	0
T250	0	2014	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	875	0	0
T2	33828	9	0	0
T3	927	0	0	0
T4	14720	0	0	0
T12	0	8	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	4	0	0
T19	503	0	0	0
T42	0	5	0	0
T51	414	0	0	0
T55	0	29	0	0
T74	0	14	0	0
T80	0	9	0	0
T132	0	3	0	0
T249	0	14	0	0
T250	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T18
1	Covered	T5,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T1	VC_COV_UNR
1	Covered	T1,T2,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T1
1	Covered	T1,T2,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T7
0	1	Covered	T7,T10,T136
1	0	Covered	T75,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T8
1	-	Covered	T1,T2,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T7
DetectSt	168	Covered	T1,T2,T7
IdleSt	163	Covered	T5,T6,T1
StableSt	191	Covered	T1,T2,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T7
DebounceSt->IdleSt	163	Covered	T10,T11,T55
DetectSt->IdleSt	186	Covered	T7,T10,T75
DetectSt->StableSt	191	Covered	T1,T2,T8
IdleSt->DebounceSt	148	Covered	T1,T2,T7
StableSt->IdleSt	206	Covered	T1,T2,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T2,T7
0	0	Excluded	T5,T6,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T75,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T11,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T10,T75
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6427592	904	0	0
CntIncr_A	6427592	48931	0	0
CntNoWrap_A	6427592	5750689	0	0
DetectStDropOut_A	6427592	57	0	0
DetectedOut_A	6427592	15890	0	0
DetectedPulseOut_A	6427592	367	0	0
DisabledIdleSt_A	6427592	5341450	0	0
DisabledNoDetection_A	6427592	5343204	0	0
EnterDebounceSt_A	6427592	477	0	0
EnterDetectSt_A	6427592	430	0	0
EnterStableSt_A	6427592	367	0	0
PulseIsPulse_A	6427592	367	0	0
StayInStableSt	6427592	15494	0	0
gen_high_level_sva.HighLevelEvent_A	6427592	5754030	0	0
gen_not_sticky_sva.StableStDropOut_A	6427592	336	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	904	0	0
T1	17586	2	0	0
T2	33828	4	0	0
T3	927	0	0	0
T7	0	4	0	0
T8	0	2	0	0
T10	0	17	0	0
T11	0	11	0	0
T12	0	4	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	4	0	0
T55	0	4	0	0
T211	0	9	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	48931	0	0
T1	17586	102	0	0
T2	33828	152	0	0
T3	927	0	0	0
T7	0	228	0	0
T8	0	177	0	0
T10	0	1538	0	0
T11	0	898	0	0
T12	0	94	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	346	0	0
T55	0	192	0	0
T211	0	1024	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5750689	0	0
T1	17586	11528	0	0
T2	33828	33327	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	57	0	0
T7	18382	2	0	0
T8	13249	0	0	0
T9	1569	0	0	0
T10	12980	8	0	0
T61	491	0	0	0
T66	523	0	0	0
T67	505	0	0	0
T68	521	0	0	0
T69	506	0	0	0
T97	0	12	0	0
T134	0	2	0	0
T136	0	2	0	0
T162	425	0	0	0
T261	0	6	0	0
T262	0	7	0	0
T263	0	4	0	0
T264	0	1	0	0
T265	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	15890	0	0
T1	17586	66	0	0
T2	33828	84	0	0
T3	927	0	0	0
T8	0	59	0	0
T11	0	44	0	0
T12	0	101	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	8	0	0
T42	0	58	0	0
T55	0	67	0	0
T211	0	220	0	0
T247	0	30	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	367	0	0
T1	17586	1	0	0
T2	33828	2	0	0
T3	927	0	0	0
T8	0	1	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T55	0	1	0	0
T211	0	4	0	0
T247	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5341450	0	0
T1	17586	9959	0	0
T2	33828	32288	0	0
T3	927	526	0	0
T5	426	25	0	0
T6	735	334	0	0
T13	404	3	0	0
T14	516	115	0	0
T15	405	4	0	0
T16	405	4	0	0
T17	694	293	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5343204	0	0
T1	17586	9975	0	0
T2	33828	32297	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	477	0	0
T1	17586	1	0	0
T2	33828	2	0	0
T3	927	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T10	0	9	0	0
T11	0	6	0	0
T12	0	2	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T55	0	3	0	0
T211	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	430	0	0
T1	17586	1	0	0
T2	33828	2	0	0
T3	927	0	0	0
T7	0	2	0	0
T8	0	1	0	0
T10	0	8	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T55	0	1	0	0
T211	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	367	0	0
T1	17586	1	0	0
T2	33828	2	0	0
T3	927	0	0	0
T8	0	1	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T55	0	1	0	0
T211	0	4	0	0
T247	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	367	0	0
T1	17586	1	0	0
T2	33828	2	0	0
T3	927	0	0	0
T8	0	1	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T55	0	1	0	0
T211	0	4	0	0
T247	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	15494	0	0
T1	17586	65	0	0
T2	33828	82	0	0
T3	927	0	0	0
T8	0	58	0	0
T11	0	39	0	0
T12	0	99	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	6	0	0
T42	0	57	0	0
T55	0	66	0	0
T211	0	216	0	0
T247	0	26	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	5754030	0	0
T1	17586	11549	0	0
T2	33828	33344	0	0
T3	927	527	0	0
T5	426	26	0	0
T6	735	335	0	0
T13	404	4	0	0
T14	516	116	0	0
T15	405	5	0	0
T16	405	5	0	0
T17	694	294	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6427592	336	0	0
T1	17586	1	0	0
T2	33828	2	0	0
T3	927	0	0	0
T8	0	1	0	0
T11	0	5	0	0
T12	0	2	0	0
T13	404	0	0	0
T14	516	0	0	0
T15	405	0	0	0
T16	405	0	0	0
T17	694	0	0	0
T18	4773	0	0	0
T19	503	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T55	0	1	0	0
T211	0	4	0	0
T247	0	4	0	0