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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.98 99.40 96.51 100.00 98.08 98.85 99.61 93.44


Total test records in report: 915
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T360 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2192877182 Mar 14 01:29:51 PM PDT 24 Mar 14 01:32:21 PM PDT 24 55813157837 ps
T456 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.4207439871 Mar 14 01:28:05 PM PDT 24 Mar 14 01:28:54 PM PDT 24 110590923077 ps
T97 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.2178029525 Mar 14 01:29:13 PM PDT 24 Mar 14 01:31:33 PM PDT 24 106680811657 ps
T184 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3730051167 Mar 14 01:29:12 PM PDT 24 Mar 14 01:29:18 PM PDT 24 3363093566 ps
T457 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3801005114 Mar 14 01:28:56 PM PDT 24 Mar 14 01:30:52 PM PDT 24 92826316609 ps
T458 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3110619240 Mar 14 01:28:19 PM PDT 24 Mar 14 01:28:22 PM PDT 24 2638667746 ps
T459 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2967399629 Mar 14 01:28:06 PM PDT 24 Mar 14 01:28:09 PM PDT 24 2627294308 ps
T460 /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1282802644 Mar 14 01:29:38 PM PDT 24 Mar 14 01:29:39 PM PDT 24 3177993942 ps
T258 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.628081241 Mar 14 01:30:04 PM PDT 24 Mar 14 01:30:55 PM PDT 24 35063715657 ps
T461 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2170707272 Mar 14 01:29:40 PM PDT 24 Mar 14 01:29:43 PM PDT 24 2527180812 ps
T462 /workspace/coverage/default/0.sysrst_ctrl_stress_all.3046732074 Mar 14 01:27:55 PM PDT 24 Mar 14 01:28:02 PM PDT 24 7074380816 ps
T379 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.4237887730 Mar 14 01:30:02 PM PDT 24 Mar 14 01:30:28 PM PDT 24 62767848457 ps
T323 /workspace/coverage/default/10.sysrst_ctrl_stress_all.197251681 Mar 14 01:28:16 PM PDT 24 Mar 14 01:28:22 PM PDT 24 8246212961 ps
T463 /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2223182914 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:51 PM PDT 24 3300346967 ps
T137 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.4154874209 Mar 14 01:29:50 PM PDT 24 Mar 14 01:29:57 PM PDT 24 3545236228 ps
T464 /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1985896148 Mar 14 01:29:39 PM PDT 24 Mar 14 01:30:13 PM PDT 24 18441584266 ps
T122 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2162080555 Mar 14 01:28:19 PM PDT 24 Mar 14 01:28:29 PM PDT 24 9900272009 ps
T465 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3203411155 Mar 14 01:29:21 PM PDT 24 Mar 14 01:29:30 PM PDT 24 3104018410 ps
T98 /workspace/coverage/default/42.sysrst_ctrl_stress_all.4091924405 Mar 14 01:29:49 PM PDT 24 Mar 14 01:40:24 PM PDT 24 235246704192 ps
T155 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.157291723 Mar 14 01:29:09 PM PDT 24 Mar 14 01:29:17 PM PDT 24 5059187237 ps
T166 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3745273228 Mar 14 01:30:02 PM PDT 24 Mar 14 01:30:15 PM PDT 24 48104137062 ps
T167 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.549649240 Mar 14 01:29:53 PM PDT 24 Mar 14 01:30:16 PM PDT 24 88551412392 ps
T168 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.94577268 Mar 14 01:28:59 PM PDT 24 Mar 14 01:29:07 PM PDT 24 2607402426 ps
T169 /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1554823408 Mar 14 01:29:10 PM PDT 24 Mar 14 01:29:14 PM PDT 24 3221270607 ps
T170 /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1323988258 Mar 14 01:28:37 PM PDT 24 Mar 14 01:28:39 PM PDT 24 2574411309 ps
T171 /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.996166879 Mar 14 01:29:14 PM PDT 24 Mar 14 01:29:55 PM PDT 24 32087035644 ps
T172 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.321738391 Mar 14 01:28:07 PM PDT 24 Mar 14 01:28:11 PM PDT 24 2129743600 ps
T173 /workspace/coverage/default/29.sysrst_ctrl_alert_test.3076810253 Mar 14 01:29:10 PM PDT 24 Mar 14 01:29:14 PM PDT 24 2017792768 ps
T88 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2458094324 Mar 14 01:27:54 PM PDT 24 Mar 14 01:27:57 PM PDT 24 5394912441 ps
T298 /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2181480907 Mar 14 01:29:10 PM PDT 24 Mar 14 01:29:20 PM PDT 24 3437197508 ps
T466 /workspace/coverage/default/46.sysrst_ctrl_stress_all.44512045 Mar 14 01:29:53 PM PDT 24 Mar 14 01:30:02 PM PDT 24 7248742755 ps
T467 /workspace/coverage/default/44.sysrst_ctrl_smoke.3135443000 Mar 14 01:29:50 PM PDT 24 Mar 14 01:29:53 PM PDT 24 2129650163 ps
T299 /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3872753185 Mar 14 01:29:55 PM PDT 24 Mar 14 01:29:59 PM PDT 24 3048508058 ps
T468 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2115329303 Mar 14 01:30:05 PM PDT 24 Mar 14 01:32:25 PM PDT 24 52118388482 ps
T336 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.4247234392 Mar 14 01:28:56 PM PDT 24 Mar 14 01:29:02 PM PDT 24 4472170181 ps
T469 /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1952478429 Mar 14 01:28:55 PM PDT 24 Mar 14 01:28:57 PM PDT 24 2529428034 ps
T376 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1634488614 Mar 14 01:28:24 PM PDT 24 Mar 14 01:29:46 PM PDT 24 51998584818 ps
T470 /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4223489533 Mar 14 01:29:37 PM PDT 24 Mar 14 01:29:39 PM PDT 24 2193465306 ps
T471 /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2000324259 Mar 14 01:29:52 PM PDT 24 Mar 14 01:29:55 PM PDT 24 2537422650 ps
T373 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2372754474 Mar 14 01:30:05 PM PDT 24 Mar 14 01:31:06 PM PDT 24 118070560208 ps
T472 /workspace/coverage/default/1.sysrst_ctrl_smoke.1293523161 Mar 14 01:27:51 PM PDT 24 Mar 14 01:27:58 PM PDT 24 2113438604 ps
T385 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.3412640315 Mar 14 01:29:10 PM PDT 24 Mar 14 01:35:45 PM PDT 24 172170706151 ps
T332 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3256264120 Mar 14 01:28:39 PM PDT 24 Mar 14 01:28:42 PM PDT 24 2479753270 ps
T473 /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.905742467 Mar 14 01:28:19 PM PDT 24 Mar 14 01:28:23 PM PDT 24 4065713338 ps
T474 /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1946702580 Mar 14 01:29:09 PM PDT 24 Mar 14 01:29:13 PM PDT 24 8905932815 ps
T475 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1268704266 Mar 14 01:28:10 PM PDT 24 Mar 14 01:28:19 PM PDT 24 4785237112 ps
T185 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.3480667910 Mar 14 01:28:57 PM PDT 24 Mar 14 01:29:00 PM PDT 24 2533062835 ps
T476 /workspace/coverage/default/39.sysrst_ctrl_stress_all.2591438585 Mar 14 01:29:38 PM PDT 24 Mar 14 01:29:51 PM PDT 24 7764923382 ps
T477 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1339224060 Mar 14 01:29:08 PM PDT 24 Mar 14 01:29:16 PM PDT 24 2613344573 ps
T478 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1726230885 Mar 14 01:30:13 PM PDT 24 Mar 14 01:30:20 PM PDT 24 39500306934 ps
T479 /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.770203527 Mar 14 01:27:52 PM PDT 24 Mar 14 01:28:00 PM PDT 24 2610652282 ps
T138 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.519387030 Mar 14 01:29:37 PM PDT 24 Mar 14 01:29:38 PM PDT 24 5831162819 ps
T380 /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1800325095 Mar 14 01:30:04 PM PDT 24 Mar 14 01:31:37 PM PDT 24 69843322119 ps
T174 /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3114884152 Mar 14 01:29:55 PM PDT 24 Mar 14 01:30:48 PM PDT 24 80398092116 ps
T333 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.4149272137 Mar 14 01:27:49 PM PDT 24 Mar 14 01:27:53 PM PDT 24 2458448608 ps
T86 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.720975079 Mar 14 01:29:19 PM PDT 24 Mar 14 01:29:21 PM PDT 24 6004304251 ps
T115 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.839103015 Mar 14 01:29:20 PM PDT 24 Mar 14 01:29:59 PM PDT 24 69236920333 ps
T260 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.626065377 Mar 14 01:29:41 PM PDT 24 Mar 14 01:30:26 PM PDT 24 78097647365 ps
T480 /workspace/coverage/default/38.sysrst_ctrl_alert_test.3938968430 Mar 14 01:29:37 PM PDT 24 Mar 14 01:29:43 PM PDT 24 2014204928 ps
T481 /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1958695128 Mar 14 01:27:55 PM PDT 24 Mar 14 01:28:03 PM PDT 24 2457623568 ps
T482 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.300856286 Mar 14 01:29:38 PM PDT 24 Mar 14 01:29:46 PM PDT 24 2467751553 ps
T483 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1992069192 Mar 14 01:28:39 PM PDT 24 Mar 14 01:28:44 PM PDT 24 3020342160 ps
T484 /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3245069160 Mar 14 01:28:24 PM PDT 24 Mar 14 01:28:35 PM PDT 24 3887356374 ps
T337 /workspace/coverage/default/28.sysrst_ctrl_stress_all.1175319740 Mar 14 01:28:57 PM PDT 24 Mar 14 01:29:41 PM PDT 24 266811487085 ps
T485 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3263795580 Mar 14 01:28:07 PM PDT 24 Mar 14 01:28:15 PM PDT 24 2607136867 ps
T486 /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.1081421496 Mar 14 01:29:09 PM PDT 24 Mar 14 01:29:19 PM PDT 24 2511261104 ps
T487 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.554555664 Mar 14 01:30:09 PM PDT 24 Mar 14 01:31:29 PM PDT 24 32051476639 ps
T488 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3859393630 Mar 14 01:28:47 PM PDT 24 Mar 14 01:29:03 PM PDT 24 22612955782 ps
T304 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2696212558 Mar 14 01:28:38 PM PDT 24 Mar 14 01:29:53 PM PDT 24 29821822784 ps
T309 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3472950171 Mar 14 01:30:13 PM PDT 24 Mar 14 01:31:41 PM PDT 24 63536510167 ps
T186 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.895255755 Mar 14 01:29:50 PM PDT 24 Mar 14 01:30:56 PM PDT 24 49988890470 ps
T310 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1533994193 Mar 14 01:28:33 PM PDT 24 Mar 14 01:28:39 PM PDT 24 3235509805 ps
T311 /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3299142287 Mar 14 01:27:53 PM PDT 24 Mar 14 01:27:56 PM PDT 24 2931389312 ps
T312 /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2601615656 Mar 14 01:28:03 PM PDT 24 Mar 14 01:28:05 PM PDT 24 3471505823 ps
T313 /workspace/coverage/default/46.sysrst_ctrl_combo_detect.3041850746 Mar 14 01:29:51 PM PDT 24 Mar 14 01:33:06 PM PDT 24 74501552919 ps
T314 /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2945762607 Mar 14 01:28:05 PM PDT 24 Mar 14 01:28:10 PM PDT 24 3772293750 ps
T315 /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2745747262 Mar 14 01:28:02 PM PDT 24 Mar 14 01:28:04 PM PDT 24 2637572214 ps
T116 /workspace/coverage/default/33.sysrst_ctrl_stress_all.688419630 Mar 14 01:29:16 PM PDT 24 Mar 14 01:30:29 PM PDT 24 1013300004938 ps
T489 /workspace/coverage/default/40.sysrst_ctrl_alert_test.280971798 Mar 14 01:29:39 PM PDT 24 Mar 14 01:29:42 PM PDT 24 2035656784 ps
T490 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.423759801 Mar 14 01:28:15 PM PDT 24 Mar 14 01:28:23 PM PDT 24 2461335328 ps
T491 /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.4181297320 Mar 14 01:28:17 PM PDT 24 Mar 14 01:28:25 PM PDT 24 2511847596 ps
T492 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.5158775 Mar 14 01:28:45 PM PDT 24 Mar 14 01:28:55 PM PDT 24 4442534102 ps
T493 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3270257855 Mar 14 01:28:45 PM PDT 24 Mar 14 01:28:53 PM PDT 24 2445720707 ps
T494 /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.273340840 Mar 14 01:30:08 PM PDT 24 Mar 14 01:30:14 PM PDT 24 2225889455 ps
T252 /workspace/coverage/default/0.sysrst_ctrl_combo_detect.657801361 Mar 14 01:27:54 PM PDT 24 Mar 14 01:29:21 PM PDT 24 82343256641 ps
T495 /workspace/coverage/default/16.sysrst_ctrl_smoke.3140379276 Mar 14 01:28:36 PM PDT 24 Mar 14 01:28:39 PM PDT 24 2130558140 ps
T84 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1947129967 Mar 14 01:30:05 PM PDT 24 Mar 14 01:32:16 PM PDT 24 46860495750 ps
T85 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1288579221 Mar 14 01:28:19 PM PDT 24 Mar 14 01:29:23 PM PDT 24 85932588951 ps
T496 /workspace/coverage/default/5.sysrst_ctrl_smoke.3564562844 Mar 14 01:28:08 PM PDT 24 Mar 14 01:28:14 PM PDT 24 2113589551 ps
T497 /workspace/coverage/default/28.sysrst_ctrl_alert_test.1331515826 Mar 14 01:29:00 PM PDT 24 Mar 14 01:29:07 PM PDT 24 2014124420 ps
T498 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.826310788 Mar 14 01:30:09 PM PDT 24 Mar 14 01:31:54 PM PDT 24 47397317242 ps
T499 /workspace/coverage/default/20.sysrst_ctrl_smoke.616868851 Mar 14 01:28:45 PM PDT 24 Mar 14 01:28:47 PM PDT 24 2132441325 ps
T500 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.133725418 Mar 14 01:28:41 PM PDT 24 Mar 14 01:30:19 PM PDT 24 70200870097 ps
T501 /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.470988087 Mar 14 01:29:00 PM PDT 24 Mar 14 01:29:02 PM PDT 24 2578679771 ps
T502 /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3039750346 Mar 14 01:29:54 PM PDT 24 Mar 14 01:29:56 PM PDT 24 2469305498 ps
T503 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.4046806454 Mar 14 01:28:06 PM PDT 24 Mar 14 01:28:08 PM PDT 24 2060072775 ps
T504 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1369093133 Mar 14 01:28:06 PM PDT 24 Mar 14 01:28:10 PM PDT 24 2519853048 ps
T384 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2881571156 Mar 14 01:28:50 PM PDT 24 Mar 14 01:30:25 PM PDT 24 74428847652 ps
T253 /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.321201621 Mar 14 01:27:51 PM PDT 24 Mar 14 01:31:04 PM PDT 24 83576210627 ps
T505 /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3291541054 Mar 14 01:29:14 PM PDT 24 Mar 14 01:29:22 PM PDT 24 2452410354 ps
T506 /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2263402325 Mar 14 01:29:40 PM PDT 24 Mar 14 01:29:43 PM PDT 24 2633785471 ps
T507 /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1159073213 Mar 14 01:29:07 PM PDT 24 Mar 14 01:29:10 PM PDT 24 3012725942 ps
T508 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1936194443 Mar 14 01:29:11 PM PDT 24 Mar 14 01:29:13 PM PDT 24 2721826345 ps
T509 /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.2828087540 Mar 14 01:28:23 PM PDT 24 Mar 14 01:28:25 PM PDT 24 2261074754 ps
T218 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2397329570 Mar 14 01:29:54 PM PDT 24 Mar 14 01:29:59 PM PDT 24 3643458767 ps
T510 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.978687996 Mar 14 01:30:08 PM PDT 24 Mar 14 01:30:25 PM PDT 24 24612317324 ps
T511 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2286575530 Mar 14 01:29:01 PM PDT 24 Mar 14 01:29:10 PM PDT 24 41248807203 ps
T512 /workspace/coverage/default/30.sysrst_ctrl_alert_test.617602160 Mar 14 01:29:08 PM PDT 24 Mar 14 01:29:14 PM PDT 24 2010763156 ps
T513 /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.2831659056 Mar 14 01:27:54 PM PDT 24 Mar 14 01:27:57 PM PDT 24 2537673439 ps
T87 /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1996692612 Mar 14 01:28:38 PM PDT 24 Mar 14 01:28:41 PM PDT 24 8338042849 ps
T338 /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3364746333 Mar 14 01:28:38 PM PDT 24 Mar 14 01:28:44 PM PDT 24 7126138165 ps
T188 /workspace/coverage/default/17.sysrst_ctrl_edge_detect.2310826508 Mar 14 01:28:34 PM PDT 24 Mar 14 01:28:38 PM PDT 24 4387268271 ps
T514 /workspace/coverage/default/26.sysrst_ctrl_stress_all.185038790 Mar 14 01:28:58 PM PDT 24 Mar 14 01:29:17 PM PDT 24 7219906147 ps
T515 /workspace/coverage/default/31.sysrst_ctrl_stress_all.178308312 Mar 14 01:29:09 PM PDT 24 Mar 14 01:29:22 PM PDT 24 17002533770 ps
T516 /workspace/coverage/default/34.sysrst_ctrl_stress_all.2070443637 Mar 14 01:29:21 PM PDT 24 Mar 14 01:29:39 PM PDT 24 6566794350 ps
T517 /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3001539320 Mar 14 01:29:40 PM PDT 24 Mar 14 01:29:46 PM PDT 24 2440843901 ps
T518 /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4218191224 Mar 14 01:28:03 PM PDT 24 Mar 14 01:28:04 PM PDT 24 2106466914 ps
T519 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.537708694 Mar 14 01:29:22 PM PDT 24 Mar 14 01:31:15 PM PDT 24 170221220216 ps
T520 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2393203875 Mar 14 01:29:50 PM PDT 24 Mar 14 01:29:58 PM PDT 24 3033629382 ps
T521 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3147250514 Mar 14 01:29:52 PM PDT 24 Mar 14 01:29:54 PM PDT 24 2220281616 ps
T139 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3788366116 Mar 14 01:28:45 PM PDT 24 Mar 14 01:32:29 PM PDT 24 88637426598 ps
T254 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.3933626900 Mar 14 01:29:07 PM PDT 24 Mar 14 01:32:33 PM PDT 24 79648079640 ps
T522 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1645499701 Mar 14 01:28:44 PM PDT 24 Mar 14 01:28:46 PM PDT 24 2662300259 ps
T523 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3028596222 Mar 14 01:28:21 PM PDT 24 Mar 14 01:29:47 PM PDT 24 61274836292 ps
T524 /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.4089403929 Mar 14 01:29:48 PM PDT 24 Mar 14 01:29:52 PM PDT 24 2111337651 ps
T362 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3960750329 Mar 14 01:28:19 PM PDT 24 Mar 14 01:35:10 PM PDT 24 153427311891 ps
T189 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.2667155129 Mar 14 01:28:51 PM PDT 24 Mar 14 01:28:55 PM PDT 24 4876930628 ps
T232 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1574349944 Mar 14 01:30:00 PM PDT 24 Mar 14 01:30:41 PM PDT 24 29603461163 ps
T233 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3553671922 Mar 14 01:28:46 PM PDT 24 Mar 14 01:28:48 PM PDT 24 2062390360 ps
T117 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3940363197 Mar 14 01:28:24 PM PDT 24 Mar 14 01:29:47 PM PDT 24 69625389117 ps
T234 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.2790317568 Mar 14 01:28:54 PM PDT 24 Mar 14 01:28:58 PM PDT 24 2188030502 ps
T194 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.3824146192 Mar 14 01:29:10 PM PDT 24 Mar 14 01:29:12 PM PDT 24 2812988648 ps
T235 /workspace/coverage/default/9.sysrst_ctrl_smoke.902907034 Mar 14 01:28:11 PM PDT 24 Mar 14 01:28:13 PM PDT 24 2135878700 ps
T236 /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.223988017 Mar 14 01:29:39 PM PDT 24 Mar 14 01:29:41 PM PDT 24 3610283837 ps
T237 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2230187309 Mar 14 01:28:57 PM PDT 24 Mar 14 01:29:08 PM PDT 24 3585051493 ps
T238 /workspace/coverage/default/19.sysrst_ctrl_combo_detect.1173813807 Mar 14 01:28:35 PM PDT 24 Mar 14 01:29:57 PM PDT 24 120403768778 ps
T525 /workspace/coverage/default/24.sysrst_ctrl_smoke.800489349 Mar 14 01:28:45 PM PDT 24 Mar 14 01:28:48 PM PDT 24 2117631989 ps
T526 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.1724656844 Mar 14 01:28:50 PM PDT 24 Mar 14 01:28:53 PM PDT 24 2493417749 ps
T527 /workspace/coverage/default/48.sysrst_ctrl_smoke.2987473584 Mar 14 01:29:49 PM PDT 24 Mar 14 01:29:55 PM PDT 24 2113091418 ps
T358 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.2074369951 Mar 14 01:28:48 PM PDT 24 Mar 14 01:34:23 PM PDT 24 128421545742 ps
T528 /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.988003706 Mar 14 01:28:38 PM PDT 24 Mar 14 01:28:46 PM PDT 24 2532180606 ps
T529 /workspace/coverage/default/43.sysrst_ctrl_combo_detect.3248202418 Mar 14 01:29:53 PM PDT 24 Mar 14 01:30:49 PM PDT 24 166333624049 ps
T530 /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1239688027 Mar 14 01:29:09 PM PDT 24 Mar 14 01:29:12 PM PDT 24 11727975615 ps
T531 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1502774655 Mar 14 01:28:21 PM PDT 24 Mar 14 01:28:31 PM PDT 24 3488034184 ps
T532 /workspace/coverage/default/46.sysrst_ctrl_alert_test.3599123473 Mar 14 01:29:53 PM PDT 24 Mar 14 01:29:59 PM PDT 24 2011098764 ps
T533 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.485403809 Mar 14 01:29:20 PM PDT 24 Mar 14 01:29:27 PM PDT 24 2448851383 ps
T534 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3779952241 Mar 14 01:27:55 PM PDT 24 Mar 14 01:28:04 PM PDT 24 3022988267 ps
T535 /workspace/coverage/default/43.sysrst_ctrl_smoke.3263276255 Mar 14 01:29:55 PM PDT 24 Mar 14 01:30:01 PM PDT 24 2112834615 ps
T99 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.93716047 Mar 14 01:29:50 PM PDT 24 Mar 14 01:31:50 PM PDT 24 46697430126 ps
T536 /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.3222399670 Mar 14 01:29:14 PM PDT 24 Mar 14 01:29:16 PM PDT 24 2128336611 ps
T537 /workspace/coverage/default/10.sysrst_ctrl_combo_detect.3578715685 Mar 14 01:28:21 PM PDT 24 Mar 14 01:32:22 PM PDT 24 157342899512 ps
T538 /workspace/coverage/default/2.sysrst_ctrl_smoke.1224450601 Mar 14 01:27:52 PM PDT 24 Mar 14 01:27:58 PM PDT 24 2112193259 ps
T239 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.76082452 Mar 14 01:29:37 PM PDT 24 Mar 14 01:30:00 PM PDT 24 71522167858 ps
T372 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2308484423 Mar 14 01:29:13 PM PDT 24 Mar 14 01:31:53 PM PDT 24 55473210260 ps
T539 /workspace/coverage/default/47.sysrst_ctrl_smoke.298354198 Mar 14 01:29:58 PM PDT 24 Mar 14 01:30:01 PM PDT 24 2114923896 ps
T540 /workspace/coverage/default/23.sysrst_ctrl_stress_all.4114814602 Mar 14 01:28:46 PM PDT 24 Mar 14 01:29:14 PM PDT 24 9057040889 ps
T541 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.638953890 Mar 14 01:29:39 PM PDT 24 Mar 14 01:29:42 PM PDT 24 2461133947 ps
T542 /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2706324565 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:50 PM PDT 24 4626881675 ps
T543 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.4216071033 Mar 14 01:29:52 PM PDT 24 Mar 14 01:30:03 PM PDT 24 3668694733 ps
T544 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3104284197 Mar 14 01:30:03 PM PDT 24 Mar 14 01:31:32 PM PDT 24 64495724297 ps
T545 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.742704853 Mar 14 01:28:57 PM PDT 24 Mar 14 01:34:04 PM PDT 24 232232455342 ps
T546 /workspace/coverage/default/15.sysrst_ctrl_alert_test.1552620003 Mar 14 01:28:38 PM PDT 24 Mar 14 01:28:44 PM PDT 24 2015942621 ps
T547 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.582133089 Mar 14 01:28:21 PM PDT 24 Mar 14 01:28:23 PM PDT 24 2029665173 ps
T548 /workspace/coverage/default/4.sysrst_ctrl_smoke.3133316048 Mar 14 01:28:07 PM PDT 24 Mar 14 01:28:13 PM PDT 24 2112903029 ps
T118 /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3552767755 Mar 14 01:30:02 PM PDT 24 Mar 14 01:30:10 PM PDT 24 4765081668 ps
T549 /workspace/coverage/default/21.sysrst_ctrl_stress_all.765041114 Mar 14 01:28:46 PM PDT 24 Mar 14 01:29:31 PM PDT 24 15226664170 ps
T550 /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3518223969 Mar 14 01:28:40 PM PDT 24 Mar 14 01:28:47 PM PDT 24 2196638460 ps
T375 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1078255382 Mar 14 01:29:53 PM PDT 24 Mar 14 01:32:33 PM PDT 24 57927733309 ps
T551 /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2242969383 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:56 PM PDT 24 2611225052 ps
T552 /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.102096998 Mar 14 01:29:38 PM PDT 24 Mar 14 01:29:44 PM PDT 24 2083665135 ps
T394 /workspace/coverage/default/3.sysrst_ctrl_stress_all.3985470448 Mar 14 01:27:55 PM PDT 24 Mar 14 01:28:19 PM PDT 24 16109060792 ps
T553 /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2286738287 Mar 14 01:29:00 PM PDT 24 Mar 14 01:29:05 PM PDT 24 3075900264 ps
T554 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3190534411 Mar 14 01:30:08 PM PDT 24 Mar 14 01:32:38 PM PDT 24 56385820484 ps
T555 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1685145904 Mar 14 01:28:19 PM PDT 24 Mar 14 01:29:23 PM PDT 24 39273100247 ps
T140 /workspace/coverage/default/24.sysrst_ctrl_stress_all.2438178370 Mar 14 01:28:56 PM PDT 24 Mar 14 01:29:23 PM PDT 24 10927855115 ps
T219 /workspace/coverage/default/27.sysrst_ctrl_edge_detect.4104087523 Mar 14 01:28:56 PM PDT 24 Mar 14 01:28:57 PM PDT 24 4962501665 ps
T220 /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1309034752 Mar 14 01:30:02 PM PDT 24 Mar 14 01:30:40 PM PDT 24 27581002485 ps
T221 /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2661754407 Mar 14 01:27:51 PM PDT 24 Mar 14 01:27:54 PM PDT 24 2126309401 ps
T222 /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2915634749 Mar 14 01:29:52 PM PDT 24 Mar 14 01:29:55 PM PDT 24 2215407194 ps
T223 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.3368888404 Mar 14 01:30:04 PM PDT 24 Mar 14 01:31:08 PM PDT 24 48193404191 ps
T224 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1203253207 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:59 PM PDT 24 4443181638 ps
T225 /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.968511712 Mar 14 01:29:21 PM PDT 24 Mar 14 01:29:27 PM PDT 24 3513219634 ps
T226 /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2071408332 Mar 14 01:27:50 PM PDT 24 Mar 14 01:27:53 PM PDT 24 2629274309 ps
T227 /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3546465714 Mar 14 01:28:20 PM PDT 24 Mar 14 01:28:48 PM PDT 24 207266613159 ps
T556 /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2231820867 Mar 14 01:28:55 PM PDT 24 Mar 14 01:29:05 PM PDT 24 3652643545 ps
T389 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3832242950 Mar 14 01:28:58 PM PDT 24 Mar 14 01:29:56 PM PDT 24 94884963504 ps
T557 /workspace/coverage/default/30.sysrst_ctrl_stress_all.3418750104 Mar 14 01:29:07 PM PDT 24 Mar 14 01:29:28 PM PDT 24 14905585430 ps
T558 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2421076518 Mar 14 01:27:51 PM PDT 24 Mar 14 01:27:55 PM PDT 24 2410999164 ps
T559 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1596523608 Mar 14 01:29:23 PM PDT 24 Mar 14 01:29:32 PM PDT 24 2787299430 ps
T560 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.803024463 Mar 14 01:28:21 PM PDT 24 Mar 14 01:29:15 PM PDT 24 36160643565 ps
T561 /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2586755433 Mar 14 01:28:52 PM PDT 24 Mar 14 01:28:56 PM PDT 24 2518406131 ps
T141 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.2531686011 Mar 14 01:28:27 PM PDT 24 Mar 14 01:29:05 PM PDT 24 52401731181 ps
T562 /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2286832915 Mar 14 01:28:45 PM PDT 24 Mar 14 01:28:49 PM PDT 24 2512510341 ps
T261 /workspace/coverage/default/7.sysrst_ctrl_combo_detect.1500545904 Mar 14 01:28:03 PM PDT 24 Mar 14 01:31:02 PM PDT 24 141951847617 ps
T374 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1749985599 Mar 14 01:30:07 PM PDT 24 Mar 14 01:30:25 PM PDT 24 114241912913 ps
T563 /workspace/coverage/default/22.sysrst_ctrl_smoke.1950931896 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:51 PM PDT 24 2114443060 ps
T564 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.27696577 Mar 14 01:27:54 PM PDT 24 Mar 14 01:27:59 PM PDT 24 2289795722 ps
T565 /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3647716495 Mar 14 01:28:24 PM PDT 24 Mar 14 01:28:29 PM PDT 24 2524731203 ps
T305 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3925561803 Mar 14 01:27:56 PM PDT 24 Mar 14 01:31:19 PM PDT 24 103953098146 ps
T566 /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3349070539 Mar 14 01:29:39 PM PDT 24 Mar 14 01:29:47 PM PDT 24 2939522928 ps
T567 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1377265143 Mar 14 01:28:48 PM PDT 24 Mar 14 01:28:59 PM PDT 24 3866451889 ps
T568 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1892975031 Mar 14 01:29:54 PM PDT 24 Mar 14 01:30:02 PM PDT 24 5153666337 ps
T569 /workspace/coverage/default/31.sysrst_ctrl_alert_test.877247746 Mar 14 01:29:09 PM PDT 24 Mar 14 01:29:16 PM PDT 24 2011992019 ps
T570 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1809864281 Mar 14 01:28:41 PM PDT 24 Mar 14 01:28:44 PM PDT 24 8744807591 ps
T571 /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3410098748 Mar 14 01:29:10 PM PDT 24 Mar 14 01:29:14 PM PDT 24 2148282876 ps
T572 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.4031485617 Mar 14 01:29:38 PM PDT 24 Mar 14 01:29:45 PM PDT 24 2453966705 ps
T573 /workspace/coverage/default/12.sysrst_ctrl_edge_detect.2019060700 Mar 14 01:28:21 PM PDT 24 Mar 14 01:28:25 PM PDT 24 2582748140 ps
T240 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.261192664 Mar 14 01:30:00 PM PDT 24 Mar 14 01:30:29 PM PDT 24 22092307566 ps
T574 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3052947970 Mar 14 01:29:22 PM PDT 24 Mar 14 01:29:24 PM PDT 24 2495202488 ps
T575 /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3774246852 Mar 14 01:29:23 PM PDT 24 Mar 14 01:29:36 PM PDT 24 4743414690 ps
T576 /workspace/coverage/default/27.sysrst_ctrl_alert_test.1557361388 Mar 14 01:29:01 PM PDT 24 Mar 14 01:29:05 PM PDT 24 2021965240 ps
T577 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.4124667026 Mar 14 01:28:19 PM PDT 24 Mar 14 01:28:21 PM PDT 24 2946177993 ps
T578 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.74176061 Mar 14 01:29:05 PM PDT 24 Mar 14 01:29:07 PM PDT 24 2205720728 ps
T255 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.353151020 Mar 14 01:28:17 PM PDT 24 Mar 14 01:30:03 PM PDT 24 180321791274 ps
T579 /workspace/coverage/default/19.sysrst_ctrl_alert_test.1031948910 Mar 14 01:28:48 PM PDT 24 Mar 14 01:28:50 PM PDT 24 2059883463 ps
T81 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3413658837 Mar 14 01:30:03 PM PDT 24 Mar 14 01:33:03 PM PDT 24 71438237675 ps
T580 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2679902024 Mar 14 01:28:50 PM PDT 24 Mar 14 01:28:54 PM PDT 24 2612207519 ps
T306 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1022406168 Mar 14 01:29:53 PM PDT 24 Mar 14 01:32:32 PM PDT 24 59161652629 ps
T581 /workspace/coverage/default/29.sysrst_ctrl_smoke.3047873248 Mar 14 01:29:01 PM PDT 24 Mar 14 01:29:03 PM PDT 24 2123774247 ps
T142 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.3102111247 Mar 14 01:28:56 PM PDT 24 Mar 14 01:29:07 PM PDT 24 5510009372 ps
T119 /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2452278637 Mar 14 01:29:00 PM PDT 24 Mar 14 01:29:08 PM PDT 24 92026378497 ps
T195 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2600638627 Mar 14 01:29:40 PM PDT 24 Mar 14 01:29:42 PM PDT 24 3461610521 ps
T196 /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2352867092 Mar 14 01:29:16 PM PDT 24 Mar 14 01:29:19 PM PDT 24 3933329089 ps
T197 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1807961220 Mar 14 01:28:15 PM PDT 24 Mar 14 01:29:07 PM PDT 24 85162114643 ps
T198 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2839182580 Mar 14 01:29:22 PM PDT 24 Mar 14 01:29:29 PM PDT 24 2513058891 ps
T199 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.2335165959 Mar 14 01:27:53 PM PDT 24 Mar 14 01:30:05 PM PDT 24 211031964118 ps
T200 /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3718259495 Mar 14 01:28:43 PM PDT 24 Mar 14 01:28:45 PM PDT 24 3303065559 ps
T201 /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2956434231 Mar 14 01:28:36 PM PDT 24 Mar 14 01:28:43 PM PDT 24 2458466047 ps
T202 /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1178748135 Mar 14 01:28:37 PM PDT 24 Mar 14 01:28:39 PM PDT 24 2786559505 ps
T582 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.7847415 Mar 14 01:28:27 PM PDT 24 Mar 14 01:28:29 PM PDT 24 2628361413 ps
T583 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.128605201 Mar 14 01:29:09 PM PDT 24 Mar 14 01:29:15 PM PDT 24 2516713521 ps
T584 /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1867791419 Mar 14 01:29:13 PM PDT 24 Mar 14 01:29:15 PM PDT 24 2115802537 ps
T585 /workspace/coverage/default/7.sysrst_ctrl_alert_test.4011226764 Mar 14 01:28:07 PM PDT 24 Mar 14 01:28:13 PM PDT 24 2014761947 ps
T279 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.377434159 Mar 14 01:28:59 PM PDT 24 Mar 14 01:30:44 PM PDT 24 43960804843 ps
T100 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1284111512 Mar 14 01:28:14 PM PDT 24 Mar 14 01:29:37 PM PDT 24 31270903945 ps
T586 /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.37161756 Mar 14 01:28:07 PM PDT 24 Mar 14 01:28:19 PM PDT 24 4208343361 ps
T157 /workspace/coverage/default/43.sysrst_ctrl_edge_detect.615149368 Mar 14 01:29:49 PM PDT 24 Mar 14 01:29:51 PM PDT 24 4233510100 ps
T587 /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.125753163 Mar 14 01:28:51 PM PDT 24 Mar 14 01:28:53 PM PDT 24 2515281801 ps
T588 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1089813594 Mar 14 01:29:49 PM PDT 24 Mar 14 01:29:51 PM PDT 24 2084677641 ps
T589 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.190648265 Mar 14 01:28:44 PM PDT 24 Mar 14 01:33:28 PM PDT 24 102429722702 ps
T590 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.301514515 Mar 14 01:27:54 PM PDT 24 Mar 14 01:28:03 PM PDT 24 11627334096 ps
T591 /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3680916064 Mar 14 01:29:39 PM PDT 24 Mar 14 01:29:43 PM PDT 24 2022984376 ps
T592 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3241636404 Mar 14 01:30:07 PM PDT 24 Mar 14 01:33:03 PM PDT 24 68368971795 ps
T593 /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.2718308715 Mar 14 01:29:35 PM PDT 24 Mar 14 01:29:39 PM PDT 24 2245031006 ps
T594 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1037755085 Mar 14 01:27:52 PM PDT 24 Mar 14 01:35:26 PM PDT 24 164870184463 ps
T595 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3429381933 Mar 14 01:29:53 PM PDT 24 Mar 14 01:29:58 PM PDT 24 2617559420 ps
T143 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1997643035 Mar 14 01:29:06 PM PDT 24 Mar 14 01:30:52 PM PDT 24 166287653670 ps
T596 /workspace/coverage/default/30.sysrst_ctrl_smoke.4156834131 Mar 14 01:29:09 PM PDT 24 Mar 14 01:29:11 PM PDT 24 2152936990 ps
T597 /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1950364288 Mar 14 01:29:38 PM PDT 24 Mar 14 01:29:42 PM PDT 24 3631819624 ps
T395 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2022044758 Mar 14 01:29:52 PM PDT 24 Mar 14 01:30:37 PM PDT 24 342546265805 ps
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