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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.98 99.40 96.51 100.00 98.08 98.85 99.61 93.44


Total test records in report: 915
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T598 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3965498848 Mar 14 01:29:41 PM PDT 24 Mar 14 01:30:10 PM PDT 24 24342867101 ps
T599 /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.585900892 Mar 14 01:29:00 PM PDT 24 Mar 14 01:29:07 PM PDT 24 2166783651 ps
T600 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3641333816 Mar 14 01:29:54 PM PDT 24 Mar 14 01:30:44 PM PDT 24 19080831912 ps
T120 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1848259997 Mar 14 01:28:08 PM PDT 24 Mar 14 01:28:16 PM PDT 24 7222745761 ps
T601 /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2772484270 Mar 14 01:28:38 PM PDT 24 Mar 14 01:28:51 PM PDT 24 4314331491 ps
T602 /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1119437251 Mar 14 01:29:55 PM PDT 24 Mar 14 01:29:59 PM PDT 24 5558543054 ps
T603 /workspace/coverage/default/20.sysrst_ctrl_alert_test.1076210884 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:54 PM PDT 24 2012642485 ps
T604 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.4185805588 Mar 14 01:28:46 PM PDT 24 Mar 14 01:28:49 PM PDT 24 2651996745 ps
T605 /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.452300745 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:52 PM PDT 24 2465066301 ps
T606 /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3224900031 Mar 14 01:29:39 PM PDT 24 Mar 14 01:29:46 PM PDT 24 2511721222 ps
T607 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.429603097 Mar 14 01:29:43 PM PDT 24 Mar 14 01:29:45 PM PDT 24 11016832814 ps
T608 /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.4281230284 Mar 14 01:28:57 PM PDT 24 Mar 14 01:29:05 PM PDT 24 2610532780 ps
T101 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2412136848 Mar 14 01:28:59 PM PDT 24 Mar 14 01:29:19 PM PDT 24 95917936254 ps
T609 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.665259032 Mar 14 01:29:51 PM PDT 24 Mar 14 01:29:53 PM PDT 24 2130010157 ps
T102 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3989889388 Mar 14 01:28:07 PM PDT 24 Mar 14 01:30:53 PM PDT 24 257738988888 ps
T610 /workspace/coverage/default/23.sysrst_ctrl_edge_detect.1755700333 Mar 14 01:28:43 PM PDT 24 Mar 14 01:28:54 PM PDT 24 4577710321 ps
T611 /workspace/coverage/default/7.sysrst_ctrl_edge_detect.4136349206 Mar 14 01:28:04 PM PDT 24 Mar 14 01:28:09 PM PDT 24 3465926517 ps
T612 /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.31195032 Mar 14 01:27:48 PM PDT 24 Mar 14 01:27:50 PM PDT 24 2048788740 ps
T613 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.2862282513 Mar 14 01:28:37 PM PDT 24 Mar 14 01:30:25 PM PDT 24 39616889541 ps
T614 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.547240406 Mar 14 01:29:00 PM PDT 24 Mar 14 01:30:17 PM PDT 24 34453948181 ps
T615 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.2324579293 Mar 14 01:28:35 PM PDT 24 Mar 14 01:30:06 PM PDT 24 139154231106 ps
T616 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.291440485 Mar 14 01:29:51 PM PDT 24 Mar 14 01:29:59 PM PDT 24 2610802900 ps
T617 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2502131467 Mar 14 01:29:22 PM PDT 24 Mar 14 01:29:25 PM PDT 24 8906994576 ps
T382 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.756883551 Mar 14 01:28:10 PM PDT 24 Mar 14 01:30:05 PM PDT 24 95996254515 ps
T618 /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.133984100 Mar 14 01:29:40 PM PDT 24 Mar 14 01:29:43 PM PDT 24 3877177918 ps
T619 /workspace/coverage/default/22.sysrst_ctrl_stress_all.3294145094 Mar 14 01:28:45 PM PDT 24 Mar 14 01:28:50 PM PDT 24 6587233929 ps
T365 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3819234914 Mar 14 01:30:08 PM PDT 24 Mar 14 01:31:06 PM PDT 24 145774946796 ps
T620 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2168296113 Mar 14 01:29:38 PM PDT 24 Mar 14 01:29:41 PM PDT 24 3331744210 ps
T621 /workspace/coverage/default/5.sysrst_ctrl_alert_test.3166248423 Mar 14 01:28:06 PM PDT 24 Mar 14 01:28:08 PM PDT 24 2073402400 ps
T622 /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1579868086 Mar 14 01:29:07 PM PDT 24 Mar 14 01:29:14 PM PDT 24 2037294823 ps
T383 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.599631872 Mar 14 01:29:22 PM PDT 24 Mar 14 01:30:50 PM PDT 24 72231507947 ps
T623 /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3387804274 Mar 14 01:28:59 PM PDT 24 Mar 14 01:29:06 PM PDT 24 2510949299 ps
T624 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2410744684 Mar 14 01:29:20 PM PDT 24 Mar 14 01:29:24 PM PDT 24 2622295734 ps
T625 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2088328737 Mar 14 01:28:58 PM PDT 24 Mar 14 01:30:04 PM PDT 24 117242742140 ps
T626 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.407379064 Mar 14 01:27:53 PM PDT 24 Mar 14 01:27:55 PM PDT 24 2228722019 ps
T262 /workspace/coverage/default/20.sysrst_ctrl_combo_detect.411347294 Mar 14 01:28:42 PM PDT 24 Mar 14 01:34:18 PM PDT 24 130129458049 ps
T627 /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1527703095 Mar 14 01:29:58 PM PDT 24 Mar 14 01:30:01 PM PDT 24 4180585140 ps
T103 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.485525301 Mar 14 01:27:54 PM PDT 24 Mar 14 01:33:25 PM PDT 24 122079690717 ps
T628 /workspace/coverage/default/0.sysrst_ctrl_smoke.968813839 Mar 14 01:27:52 PM PDT 24 Mar 14 01:27:54 PM PDT 24 2137051940 ps
T629 /workspace/coverage/default/17.sysrst_ctrl_smoke.3893308123 Mar 14 01:28:35 PM PDT 24 Mar 14 01:28:37 PM PDT 24 2167449065 ps
T144 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.3064261961 Mar 14 01:28:46 PM PDT 24 Mar 14 01:28:49 PM PDT 24 3207596734 ps
T147 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.735069361 Mar 14 01:28:58 PM PDT 24 Mar 14 01:29:06 PM PDT 24 6996547561 ps
T148 /workspace/coverage/default/7.sysrst_ctrl_smoke.384145197 Mar 14 01:28:09 PM PDT 24 Mar 14 01:28:15 PM PDT 24 2114292076 ps
T121 /workspace/coverage/default/1.sysrst_ctrl_stress_all.3906208199 Mar 14 01:27:54 PM PDT 24 Mar 14 01:28:13 PM PDT 24 7833444391 ps
T149 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1003403029 Mar 14 01:28:45 PM PDT 24 Mar 14 01:28:53 PM PDT 24 2611573896 ps
T150 /workspace/coverage/default/39.sysrst_ctrl_smoke.658745992 Mar 14 01:29:38 PM PDT 24 Mar 14 01:29:42 PM PDT 24 2113903809 ps
T151 /workspace/coverage/default/35.sysrst_ctrl_stress_all.1578987319 Mar 14 01:29:22 PM PDT 24 Mar 14 01:29:40 PM PDT 24 71013393170 ps
T152 /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.439697178 Mar 14 01:28:22 PM PDT 24 Mar 14 01:28:24 PM PDT 24 2856378776 ps
T153 /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1262376560 Mar 14 01:27:50 PM PDT 24 Mar 14 01:27:57 PM PDT 24 3149101664 ps
T154 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3156281547 Mar 14 01:28:46 PM PDT 24 Mar 14 01:29:53 PM PDT 24 563037430294 ps
T630 /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3723738359 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:56 PM PDT 24 2564049579 ps
T631 /workspace/coverage/default/9.sysrst_ctrl_alert_test.1360870417 Mar 14 01:28:19 PM PDT 24 Mar 14 01:28:21 PM PDT 24 2058898278 ps
T632 /workspace/coverage/default/18.sysrst_ctrl_smoke.142666887 Mar 14 01:28:39 PM PDT 24 Mar 14 01:28:41 PM PDT 24 2148107783 ps
T633 /workspace/coverage/default/23.sysrst_ctrl_alert_test.1491760320 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:51 PM PDT 24 2021604616 ps
T634 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2282622584 Mar 14 01:29:13 PM PDT 24 Mar 14 01:29:20 PM PDT 24 2558844760 ps
T635 /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3198025716 Mar 14 01:29:05 PM PDT 24 Mar 14 01:29:08 PM PDT 24 2472013373 ps
T636 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2399834802 Mar 14 01:28:56 PM PDT 24 Mar 14 01:29:40 PM PDT 24 69234795244 ps
T637 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1500444016 Mar 14 01:28:23 PM PDT 24 Mar 14 01:29:07 PM PDT 24 34938634567 ps
T638 /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1072793316 Mar 14 01:29:39 PM PDT 24 Mar 14 01:29:46 PM PDT 24 3177689237 ps
T639 /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2062700688 Mar 14 01:28:06 PM PDT 24 Mar 14 01:28:10 PM PDT 24 3391023080 ps
T640 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2581714051 Mar 14 01:29:51 PM PDT 24 Mar 14 01:32:03 PM PDT 24 48917592833 ps
T641 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3918702978 Mar 14 01:28:04 PM PDT 24 Mar 14 01:28:07 PM PDT 24 2299903257 ps
T642 /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.4122861127 Mar 14 01:27:53 PM PDT 24 Mar 14 01:28:02 PM PDT 24 2611993359 ps
T643 /workspace/coverage/default/38.sysrst_ctrl_smoke.2554787216 Mar 14 01:29:36 PM PDT 24 Mar 14 01:29:43 PM PDT 24 2111686667 ps
T644 /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.2524761769 Mar 14 01:28:50 PM PDT 24 Mar 14 01:28:57 PM PDT 24 2162229373 ps
T645 /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1960433951 Mar 14 01:28:09 PM PDT 24 Mar 14 01:28:14 PM PDT 24 2613317830 ps
T646 /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2696832433 Mar 14 01:29:58 PM PDT 24 Mar 14 01:30:00 PM PDT 24 2613277341 ps
T647 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2900255563 Mar 14 01:29:51 PM PDT 24 Mar 14 01:29:54 PM PDT 24 2490841384 ps
T648 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2701412992 Mar 14 01:28:01 PM PDT 24 Mar 14 01:28:08 PM PDT 24 2224200679 ps
T649 /workspace/coverage/default/2.sysrst_ctrl_stress_all.3143306372 Mar 14 01:27:55 PM PDT 24 Mar 14 01:46:56 PM PDT 24 411437191557 ps
T650 /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1098636637 Mar 14 01:28:33 PM PDT 24 Mar 14 01:28:37 PM PDT 24 3546245644 ps
T651 /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.33319571 Mar 14 01:27:55 PM PDT 24 Mar 14 01:47:15 PM PDT 24 440796432383 ps
T363 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.654251093 Mar 14 01:29:40 PM PDT 24 Mar 14 01:31:33 PM PDT 24 167733219978 ps
T652 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4257077340 Mar 14 01:27:53 PM PDT 24 Mar 14 01:28:00 PM PDT 24 2252202846 ps
T263 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2087625926 Mar 14 01:28:10 PM PDT 24 Mar 14 01:30:51 PM PDT 24 422186393045 ps
T653 /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2642956808 Mar 14 01:27:54 PM PDT 24 Mar 14 01:28:42 PM PDT 24 75831373476 ps
T654 /workspace/coverage/default/37.sysrst_ctrl_smoke.4285564506 Mar 14 01:29:23 PM PDT 24 Mar 14 01:29:27 PM PDT 24 2112413435 ps
T655 /workspace/coverage/default/3.sysrst_ctrl_combo_detect.512469766 Mar 14 01:27:53 PM PDT 24 Mar 14 01:28:52 PM PDT 24 45638878542 ps
T656 /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.171028767 Mar 14 01:29:49 PM PDT 24 Mar 14 01:33:00 PM PDT 24 148962267908 ps
T657 /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1123956701 Mar 14 01:29:28 PM PDT 24 Mar 14 01:29:38 PM PDT 24 3837972879 ps
T658 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.201825721 Mar 14 01:28:24 PM PDT 24 Mar 14 01:33:24 PM PDT 24 111831800016 ps
T659 /workspace/coverage/default/16.sysrst_ctrl_alert_test.356738508 Mar 14 01:28:37 PM PDT 24 Mar 14 01:28:43 PM PDT 24 2010615839 ps
T269 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3353732715 Mar 14 01:27:55 PM PDT 24 Mar 14 01:28:11 PM PDT 24 22061197190 ps
T660 /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3476428224 Mar 14 01:28:09 PM PDT 24 Mar 14 01:28:11 PM PDT 24 2909410332 ps
T661 /workspace/coverage/default/32.sysrst_ctrl_stress_all.268425224 Mar 14 01:29:13 PM PDT 24 Mar 14 01:29:17 PM PDT 24 7142600978 ps
T662 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.505525086 Mar 14 01:28:51 PM PDT 24 Mar 14 01:28:57 PM PDT 24 2669994550 ps
T663 /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.251246729 Mar 14 01:29:38 PM PDT 24 Mar 14 01:29:45 PM PDT 24 2514140913 ps
T307 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1582643313 Mar 14 01:27:55 PM PDT 24 Mar 14 01:28:14 PM PDT 24 36563680087 ps
T664 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.371249714 Mar 14 01:29:54 PM PDT 24 Mar 14 01:29:56 PM PDT 24 2634030555 ps
T665 /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1768713990 Mar 14 01:28:18 PM PDT 24 Mar 14 01:28:21 PM PDT 24 2464285835 ps
T390 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.363368457 Mar 14 01:30:04 PM PDT 24 Mar 14 01:33:31 PM PDT 24 172447852187 ps
T666 /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1602421849 Mar 14 01:28:35 PM PDT 24 Mar 14 01:28:37 PM PDT 24 2630473609 ps
T366 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3187864734 Mar 14 01:28:02 PM PDT 24 Mar 14 01:31:00 PM PDT 24 69833754143 ps
T667 /workspace/coverage/default/14.sysrst_ctrl_stress_all.3847952248 Mar 14 01:28:27 PM PDT 24 Mar 14 01:28:51 PM PDT 24 16941502926 ps
T668 /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.784737542 Mar 14 01:29:08 PM PDT 24 Mar 14 01:29:16 PM PDT 24 2444487328 ps
T669 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.650389088 Mar 14 01:28:38 PM PDT 24 Mar 14 01:35:56 PM PDT 24 635052503593 ps
T228 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1365673843 Mar 14 01:29:57 PM PDT 24 Mar 14 01:29:59 PM PDT 24 4312857808 ps
T670 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3933180381 Mar 14 01:28:22 PM PDT 24 Mar 14 01:28:31 PM PDT 24 7230624584 ps
T125 /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.447412102 Mar 14 01:28:04 PM PDT 24 Mar 14 01:28:16 PM PDT 24 2784434969940 ps
T367 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2872589564 Mar 14 01:30:15 PM PDT 24 Mar 14 01:30:58 PM PDT 24 60824287424 ps
T671 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2220190804 Mar 14 01:28:07 PM PDT 24 Mar 14 01:28:10 PM PDT 24 3670739598 ps
T672 /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.79612541 Mar 14 01:29:50 PM PDT 24 Mar 14 01:29:52 PM PDT 24 2460596909 ps
T673 /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3249505419 Mar 14 01:28:23 PM PDT 24 Mar 14 01:28:30 PM PDT 24 2473104906 ps
T674 /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.385263000 Mar 14 01:28:34 PM PDT 24 Mar 14 01:28:42 PM PDT 24 2694481178 ps
T675 /workspace/coverage/default/24.sysrst_ctrl_alert_test.4158248029 Mar 14 01:29:00 PM PDT 24 Mar 14 01:29:03 PM PDT 24 2033853880 ps
T256 /workspace/coverage/default/24.sysrst_ctrl_combo_detect.3966189057 Mar 14 01:28:57 PM PDT 24 Mar 14 01:31:46 PM PDT 24 64501324191 ps
T676 /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1929064335 Mar 14 01:29:50 PM PDT 24 Mar 14 01:29:52 PM PDT 24 2559487398 ps
T677 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1763853338 Mar 14 01:30:01 PM PDT 24 Mar 14 01:30:44 PM PDT 24 55683030228 ps
T361 /workspace/coverage/default/44.sysrst_ctrl_combo_detect.2288008350 Mar 14 01:29:53 PM PDT 24 Mar 14 01:30:31 PM PDT 24 61064467477 ps
T204 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1162402315 Mar 14 01:29:37 PM PDT 24 Mar 14 01:31:24 PM PDT 24 155809065327 ps
T678 /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2246476064 Mar 14 01:28:56 PM PDT 24 Mar 14 01:28:58 PM PDT 24 2472167612 ps
T123 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1889102972 Mar 14 01:29:55 PM PDT 24 Mar 14 01:32:30 PM PDT 24 420383874055 ps
T679 /workspace/coverage/default/4.sysrst_ctrl_combo_detect.2414279557 Mar 14 01:28:05 PM PDT 24 Mar 14 01:28:45 PM PDT 24 57684203246 ps
T680 /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3318445531 Mar 14 01:29:37 PM PDT 24 Mar 14 01:29:44 PM PDT 24 5678049778 ps
T681 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.4154254136 Mar 14 01:28:29 PM PDT 24 Mar 14 01:28:31 PM PDT 24 2540284449 ps
T682 /workspace/coverage/default/42.sysrst_ctrl_alert_test.388612927 Mar 14 01:29:52 PM PDT 24 Mar 14 01:29:53 PM PDT 24 2031269935 ps
T683 /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3975161440 Mar 14 01:29:27 PM PDT 24 Mar 14 01:29:52 PM PDT 24 39983826735 ps
T684 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.4162666223 Mar 14 01:28:37 PM PDT 24 Mar 14 01:30:38 PM PDT 24 135804151753 ps
T685 /workspace/coverage/default/25.sysrst_ctrl_alert_test.3474908891 Mar 14 01:28:56 PM PDT 24 Mar 14 01:28:58 PM PDT 24 2058911310 ps
T686 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2537593283 Mar 14 01:29:24 PM PDT 24 Mar 14 01:29:26 PM PDT 24 2472844886 ps
T687 /workspace/coverage/default/12.sysrst_ctrl_alert_test.1446357856 Mar 14 01:28:25 PM PDT 24 Mar 14 01:28:31 PM PDT 24 2013324067 ps
T688 /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1493099926 Mar 14 01:28:57 PM PDT 24 Mar 14 01:29:05 PM PDT 24 2613026982 ps
T689 /workspace/coverage/default/19.sysrst_ctrl_stress_all.2954656596 Mar 14 01:28:46 PM PDT 24 Mar 14 01:31:45 PM PDT 24 72197344276 ps
T264 /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1433903851 Mar 14 01:28:59 PM PDT 24 Mar 14 01:33:00 PM PDT 24 90139001711 ps
T690 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.916223147 Mar 14 01:28:21 PM PDT 24 Mar 14 01:28:23 PM PDT 24 2758578507 ps
T124 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1736624503 Mar 14 01:28:37 PM PDT 24 Mar 14 01:29:49 PM PDT 24 70738126226 ps
T691 /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1352251838 Mar 14 01:28:04 PM PDT 24 Mar 14 01:28:11 PM PDT 24 2443915710 ps
T692 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.309057068 Mar 14 01:29:58 PM PDT 24 Mar 14 01:30:04 PM PDT 24 2150681424 ps
T693 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2368763873 Mar 14 01:27:52 PM PDT 24 Mar 14 01:27:53 PM PDT 24 2349777029 ps
T694 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1968463096 Mar 14 01:30:14 PM PDT 24 Mar 14 01:30:41 PM PDT 24 36854190055 ps
T695 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2177276236 Mar 14 01:28:19 PM PDT 24 Mar 14 01:28:20 PM PDT 24 3940961808 ps
T696 /workspace/coverage/default/21.sysrst_ctrl_alert_test.3134392088 Mar 14 01:28:46 PM PDT 24 Mar 14 01:28:49 PM PDT 24 2017335674 ps
T697 /workspace/coverage/default/21.sysrst_ctrl_combo_detect.98492899 Mar 14 01:28:45 PM PDT 24 Mar 14 01:30:20 PM PDT 24 148251019294 ps
T698 /workspace/coverage/default/1.sysrst_ctrl_alert_test.509244186 Mar 14 01:27:53 PM PDT 24 Mar 14 01:27:59 PM PDT 24 2008782571 ps
T270 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.451603706 Mar 14 01:28:03 PM PDT 24 Mar 14 01:28:36 PM PDT 24 22017873733 ps
T699 /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1468015589 Mar 14 01:29:37 PM PDT 24 Mar 14 01:29:39 PM PDT 24 2535491842 ps
T700 /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1770971797 Mar 14 01:28:33 PM PDT 24 Mar 14 01:28:35 PM PDT 24 2643488497 ps
T378 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3179467706 Mar 14 01:29:19 PM PDT 24 Mar 14 01:30:07 PM PDT 24 109438355030 ps
T203 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3301831944 Mar 14 01:28:36 PM PDT 24 Mar 14 01:29:51 PM PDT 24 28555591522 ps
T701 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.300674467 Mar 14 01:28:57 PM PDT 24 Mar 14 01:29:00 PM PDT 24 9064857703 ps
T702 /workspace/coverage/default/41.sysrst_ctrl_stress_all.2682196902 Mar 14 01:29:37 PM PDT 24 Mar 14 01:30:14 PM PDT 24 13620350557 ps
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T705 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.708887661 Mar 14 01:29:37 PM PDT 24 Mar 14 01:29:39 PM PDT 24 2523584504 ps
T706 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1491008524 Mar 14 01:28:34 PM PDT 24 Mar 14 01:28:37 PM PDT 24 3235625798 ps
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T709 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2813058880 Mar 14 01:29:52 PM PDT 24 Mar 14 01:29:56 PM PDT 24 4860005454 ps
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T712 /workspace/coverage/default/35.sysrst_ctrl_edge_detect.4185724279 Mar 14 01:29:20 PM PDT 24 Mar 14 01:29:22 PM PDT 24 4199468146 ps
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T717 /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3427682212 Mar 14 01:29:14 PM PDT 24 Mar 14 01:29:21 PM PDT 24 2610944967 ps
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T719 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.915155143 Mar 14 01:30:03 PM PDT 24 Mar 14 01:30:13 PM PDT 24 3566035667 ps
T720 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3597664091 Mar 14 01:29:55 PM PDT 24 Mar 14 01:30:03 PM PDT 24 2608508960 ps
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T721 /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3740953293 Mar 14 01:28:06 PM PDT 24 Mar 14 01:28:08 PM PDT 24 2495243846 ps
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T723 /workspace/coverage/default/9.sysrst_ctrl_stress_all.2489859501 Mar 14 01:28:15 PM PDT 24 Mar 14 01:28:35 PM PDT 24 8420628188 ps
T724 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1928201195 Mar 14 01:28:22 PM PDT 24 Mar 14 01:28:24 PM PDT 24 2536258508 ps
T725 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.797508458 Mar 14 01:29:23 PM PDT 24 Mar 14 01:29:39 PM PDT 24 12102851269 ps
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T727 /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1213099568 Mar 14 01:29:49 PM PDT 24 Mar 14 01:29:55 PM PDT 24 3828098916 ps
T728 /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.873763867 Mar 14 01:28:37 PM PDT 24 Mar 14 01:28:40 PM PDT 24 2096689198 ps
T729 /workspace/coverage/default/47.sysrst_ctrl_stress_all.3299502735 Mar 14 01:29:58 PM PDT 24 Mar 14 01:33:29 PM PDT 24 84371317516 ps
T730 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1642767695 Mar 14 01:27:49 PM PDT 24 Mar 14 01:27:51 PM PDT 24 3682729346 ps
T731 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.723249518 Mar 14 01:29:08 PM PDT 24 Mar 14 01:29:10 PM PDT 24 3657856988 ps
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T733 /workspace/coverage/default/12.sysrst_ctrl_stress_all.2223596009 Mar 14 01:28:22 PM PDT 24 Mar 14 01:29:51 PM PDT 24 120562949151 ps
T734 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.4251017452 Mar 14 01:28:48 PM PDT 24 Mar 14 01:28:54 PM PDT 24 2046572671 ps
T392 /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.825156139 Mar 14 01:29:08 PM PDT 24 Mar 14 01:33:43 PM PDT 24 101952536447 ps
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T736 /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1635497593 Mar 14 01:28:23 PM PDT 24 Mar 14 01:28:27 PM PDT 24 2623620154 ps
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T739 /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1171810449 Mar 14 01:30:01 PM PDT 24 Mar 14 01:30:08 PM PDT 24 2612436980 ps
T740 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2069290438 Mar 14 01:28:52 PM PDT 24 Mar 14 01:28:54 PM PDT 24 5332274264 ps
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T741 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.4122647481 Mar 14 01:28:34 PM PDT 24 Mar 14 01:28:37 PM PDT 24 2227456776 ps
T742 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3864871270 Mar 14 01:29:50 PM PDT 24 Mar 14 01:32:19 PM PDT 24 57335433330 ps
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T377 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3436461361 Mar 14 01:30:02 PM PDT 24 Mar 14 01:33:26 PM PDT 24 72938868644 ps
T745 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1843337815 Mar 14 01:29:01 PM PDT 24 Mar 14 01:29:09 PM PDT 24 2514187448 ps
T746 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1289986826 Mar 14 01:28:19 PM PDT 24 Mar 14 01:28:36 PM PDT 24 50276567030 ps
T747 /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.103336270 Mar 14 01:28:15 PM PDT 24 Mar 14 01:28:17 PM PDT 24 2068242641 ps
T257 /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.4030488739 Mar 14 01:30:13 PM PDT 24 Mar 14 01:34:11 PM PDT 24 85195249999 ps
T748 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3823327036 Mar 14 01:29:00 PM PDT 24 Mar 14 01:31:29 PM PDT 24 119648625559 ps
T749 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1953683065 Mar 14 01:29:51 PM PDT 24 Mar 14 01:32:03 PM PDT 24 173847387732 ps
T750 /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2163376269 Mar 14 01:28:04 PM PDT 24 Mar 14 01:28:11 PM PDT 24 3678344768 ps
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T753 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.81327916 Mar 14 01:29:53 PM PDT 24 Mar 14 01:29:55 PM PDT 24 2541653215 ps
T79 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2482747082 Mar 14 01:27:54 PM PDT 24 Mar 14 01:28:16 PM PDT 24 31345590917 ps
T754 /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.19829168 Mar 14 01:29:51 PM PDT 24 Mar 14 01:29:53 PM PDT 24 2783117207 ps
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T285 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.790533111 Mar 14 01:27:53 PM PDT 24 Mar 14 01:28:32 PM PDT 24 42073492209 ps
T758 /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2712675081 Mar 14 01:29:50 PM PDT 24 Mar 14 01:29:54 PM PDT 24 2443616250 ps
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T761 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1918985428 Mar 14 01:28:33 PM PDT 24 Mar 14 01:33:45 PM PDT 24 112171283204 ps
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T763 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1647899140 Mar 14 01:29:08 PM PDT 24 Mar 14 01:29:20 PM PDT 24 13346985646 ps
T764 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1743841189 Mar 14 01:28:05 PM PDT 24 Mar 14 01:28:07 PM PDT 24 3182306568 ps
T308 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1628472391 Mar 14 01:28:56 PM PDT 24 Mar 14 01:29:34 PM PDT 24 54170698817 ps
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T766 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2832124147 Mar 14 01:30:08 PM PDT 24 Mar 14 01:30:58 PM PDT 24 38369416569 ps
T767 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1795446066 Mar 14 01:27:54 PM PDT 24 Mar 14 01:28:03 PM PDT 24 2514666033 ps
T768 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1086301795 Mar 14 01:27:48 PM PDT 24 Mar 14 01:27:58 PM PDT 24 3730353613 ps
T769 /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1072502825 Mar 14 01:29:27 PM PDT 24 Mar 14 01:29:29 PM PDT 24 2624543963 ps
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T771 /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2316749382 Mar 14 01:28:39 PM PDT 24 Mar 14 01:28:44 PM PDT 24 2514792404 ps
T772 /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1464782508 Mar 14 01:30:02 PM PDT 24 Mar 14 01:30:10 PM PDT 24 2510550855 ps
T773 /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1404560433 Mar 14 01:27:58 PM PDT 24 Mar 14 01:28:00 PM PDT 24 2481218632 ps
T381 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1658608808 Mar 14 01:30:13 PM PDT 24 Mar 14 01:30:52 PM PDT 24 61432838764 ps
T774 /workspace/coverage/default/8.sysrst_ctrl_alert_test.4177490582 Mar 14 01:28:19 PM PDT 24 Mar 14 01:28:25 PM PDT 24 2012909568 ps
T364 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2506738615 Mar 14 01:30:02 PM PDT 24 Mar 14 01:32:48 PM PDT 24 64612819506 ps
T265 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.3210386835 Mar 14 01:29:38 PM PDT 24 Mar 14 01:31:29 PM PDT 24 164187112015 ps
T775 /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.3766104179 Mar 14 01:29:20 PM PDT 24 Mar 14 01:29:22 PM PDT 24 2147676838 ps
T145 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2467958162 Mar 14 01:28:39 PM PDT 24 Mar 14 01:28:43 PM PDT 24 4177341221 ps
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T777 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3207957530 Mar 14 01:27:55 PM PDT 24 Mar 14 01:28:03 PM PDT 24 2344961680 ps
T778 /workspace/coverage/default/37.sysrst_ctrl_alert_test.1368282058 Mar 14 01:29:42 PM PDT 24 Mar 14 01:29:49 PM PDT 24 2009561048 ps
T779 /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2048102750 Mar 14 01:29:56 PM PDT 24 Mar 14 01:29:58 PM PDT 24 2483657941 ps
T780 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3600842544 Mar 14 01:30:03 PM PDT 24 Mar 14 01:30:50 PM PDT 24 23834985127 ps
T781 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1708337505 Mar 14 01:30:03 PM PDT 24 Mar 14 01:30:05 PM PDT 24 2484395051 ps
T782 /workspace/coverage/default/14.sysrst_ctrl_alert_test.3882082927 Mar 14 01:28:24 PM PDT 24 Mar 14 01:28:25 PM PDT 24 2088285124 ps
T783 /workspace/coverage/default/35.sysrst_ctrl_alert_test.1815826531 Mar 14 01:29:23 PM PDT 24 Mar 14 01:29:29 PM PDT 24 2014989181 ps
T784 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2997481962 Mar 14 01:28:47 PM PDT 24 Mar 14 01:28:56 PM PDT 24 2896336611 ps
T785 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2275151455 Mar 14 01:28:56 PM PDT 24 Mar 14 01:28:59 PM PDT 24 2628475364 ps
T786 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2305138665 Mar 14 01:29:57 PM PDT 24 Mar 14 01:30:27 PM PDT 24 782494152664 ps
T787 /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.2870978528 Mar 14 01:28:21 PM PDT 24 Mar 14 01:28:25 PM PDT 24 2808465799 ps
T788 /workspace/coverage/default/17.sysrst_ctrl_combo_detect.487802089 Mar 14 01:28:34 PM PDT 24 Mar 14 01:29:21 PM PDT 24 66765694854 ps
T789 /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1532156465 Mar 14 01:28:05 PM PDT 24 Mar 14 01:28:10 PM PDT 24 2615316306 ps
T790 /workspace/coverage/default/7.sysrst_ctrl_stress_all.2098846721 Mar 14 01:28:10 PM PDT 24 Mar 14 01:28:16 PM PDT 24 8556100130 ps
T791 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3384299072 Mar 14 01:28:06 PM PDT 24 Mar 14 01:29:58 PM PDT 24 87399406962 ps
T792 /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2921602629 Mar 14 01:29:09 PM PDT 24 Mar 14 01:29:17 PM PDT 24 2612547650 ps
T793 /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.4147415398 Mar 14 01:28:07 PM PDT 24 Mar 14 01:29:35 PM PDT 24 59994273195 ps
T794 /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3550166797 Mar 14 01:28:46 PM PDT 24 Mar 14 01:28:51 PM PDT 24 3318067289 ps
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