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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.98 99.40 96.51 100.00 98.08 98.85 99.61 93.44


Total test records in report: 915
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T23 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3007996135 Mar 14 01:13:45 PM PDT 24 Mar 14 01:13:48 PM PDT 24 2059019422 ps
T795 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.801946260 Mar 14 01:14:11 PM PDT 24 Mar 14 01:14:16 PM PDT 24 2012921422 ps
T266 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.4150045746 Mar 14 01:14:11 PM PDT 24 Mar 14 01:14:18 PM PDT 24 2085498972 ps
T267 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3454002908 Mar 14 01:14:17 PM PDT 24 Mar 14 01:14:22 PM PDT 24 2088225882 ps
T796 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1784793057 Mar 14 01:14:18 PM PDT 24 Mar 14 01:14:21 PM PDT 24 2039435835 ps
T278 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4115036825 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:03 PM PDT 24 2224105743 ps
T33 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2645269213 Mar 14 01:13:37 PM PDT 24 Mar 14 01:13:48 PM PDT 24 3175083172 ps
T797 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2319148665 Mar 14 01:14:14 PM PDT 24 Mar 14 01:14:15 PM PDT 24 2058580322 ps
T798 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2117580600 Mar 14 01:14:17 PM PDT 24 Mar 14 01:14:23 PM PDT 24 2016084683 ps
T34 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.916619709 Mar 14 01:13:50 PM PDT 24 Mar 14 01:13:56 PM PDT 24 2060845248 ps
T20 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.749844857 Mar 14 01:13:57 PM PDT 24 Mar 14 01:14:31 PM PDT 24 10179896626 ps
T24 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1353148352 Mar 14 01:13:37 PM PDT 24 Mar 14 01:13:44 PM PDT 24 2051573275 ps
T340 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1372015785 Mar 14 01:13:49 PM PDT 24 Mar 14 01:13:55 PM PDT 24 2033993466 ps
T341 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1365234930 Mar 14 01:14:13 PM PDT 24 Mar 14 01:14:19 PM PDT 24 2042982096 ps
T799 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2177645791 Mar 14 01:14:14 PM PDT 24 Mar 14 01:14:16 PM PDT 24 2033822683 ps
T800 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2289318078 Mar 14 01:14:10 PM PDT 24 Mar 14 01:14:12 PM PDT 24 2023348606 ps
T801 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1741691810 Mar 14 01:13:48 PM PDT 24 Mar 14 01:13:54 PM PDT 24 2012417812 ps
T386 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3423740531 Mar 14 01:13:37 PM PDT 24 Mar 14 01:13:41 PM PDT 24 2148190224 ps
T282 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2241131208 Mar 14 01:13:39 PM PDT 24 Mar 14 01:13:46 PM PDT 24 2073892873 ps
T802 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.295861366 Mar 14 01:14:16 PM PDT 24 Mar 14 01:14:19 PM PDT 24 2031123877 ps
T274 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2985484448 Mar 14 01:13:36 PM PDT 24 Mar 14 01:13:45 PM PDT 24 2036384797 ps
T342 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2928591061 Mar 14 01:13:35 PM PDT 24 Mar 14 01:13:48 PM PDT 24 4010805575 ps
T803 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.883772454 Mar 14 01:13:50 PM PDT 24 Mar 14 01:13:57 PM PDT 24 2009250934 ps
T804 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.647001611 Mar 14 01:14:11 PM PDT 24 Mar 14 01:14:17 PM PDT 24 2010217868 ps
T21 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2045530218 Mar 14 01:13:44 PM PDT 24 Mar 14 01:13:50 PM PDT 24 7394422357 ps
T283 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1335893798 Mar 14 01:14:02 PM PDT 24 Mar 14 01:14:09 PM PDT 24 2135459767 ps
T357 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3203793019 Mar 14 01:13:37 PM PDT 24 Mar 14 01:13:42 PM PDT 24 3285194320 ps
T805 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.990013099 Mar 14 01:13:44 PM PDT 24 Mar 14 01:13:45 PM PDT 24 2153192527 ps
T22 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3987298859 Mar 14 01:13:50 PM PDT 24 Mar 14 01:14:18 PM PDT 24 9674615331 ps
T387 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2331803549 Mar 14 01:13:54 PM PDT 24 Mar 14 01:14:01 PM PDT 24 2156145225 ps
T271 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.63277181 Mar 14 01:13:59 PM PDT 24 Mar 14 01:15:04 PM PDT 24 22183532547 ps
T806 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2567948204 Mar 14 01:13:57 PM PDT 24 Mar 14 01:14:03 PM PDT 24 2118500878 ps
T354 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1967174205 Mar 14 01:14:01 PM PDT 24 Mar 14 01:14:14 PM PDT 24 5100302827 ps
T275 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3063259192 Mar 14 01:13:48 PM PDT 24 Mar 14 01:13:50 PM PDT 24 2270118017 ps
T355 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3246562479 Mar 14 01:13:39 PM PDT 24 Mar 14 01:13:42 PM PDT 24 4789879450 ps
T388 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3823125881 Mar 14 01:13:36 PM PDT 24 Mar 14 01:15:18 PM PDT 24 39800075542 ps
T272 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1113743105 Mar 14 01:13:37 PM PDT 24 Mar 14 01:15:26 PM PDT 24 42448357481 ps
T807 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3189646562 Mar 14 01:14:14 PM PDT 24 Mar 14 01:14:16 PM PDT 24 2037284814 ps
T276 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.156445439 Mar 14 01:13:51 PM PDT 24 Mar 14 01:13:56 PM PDT 24 2074890657 ps
T273 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.594712781 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:28 PM PDT 24 22256245188 ps
T808 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3002105997 Mar 14 01:13:52 PM PDT 24 Mar 14 01:13:59 PM PDT 24 2049530669 ps
T343 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1895498779 Mar 14 01:13:55 PM PDT 24 Mar 14 01:14:57 PM PDT 24 38790017701 ps
T809 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1533989517 Mar 14 01:14:17 PM PDT 24 Mar 14 01:14:20 PM PDT 24 2023153863 ps
T810 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2865927068 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:05 PM PDT 24 2044051808 ps
T811 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1512292577 Mar 14 01:14:15 PM PDT 24 Mar 14 01:14:21 PM PDT 24 2012820551 ps
T344 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3866079565 Mar 14 01:13:35 PM PDT 24 Mar 14 01:13:46 PM PDT 24 4014857485 ps
T281 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2468997649 Mar 14 01:14:18 PM PDT 24 Mar 14 01:14:20 PM PDT 24 2232742107 ps
T277 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.694919347 Mar 14 01:13:36 PM PDT 24 Mar 14 01:13:44 PM PDT 24 2045133316 ps
T812 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1973099082 Mar 14 01:13:39 PM PDT 24 Mar 14 01:13:43 PM PDT 24 2315194978 ps
T368 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3478409280 Mar 14 01:13:45 PM PDT 24 Mar 14 01:14:17 PM PDT 24 42778484053 ps
T356 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2907304578 Mar 14 01:13:50 PM PDT 24 Mar 14 01:13:56 PM PDT 24 2051748692 ps
T813 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3701525732 Mar 14 01:13:39 PM PDT 24 Mar 14 01:13:43 PM PDT 24 2018304904 ps
T814 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2195635863 Mar 14 01:14:00 PM PDT 24 Mar 14 01:14:03 PM PDT 24 2100414699 ps
T345 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.850183047 Mar 14 01:13:50 PM PDT 24 Mar 14 01:13:57 PM PDT 24 2062431200 ps
T815 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1752675939 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:03 PM PDT 24 2196522809 ps
T816 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2734424587 Mar 14 01:14:12 PM PDT 24 Mar 14 01:14:13 PM PDT 24 2078542625 ps
T370 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1111060902 Mar 14 01:13:38 PM PDT 24 Mar 14 01:13:53 PM PDT 24 22500180289 ps
T817 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.783709850 Mar 14 01:13:49 PM PDT 24 Mar 14 01:13:53 PM PDT 24 2331680391 ps
T818 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.612732553 Mar 14 01:14:12 PM PDT 24 Mar 14 01:14:19 PM PDT 24 2067339392 ps
T346 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2077044103 Mar 14 01:13:38 PM PDT 24 Mar 14 01:14:11 PM PDT 24 42851648187 ps
T819 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3687191036 Mar 14 01:13:39 PM PDT 24 Mar 14 01:13:42 PM PDT 24 2066276479 ps
T820 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1509731819 Mar 14 01:14:10 PM PDT 24 Mar 14 01:14:16 PM PDT 24 2009938882 ps
T821 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3398648123 Mar 14 01:14:17 PM PDT 24 Mar 14 01:14:21 PM PDT 24 2141568758 ps
T822 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.800708638 Mar 14 01:13:53 PM PDT 24 Mar 14 01:13:55 PM PDT 24 2030874530 ps
T823 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.4014716947 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:01 PM PDT 24 2022174806 ps
T824 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.172546803 Mar 14 01:14:14 PM PDT 24 Mar 14 01:14:16 PM PDT 24 2053967063 ps
T825 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1268927958 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:07 PM PDT 24 7748323442 ps
T347 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.722735809 Mar 14 01:13:52 PM PDT 24 Mar 14 01:13:59 PM PDT 24 2041295050 ps
T369 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.474585964 Mar 14 01:14:11 PM PDT 24 Mar 14 01:15:13 PM PDT 24 42370355158 ps
T826 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.71029971 Mar 14 01:13:51 PM PDT 24 Mar 14 01:13:58 PM PDT 24 2087557123 ps
T827 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3738863471 Mar 14 01:14:12 PM PDT 24 Mar 14 01:14:32 PM PDT 24 22384344297 ps
T828 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2283055737 Mar 14 01:14:01 PM PDT 24 Mar 14 01:14:13 PM PDT 24 22561938271 ps
T829 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3851176339 Mar 14 01:14:13 PM PDT 24 Mar 14 01:14:16 PM PDT 24 2019651147 ps
T830 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.56106104 Mar 14 01:13:38 PM PDT 24 Mar 14 01:13:45 PM PDT 24 2025739336 ps
T831 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.4124170792 Mar 14 01:13:38 PM PDT 24 Mar 14 01:13:50 PM PDT 24 3166972508 ps
T832 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1533698058 Mar 14 01:14:17 PM PDT 24 Mar 14 01:14:22 PM PDT 24 2010564928 ps
T833 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3905294736 Mar 14 01:14:15 PM PDT 24 Mar 14 01:14:17 PM PDT 24 2048592455 ps
T348 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.720488622 Mar 14 01:13:36 PM PDT 24 Mar 14 01:13:43 PM PDT 24 2041580830 ps
T349 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.861218084 Mar 14 01:14:02 PM PDT 24 Mar 14 01:14:08 PM PDT 24 2032015374 ps
T834 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3401757305 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:01 PM PDT 24 2114892300 ps
T835 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.891538532 Mar 14 01:14:16 PM PDT 24 Mar 14 01:14:18 PM PDT 24 2036773217 ps
T836 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.468394316 Mar 14 01:13:50 PM PDT 24 Mar 14 01:13:53 PM PDT 24 2205486904 ps
T837 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2813675497 Mar 14 01:13:37 PM PDT 24 Mar 14 01:13:41 PM PDT 24 2165678061 ps
T350 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1367596121 Mar 14 01:13:40 PM PDT 24 Mar 14 01:13:47 PM PDT 24 2656523479 ps
T352 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1821849972 Mar 14 01:13:59 PM PDT 24 Mar 14 01:14:01 PM PDT 24 2069994561 ps
T838 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1809923812 Mar 14 01:13:39 PM PDT 24 Mar 14 01:13:44 PM PDT 24 2157344366 ps
T351 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2306497166 Mar 14 01:13:35 PM PDT 24 Mar 14 01:17:29 PM PDT 24 39766354688 ps
T839 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.221028517 Mar 14 01:13:50 PM PDT 24 Mar 14 01:13:56 PM PDT 24 8491289237 ps
T840 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2155614097 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:00 PM PDT 24 2053513271 ps
T841 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3109791119 Mar 14 01:13:49 PM PDT 24 Mar 14 01:13:56 PM PDT 24 2032533230 ps
T353 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.383355688 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:01 PM PDT 24 2047281310 ps
T842 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3711972954 Mar 14 01:14:13 PM PDT 24 Mar 14 01:14:19 PM PDT 24 2055049283 ps
T843 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2541678790 Mar 14 01:13:48 PM PDT 24 Mar 14 01:14:50 PM PDT 24 22229776711 ps
T844 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3424689945 Mar 14 01:13:37 PM PDT 24 Mar 14 01:13:39 PM PDT 24 4088742675 ps
T845 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3910285434 Mar 14 01:13:52 PM PDT 24 Mar 14 01:14:04 PM PDT 24 4421525099 ps
T846 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.888056 Mar 14 01:13:41 PM PDT 24 Mar 14 01:13:48 PM PDT 24 2818102145 ps
T847 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1131596752 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:04 PM PDT 24 2077501842 ps
T848 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2671851557 Mar 14 01:13:36 PM PDT 24 Mar 14 01:13:41 PM PDT 24 3606997169 ps
T849 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.4204574859 Mar 14 01:13:31 PM PDT 24 Mar 14 01:13:33 PM PDT 24 2030890006 ps
T850 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.211366439 Mar 14 01:14:00 PM PDT 24 Mar 14 01:14:03 PM PDT 24 2120097230 ps
T851 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1493707443 Mar 14 01:13:51 PM PDT 24 Mar 14 01:15:44 PM PDT 24 42423606808 ps
T852 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3308544087 Mar 14 01:14:16 PM PDT 24 Mar 14 01:14:22 PM PDT 24 2012925614 ps
T853 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2795329260 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:15 PM PDT 24 22450684722 ps
T854 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1526422566 Mar 14 01:13:36 PM PDT 24 Mar 14 01:13:44 PM PDT 24 2024406007 ps
T855 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.481977206 Mar 14 01:13:59 PM PDT 24 Mar 14 01:14:03 PM PDT 24 5155399455 ps
T856 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2061299623 Mar 14 01:13:49 PM PDT 24 Mar 14 01:13:51 PM PDT 24 4797019119 ps
T857 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1873219368 Mar 14 01:14:11 PM PDT 24 Mar 14 01:14:14 PM PDT 24 2020744092 ps
T858 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1885466856 Mar 14 01:14:14 PM PDT 24 Mar 14 01:14:15 PM PDT 24 2060020277 ps
T859 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.648924468 Mar 14 01:14:01 PM PDT 24 Mar 14 01:14:08 PM PDT 24 2011710940 ps
T860 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3094748892 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:04 PM PDT 24 2060778342 ps
T861 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.145737080 Mar 14 01:14:15 PM PDT 24 Mar 14 01:14:31 PM PDT 24 5651612266 ps
T862 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.120177243 Mar 14 01:13:51 PM PDT 24 Mar 14 01:13:54 PM PDT 24 2026914910 ps
T863 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2103988651 Mar 14 01:13:39 PM PDT 24 Mar 14 01:13:43 PM PDT 24 4585563745 ps
T864 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1933563151 Mar 14 01:13:37 PM PDT 24 Mar 14 01:13:41 PM PDT 24 4058885713 ps
T865 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1129087249 Mar 14 01:14:14 PM PDT 24 Mar 14 01:14:21 PM PDT 24 2033609566 ps
T866 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1796900434 Mar 14 01:13:40 PM PDT 24 Mar 14 01:15:17 PM PDT 24 39981995033 ps
T867 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2338410624 Mar 14 01:13:40 PM PDT 24 Mar 14 01:13:56 PM PDT 24 6029120854 ps
T868 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3584279636 Mar 14 01:14:16 PM PDT 24 Mar 14 01:14:22 PM PDT 24 2008448246 ps
T869 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2081669732 Mar 14 01:13:49 PM PDT 24 Mar 14 01:14:19 PM PDT 24 42763838524 ps
T870 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1636384574 Mar 14 01:13:49 PM PDT 24 Mar 14 01:13:53 PM PDT 24 2025137759 ps
T871 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1448532594 Mar 14 01:14:11 PM PDT 24 Mar 14 01:14:17 PM PDT 24 2012829783 ps
T872 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3686437518 Mar 14 01:13:53 PM PDT 24 Mar 14 01:13:55 PM PDT 24 2071760511 ps
T873 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.320121861 Mar 14 01:13:38 PM PDT 24 Mar 14 01:13:56 PM PDT 24 22437514620 ps
T874 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.700950295 Mar 14 01:14:17 PM PDT 24 Mar 14 01:14:20 PM PDT 24 2019915582 ps
T875 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3324527535 Mar 14 01:13:56 PM PDT 24 Mar 14 01:14:00 PM PDT 24 2019684778 ps
T876 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2560449096 Mar 14 01:13:52 PM PDT 24 Mar 14 01:13:56 PM PDT 24 2097694643 ps
T877 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1897047907 Mar 14 01:13:41 PM PDT 24 Mar 14 01:15:24 PM PDT 24 42481673481 ps
T878 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3828128704 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:58 PM PDT 24 42392974178 ps
T879 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2791584267 Mar 14 01:13:52 PM PDT 24 Mar 14 01:13:58 PM PDT 24 2010575653 ps
T880 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.427838163 Mar 14 01:13:43 PM PDT 24 Mar 14 01:14:47 PM PDT 24 22201999750 ps
T881 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2137279016 Mar 14 01:13:54 PM PDT 24 Mar 14 01:14:03 PM PDT 24 4608294917 ps
T882 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.987625280 Mar 14 01:13:50 PM PDT 24 Mar 14 01:14:54 PM PDT 24 42409513977 ps
T883 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1554332698 Mar 14 01:13:59 PM PDT 24 Mar 14 01:14:06 PM PDT 24 2012111469 ps
T884 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3516201970 Mar 14 01:13:55 PM PDT 24 Mar 14 01:14:01 PM PDT 24 2013073758 ps
T885 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2501810036 Mar 14 01:13:36 PM PDT 24 Mar 14 01:13:39 PM PDT 24 2031698354 ps
T886 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.319344654 Mar 14 01:13:50 PM PDT 24 Mar 14 01:13:54 PM PDT 24 2129552342 ps
T887 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.652379406 Mar 14 01:13:38 PM PDT 24 Mar 14 01:13:43 PM PDT 24 2030719684 ps
T888 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.149271761 Mar 14 01:14:16 PM PDT 24 Mar 14 01:14:19 PM PDT 24 2014929610 ps
T889 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.985082846 Mar 14 01:14:17 PM PDT 24 Mar 14 01:14:23 PM PDT 24 2012092923 ps
T890 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1658580802 Mar 14 01:14:17 PM PDT 24 Mar 14 01:14:19 PM PDT 24 2029638155 ps
T891 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.409929277 Mar 14 01:14:15 PM PDT 24 Mar 14 01:14:21 PM PDT 24 2016224742 ps
T892 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.841824936 Mar 14 01:14:16 PM PDT 24 Mar 14 01:14:22 PM PDT 24 2008934462 ps
T893 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3903286101 Mar 14 01:14:15 PM PDT 24 Mar 14 01:14:17 PM PDT 24 2055978158 ps
T894 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.4256274289 Mar 14 01:14:15 PM PDT 24 Mar 14 01:14:18 PM PDT 24 2122362204 ps
T895 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2907771082 Mar 14 01:13:59 PM PDT 24 Mar 14 01:14:20 PM PDT 24 8379737792 ps
T896 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2756867646 Mar 14 01:14:14 PM PDT 24 Mar 14 01:14:43 PM PDT 24 10891259655 ps
T897 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4228925106 Mar 14 01:14:15 PM PDT 24 Mar 14 01:14:21 PM PDT 24 2015803338 ps
T898 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1284517454 Mar 14 01:14:15 PM PDT 24 Mar 14 01:14:18 PM PDT 24 2041784105 ps
T899 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.560838445 Mar 14 01:14:16 PM PDT 24 Mar 14 01:14:22 PM PDT 24 2014525863 ps
T900 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2068842342 Mar 14 01:13:57 PM PDT 24 Mar 14 01:13:59 PM PDT 24 2318443910 ps
T901 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1217771672 Mar 14 01:14:16 PM PDT 24 Mar 14 01:15:18 PM PDT 24 22168442050 ps
T902 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.731514401 Mar 14 01:13:44 PM PDT 24 Mar 14 01:13:50 PM PDT 24 2012262950 ps
T903 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.566961157 Mar 14 01:13:55 PM PDT 24 Mar 14 01:14:57 PM PDT 24 42595761555 ps
T904 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.205267582 Mar 14 01:13:49 PM PDT 24 Mar 14 01:14:49 PM PDT 24 22227340724 ps
T905 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2401007429 Mar 14 01:14:15 PM PDT 24 Mar 14 01:14:35 PM PDT 24 7759245568 ps
T906 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2831506840 Mar 14 01:13:58 PM PDT 24 Mar 14 01:14:01 PM PDT 24 2060347051 ps
T907 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1691673596 Mar 14 01:13:49 PM PDT 24 Mar 14 01:13:56 PM PDT 24 2070729977 ps
T908 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2541440888 Mar 14 01:13:49 PM PDT 24 Mar 14 01:13:51 PM PDT 24 2073027746 ps
T909 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2241360373 Mar 14 01:13:43 PM PDT 24 Mar 14 01:13:50 PM PDT 24 2130288325 ps
T910 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.140109179 Mar 14 01:13:49 PM PDT 24 Mar 14 01:14:10 PM PDT 24 7030907945 ps
T911 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1360881134 Mar 14 01:13:47 PM PDT 24 Mar 14 01:13:49 PM PDT 24 2066156792 ps
T912 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3112912560 Mar 14 01:13:49 PM PDT 24 Mar 14 01:13:51 PM PDT 24 2308268001 ps
T913 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2354130675 Mar 14 01:13:59 PM PDT 24 Mar 14 01:14:06 PM PDT 24 2122834284 ps
T914 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2789033279 Mar 14 01:14:00 PM PDT 24 Mar 14 01:14:06 PM PDT 24 5123478946 ps
T915 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1555010515 Mar 14 01:13:37 PM PDT 24 Mar 14 01:13:57 PM PDT 24 7412117178 ps

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.473976199
Short name T1
Test name
Test status
Simulation time 87930155995 ps
CPU time 110.82 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:30:36 PM PDT 24
Peak memory 209756 kb
Host smart-aa6a462d-dd79-4f50-a6fb-612bc674aed3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473976199 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.473976199
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1422323977
Short name T40
Test name
Test status
Simulation time 148295537085 ps
CPU time 222.53 seconds
Started Mar 14 01:29:16 PM PDT 24
Finished Mar 14 01:32:59 PM PDT 24
Peak memory 218028 kb
Host smart-6f124a6e-48f9-4933-b58d-59bec555b74e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422323977 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.1422323977
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2695768342
Short name T42
Test name
Test status
Simulation time 109083854435 ps
CPU time 78.34 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:30:06 PM PDT 24
Peak memory 201516 kb
Host smart-f896859c-e6a7-4ba4-b571-78967c513e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695768342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.2695768342
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3995174913
Short name T36
Test name
Test status
Simulation time 3373107014 ps
CPU time 8.87 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 201212 kb
Host smart-6a5cd366-648b-4bac-b4ca-9db78ee2d8ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995174913 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.3995174913
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3383521960
Short name T75
Test name
Test status
Simulation time 39015794382 ps
CPU time 26.4 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:28:21 PM PDT 24
Peak memory 201316 kb
Host smart-e461d9be-7bc1-4f44-927e-31d313fcfb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383521960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.3383521960
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.461537919
Short name T6
Test name
Test status
Simulation time 3677383904 ps
CPU time 2.74 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:28:25 PM PDT 24
Peak memory 201260 kb
Host smart-dc7b15be-76c5-45d1-b8c5-b0677a9803ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461537919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.461537919
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3788366116
Short name T139
Test name
Test status
Simulation time 88637426598 ps
CPU time 223.62 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:32:29 PM PDT 24
Peak memory 213552 kb
Host smart-55ba08b3-4514-4bc2-af54-93d129cf9d67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788366116 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.3788366116
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.2278032318
Short name T211
Test name
Test status
Simulation time 107868771698 ps
CPU time 264.31 seconds
Started Mar 14 01:29:08 PM PDT 24
Finished Mar 14 01:33:33 PM PDT 24
Peak memory 201320 kb
Host smart-711f7a59-6eea-45db-bb03-bcb71fa5b1ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278032318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.2278032318
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.63277181
Short name T271
Test name
Test status
Simulation time 22183532547 ps
CPU time 64.32 seconds
Started Mar 14 01:13:59 PM PDT 24
Finished Mar 14 01:15:04 PM PDT 24
Peak memory 201296 kb
Host smart-21fbc3dc-cba9-4847-8e78-cede64faeb95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63277181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_tl_intg_err.63277181
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.3658841490
Short name T35
Test name
Test status
Simulation time 1859186575824 ps
CPU time 1340.65 seconds
Started Mar 14 01:28:58 PM PDT 24
Finished Mar 14 01:51:18 PM PDT 24
Peak memory 201364 kb
Host smart-86391dc5-06fa-428b-8201-d40bbde768bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658841490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.3658841490
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1230256556
Short name T110
Test name
Test status
Simulation time 108181863676 ps
CPU time 72.06 seconds
Started Mar 14 01:29:14 PM PDT 24
Finished Mar 14 01:30:26 PM PDT 24
Peak memory 209432 kb
Host smart-f429c24e-9adf-49d0-b721-02a4d1ae93a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230256556 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1230256556
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3155760289
Short name T248
Test name
Test status
Simulation time 97573514841 ps
CPU time 226.45 seconds
Started Mar 14 01:28:44 PM PDT 24
Finished Mar 14 01:32:31 PM PDT 24
Peak memory 201512 kb
Host smart-7be8927b-4785-496e-83b2-3adf75e88c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155760289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.3155760289
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.4091924405
Short name T98
Test name
Test status
Simulation time 235246704192 ps
CPU time 635.19 seconds
Started Mar 14 01:29:49 PM PDT 24
Finished Mar 14 01:40:24 PM PDT 24
Peak memory 201444 kb
Host smart-f92cef9c-94be-4d58-be8a-1603553914b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091924405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.4091924405
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1365234930
Short name T341
Test name
Test status
Simulation time 2042982096 ps
CPU time 5.02 seconds
Started Mar 14 01:14:13 PM PDT 24
Finished Mar 14 01:14:19 PM PDT 24
Peak memory 201068 kb
Host smart-bceb59c2-c3ae-4ef8-a943-e630f4f397bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365234930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.1365234930
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.612546335
Short name T2
Test name
Test status
Simulation time 169142592851 ps
CPU time 208.68 seconds
Started Mar 14 01:30:01 PM PDT 24
Finished Mar 14 01:33:30 PM PDT 24
Peak memory 201504 kb
Host smart-d26cab3c-b5dd-4e19-86df-50717d5d69cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612546335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_wi
th_pre_cond.612546335
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.2373431893
Short name T16
Test name
Test status
Simulation time 2028126612 ps
CPU time 2.21 seconds
Started Mar 14 01:28:51 PM PDT 24
Finished Mar 14 01:28:53 PM PDT 24
Peak memory 201256 kb
Host smart-64e916bc-b840-47fe-b57d-a5422cda8b0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373431893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.2373431893
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1996692612
Short name T87
Test name
Test status
Simulation time 8338042849 ps
CPU time 1.77 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:28:41 PM PDT 24
Peak memory 201112 kb
Host smart-a9ae21dc-708f-4617-80be-0ae06f847cd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996692612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.1996692612
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3912500878
Short name T8
Test name
Test status
Simulation time 66245406228 ps
CPU time 41.41 seconds
Started Mar 14 01:30:03 PM PDT 24
Finished Mar 14 01:30:44 PM PDT 24
Peak memory 217916 kb
Host smart-c07a9533-6cb6-487c-8c15-b96fd9b7c5c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912500878 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3912500878
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3989889388
Short name T102
Test name
Test status
Simulation time 257738988888 ps
CPU time 166.38 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:30:53 PM PDT 24
Peak memory 209856 kb
Host smart-88d1421a-e95e-4109-a3d6-1d934338cda7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989889388 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.3989889388
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3454002908
Short name T267
Test name
Test status
Simulation time 2088225882 ps
CPU time 4.94 seconds
Started Mar 14 01:14:17 PM PDT 24
Finished Mar 14 01:14:22 PM PDT 24
Peak memory 201144 kb
Host smart-c433e569-b284-437d-a6a8-b5c04fe1770a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454002908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.3454002908
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2482747082
Short name T79
Test name
Test status
Simulation time 31345590917 ps
CPU time 21.36 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:28:16 PM PDT 24
Peak memory 201344 kb
Host smart-bfe9e70a-e036-4a56-836c-78a9c9b9f96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482747082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.2482747082
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.3102111247
Short name T142
Test name
Test status
Simulation time 5510009372 ps
CPU time 10.58 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:29:07 PM PDT 24
Peak memory 201180 kb
Host smart-431c9f66-8869-48eb-8df0-c2ee2ed5e176
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102111247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.3102111247
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3969245450
Short name T27
Test name
Test status
Simulation time 43964282842 ps
CPU time 31.18 seconds
Started Mar 14 01:28:55 PM PDT 24
Finished Mar 14 01:29:26 PM PDT 24
Peak memory 217872 kb
Host smart-6bbec7d6-5ec8-44bf-b6c5-3c9e8e554978
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969245450 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.3969245450
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2541080591
Short name T109
Test name
Test status
Simulation time 109123052498 ps
CPU time 69.06 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:29:32 PM PDT 24
Peak memory 209816 kb
Host smart-df8a77cf-7d68-4cf8-b05e-c039aedaf990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541080591 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.2541080591
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1736624503
Short name T124
Test name
Test status
Simulation time 70738126226 ps
CPU time 71.6 seconds
Started Mar 14 01:28:37 PM PDT 24
Finished Mar 14 01:29:49 PM PDT 24
Peak memory 217880 kb
Host smart-aa52bbd0-4685-49fd-abda-54741e30b42d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736624503 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.1736624503
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.2438178370
Short name T140
Test name
Test status
Simulation time 10927855115 ps
CPU time 27.48 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:29:23 PM PDT 24
Peak memory 201188 kb
Host smart-fc8a6156-df04-4a38-81a0-cc4fe74510ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438178370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.2438178370
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1522871294
Short name T112
Test name
Test status
Simulation time 71339726476 ps
CPU time 44.64 seconds
Started Mar 14 01:29:23 PM PDT 24
Finished Mar 14 01:30:08 PM PDT 24
Peak memory 209776 kb
Host smart-5bf0f734-3613-44eb-afb4-f064bf63a063
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522871294 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1522871294
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3997363407
Short name T7
Test name
Test status
Simulation time 91911774085 ps
CPU time 127.01 seconds
Started Mar 14 01:29:14 PM PDT 24
Finished Mar 14 01:31:21 PM PDT 24
Peak memory 201420 kb
Host smart-fd996a3e-069c-4231-8aaa-2643b1d937c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997363407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.3997363407
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1256943071
Short name T284
Test name
Test status
Simulation time 42014351190 ps
CPU time 102.93 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 221620 kb
Host smart-489f5b46-d4c6-4875-a913-4248a3d6ee65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256943071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.1256943071
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3930913294
Short name T74
Test name
Test status
Simulation time 42989471122 ps
CPU time 28.83 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:30:30 PM PDT 24
Peak memory 201484 kb
Host smart-cb7fd5d9-65b0-48ab-8536-65071dca59b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930913294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.3930913294
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1022406168
Short name T306
Test name
Test status
Simulation time 59161652629 ps
CPU time 159.72 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:32:32 PM PDT 24
Peak memory 212736 kb
Host smart-2796e6c3-1126-4b9b-9c7c-172ba5a736ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022406168 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.1022406168
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1113743105
Short name T272
Test name
Test status
Simulation time 42448357481 ps
CPU time 108.76 seconds
Started Mar 14 01:13:37 PM PDT 24
Finished Mar 14 01:15:26 PM PDT 24
Peak memory 201288 kb
Host smart-10484333-919b-420a-b623-4e5e363c5d79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113743105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.1113743105
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.469000408
Short name T217
Test name
Test status
Simulation time 174003476832 ps
CPU time 478.37 seconds
Started Mar 14 01:29:21 PM PDT 24
Finished Mar 14 01:37:20 PM PDT 24
Peak memory 201372 kb
Host smart-ea3491e9-1181-4110-b03c-f2dbb2a59722
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469000408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.469000408
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.4237887730
Short name T379
Test name
Test status
Simulation time 62767848457 ps
CPU time 26.04 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:30:28 PM PDT 24
Peak memory 201492 kb
Host smart-8fa38175-7413-4055-a270-a1b3b98ef4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237887730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.4237887730
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1278631280
Short name T295
Test name
Test status
Simulation time 8165595669 ps
CPU time 11.32 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:17 PM PDT 24
Peak memory 201376 kb
Host smart-b84b03bc-8301-423f-b462-f1acb70a02e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278631280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1278631280
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.353151020
Short name T255
Test name
Test status
Simulation time 180321791274 ps
CPU time 105.25 seconds
Started Mar 14 01:28:17 PM PDT 24
Finished Mar 14 01:30:03 PM PDT 24
Peak memory 209948 kb
Host smart-d83736c1-4403-4425-ab67-8036069ec8b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353151020 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.353151020
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4230680263
Short name T391
Test name
Test status
Simulation time 53474698044 ps
CPU time 137.49 seconds
Started Mar 14 01:28:08 PM PDT 24
Finished Mar 14 01:30:26 PM PDT 24
Peak memory 201520 kb
Host smart-85ecf764-e238-4c6f-8ebc-09b804303b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230680263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.4230680263
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.2872589564
Short name T367
Test name
Test status
Simulation time 60824287424 ps
CPU time 43.14 seconds
Started Mar 14 01:30:15 PM PDT 24
Finished Mar 14 01:30:58 PM PDT 24
Peak memory 201380 kb
Host smart-ae6f0110-7066-4637-a2d1-7c214fd27988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872589564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.2872589564
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.999086533
Short name T302
Test name
Test status
Simulation time 2634085225 ps
CPU time 1.24 seconds
Started Mar 14 01:29:24 PM PDT 24
Finished Mar 14 01:29:25 PM PDT 24
Peak memory 201276 kb
Host smart-02f486c7-d439-4a9a-a8c8-b81cbdb5385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999086533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.999086533
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1997643035
Short name T143
Test name
Test status
Simulation time 166287653670 ps
CPU time 105.87 seconds
Started Mar 14 01:29:06 PM PDT 24
Finished Mar 14 01:30:52 PM PDT 24
Peak memory 201560 kb
Host smart-9eb17ddf-0adc-42e9-b41d-826e64401999
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997643035 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1997643035
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2506738615
Short name T364
Test name
Test status
Simulation time 64612819506 ps
CPU time 166.08 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:32:48 PM PDT 24
Peak memory 201432 kb
Host smart-f1240742-836a-42fd-bf7c-f12cfda78463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506738615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.2506738615
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2001401105
Short name T72
Test name
Test status
Simulation time 99663820004 ps
CPU time 132.51 seconds
Started Mar 14 01:30:04 PM PDT 24
Finished Mar 14 01:32:17 PM PDT 24
Peak memory 201584 kb
Host smart-a6ded400-0fb3-4ac4-abe6-5d820766463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001401105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.2001401105
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3819234914
Short name T365
Test name
Test status
Simulation time 145774946796 ps
CPU time 58.06 seconds
Started Mar 14 01:30:08 PM PDT 24
Finished Mar 14 01:31:06 PM PDT 24
Peak memory 201540 kb
Host smart-33618309-af84-4ede-9362-da5b45b14802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819234914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.3819234914
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.2467958162
Short name T145
Test name
Test status
Simulation time 4177341221 ps
CPU time 2.8 seconds
Started Mar 14 01:28:39 PM PDT 24
Finished Mar 14 01:28:43 PM PDT 24
Peak memory 201208 kb
Host smart-dc098693-c43d-4907-8d1c-6a40c157c1bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467958162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.2467958162
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.321201621
Short name T253
Test name
Test status
Simulation time 83576210627 ps
CPU time 192.38 seconds
Started Mar 14 01:27:51 PM PDT 24
Finished Mar 14 01:31:04 PM PDT 24
Peak memory 209876 kb
Host smart-6927b7ae-7195-4bb4-a2e1-6eee2f747939
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321201621 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.321201621
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.447412102
Short name T125
Test name
Test status
Simulation time 2784434969940 ps
CPU time 11.62 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:28:16 PM PDT 24
Peak memory 201156 kb
Host smart-8b12dad7-ec63-47ab-b8a4-c65f6a6e8432
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447412102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ultra_low_pwr.447412102
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2306497166
Short name T351
Test name
Test status
Simulation time 39766354688 ps
CPU time 233.6 seconds
Started Mar 14 01:13:35 PM PDT 24
Finished Mar 14 01:17:29 PM PDT 24
Peak memory 201324 kb
Host smart-fba58972-3d48-4963-9b77-c58daaa5ece8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306497166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_bit_bash.2306497166
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.783709850
Short name T817
Test name
Test status
Simulation time 2331680391 ps
CPU time 3.61 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:13:53 PM PDT 24
Peak memory 201264 kb
Host smart-22b83955-95c5-4f1e-9d7c-a28eb2e0ff9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783709850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_error
s.783709850
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.15560598
Short name T41
Test name
Test status
Simulation time 3249416835 ps
CPU time 1.85 seconds
Started Mar 14 01:29:07 PM PDT 24
Finished Mar 14 01:29:09 PM PDT 24
Peak memory 201180 kb
Host smart-b51dff98-14b8-41a8-82b0-8c0340e46328
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15560598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl
_edge_detect.15560598
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1268927958
Short name T825
Test name
Test status
Simulation time 7748323442 ps
CPU time 9.25 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:07 PM PDT 24
Peak memory 201256 kb
Host smart-dfd4a9c3-e2f0-4ed9-a893-13ed75cabc04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268927958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.1268927958
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.688419630
Short name T116
Test name
Test status
Simulation time 1013300004938 ps
CPU time 72.45 seconds
Started Mar 14 01:29:16 PM PDT 24
Finished Mar 14 01:30:29 PM PDT 24
Peak memory 201200 kb
Host smart-c262905f-fbb1-427a-98a8-f96fbdd26c46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688419630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_st
ress_all.688419630
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3179467706
Short name T378
Test name
Test status
Simulation time 109438355030 ps
CPU time 48.01 seconds
Started Mar 14 01:29:19 PM PDT 24
Finished Mar 14 01:30:07 PM PDT 24
Peak memory 201460 kb
Host smart-8fc72615-db75-4e97-8c82-08a39fb2dd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179467706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.3179467706
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.599631872
Short name T383
Test name
Test status
Simulation time 72231507947 ps
CPU time 88.42 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:30:50 PM PDT 24
Peak memory 201408 kb
Host smart-e294195c-ac43-44f1-bdf6-60fc4d73447e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599631872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_wi
th_pre_cond.599631872
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3187864734
Short name T366
Test name
Test status
Simulation time 69833754143 ps
CPU time 177.93 seconds
Started Mar 14 01:28:02 PM PDT 24
Finished Mar 14 01:31:00 PM PDT 24
Peak memory 201488 kb
Host smart-19a7d96d-85c5-4b54-a33a-8b53997f0dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187864734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.3187864734
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1078255382
Short name T375
Test name
Test status
Simulation time 57927733309 ps
CPU time 159.83 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 201468 kb
Host smart-bad19beb-ab8c-4144-938e-b9f876c6381b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078255382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.1078255382
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.4114041123
Short name T393
Test name
Test status
Simulation time 61952891721 ps
CPU time 40.31 seconds
Started Mar 14 01:30:01 PM PDT 24
Finished Mar 14 01:30:42 PM PDT 24
Peak memory 201432 kb
Host smart-3362f5a8-1c98-44b5-97cb-c2e35686370e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114041123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.4114041123
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.363368457
Short name T390
Test name
Test status
Simulation time 172447852187 ps
CPU time 206.65 seconds
Started Mar 14 01:30:04 PM PDT 24
Finished Mar 14 01:33:31 PM PDT 24
Peak memory 201500 kb
Host smart-72f56ee7-25e3-4296-a4f9-165ace0feec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363368457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_wi
th_pre_cond.363368457
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2372754474
Short name T373
Test name
Test status
Simulation time 118070560208 ps
CPU time 60.61 seconds
Started Mar 14 01:30:05 PM PDT 24
Finished Mar 14 01:31:06 PM PDT 24
Peak memory 201424 kb
Host smart-b1fe4773-d956-4ff4-9e91-77ebcbb7b9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372754474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.2372754474
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1629854629
Short name T320
Test name
Test status
Simulation time 75922506695 ps
CPU time 96.41 seconds
Started Mar 14 01:30:09 PM PDT 24
Finished Mar 14 01:31:47 PM PDT 24
Peak memory 201424 kb
Host smart-b20a6a57-0c4b-466f-a555-978eabae6433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629854629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.1629854629
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1947129967
Short name T84
Test name
Test status
Simulation time 46860495750 ps
CPU time 130.26 seconds
Started Mar 14 01:30:05 PM PDT 24
Finished Mar 14 01:32:16 PM PDT 24
Peak memory 201496 kb
Host smart-fc25e773-ba81-4340-8a6d-e13d784f20b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947129967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.1947129967
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1367596121
Short name T350
Test name
Test status
Simulation time 2656523479 ps
CPU time 5.59 seconds
Started Mar 14 01:13:40 PM PDT 24
Finished Mar 14 01:13:47 PM PDT 24
Peak memory 201228 kb
Host smart-a73f7223-1998-458d-b6a1-92b61fa3742d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367596121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.1367596121
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1796900434
Short name T866
Test name
Test status
Simulation time 39981995033 ps
CPU time 96.02 seconds
Started Mar 14 01:13:40 PM PDT 24
Finished Mar 14 01:15:17 PM PDT 24
Peak memory 201228 kb
Host smart-a348d21a-7710-4463-91af-4b87546d8abb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796900434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.1796900434
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3424689945
Short name T844
Test name
Test status
Simulation time 4088742675 ps
CPU time 2.09 seconds
Started Mar 14 01:13:37 PM PDT 24
Finished Mar 14 01:13:39 PM PDT 24
Peak memory 201148 kb
Host smart-60e41fc7-d5bb-403b-95f7-235c6a1e4d4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424689945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.3424689945
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1809923812
Short name T838
Test name
Test status
Simulation time 2157344366 ps
CPU time 3.83 seconds
Started Mar 14 01:13:39 PM PDT 24
Finished Mar 14 01:13:44 PM PDT 24
Peak memory 201048 kb
Host smart-0c6a0b7e-c84e-4962-beba-89947927898f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809923812 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1809923812
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3687191036
Short name T819
Test name
Test status
Simulation time 2066276479 ps
CPU time 2.21 seconds
Started Mar 14 01:13:39 PM PDT 24
Finished Mar 14 01:13:42 PM PDT 24
Peak memory 201020 kb
Host smart-4ae5061d-854d-453e-b0d0-988f45a5e3cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687191036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.3687191036
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.990013099
Short name T805
Test name
Test status
Simulation time 2153192527 ps
CPU time 0.92 seconds
Started Mar 14 01:13:44 PM PDT 24
Finished Mar 14 01:13:45 PM PDT 24
Peak memory 200628 kb
Host smart-cd0db1af-4d44-4beb-aa96-b5d92e932d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990013099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test
.990013099
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2103988651
Short name T863
Test name
Test status
Simulation time 4585563745 ps
CPU time 3.19 seconds
Started Mar 14 01:13:39 PM PDT 24
Finished Mar 14 01:13:43 PM PDT 24
Peak memory 201320 kb
Host smart-ba7c5bfa-8b1d-4049-aea1-1a66ea7d9335
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103988651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.2103988651
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1526422566
Short name T854
Test name
Test status
Simulation time 2024406007 ps
CPU time 6.67 seconds
Started Mar 14 01:13:36 PM PDT 24
Finished Mar 14 01:13:44 PM PDT 24
Peak memory 201120 kb
Host smart-af2f4ac4-69ab-4ea5-b980-fa64e24cf41a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526422566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.1526422566
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.427838163
Short name T880
Test name
Test status
Simulation time 22201999750 ps
CPU time 63.14 seconds
Started Mar 14 01:13:43 PM PDT 24
Finished Mar 14 01:14:47 PM PDT 24
Peak memory 201360 kb
Host smart-697cd118-57de-4d24-8668-89c329ba9313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427838163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_tl_intg_err.427838163
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3203793019
Short name T357
Test name
Test status
Simulation time 3285194320 ps
CPU time 4.77 seconds
Started Mar 14 01:13:37 PM PDT 24
Finished Mar 14 01:13:42 PM PDT 24
Peak memory 201256 kb
Host smart-21d2c50c-84b1-4673-997e-2f20c400c2fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203793019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.3203793019
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3866079565
Short name T344
Test name
Test status
Simulation time 4014857485 ps
CPU time 10.46 seconds
Started Mar 14 01:13:35 PM PDT 24
Finished Mar 14 01:13:46 PM PDT 24
Peak memory 201172 kb
Host smart-0770fb4b-9664-4f33-965f-91b3a3c05a94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866079565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.3866079565
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2813675497
Short name T837
Test name
Test status
Simulation time 2165678061 ps
CPU time 3.19 seconds
Started Mar 14 01:13:37 PM PDT 24
Finished Mar 14 01:13:41 PM PDT 24
Peak memory 209548 kb
Host smart-46297436-29fc-4e6c-b4e5-dc2cf3d4e9db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813675497 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2813675497
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.652379406
Short name T887
Test name
Test status
Simulation time 2030719684 ps
CPU time 5.66 seconds
Started Mar 14 01:13:38 PM PDT 24
Finished Mar 14 01:13:43 PM PDT 24
Peak memory 201084 kb
Host smart-6f523cef-0aa8-4ee2-b4b0-8c6c1c76c715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652379406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw
.652379406
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.731514401
Short name T902
Test name
Test status
Simulation time 2012262950 ps
CPU time 5.79 seconds
Started Mar 14 01:13:44 PM PDT 24
Finished Mar 14 01:13:50 PM PDT 24
Peak memory 200548 kb
Host smart-4171bfae-af59-4d67-873e-1e1136a4ede8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731514401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test
.731514401
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1555010515
Short name T915
Test name
Test status
Simulation time 7412117178 ps
CPU time 19.59 seconds
Started Mar 14 01:13:37 PM PDT 24
Finished Mar 14 01:13:57 PM PDT 24
Peak memory 201264 kb
Host smart-a8fd349f-0fa6-49e5-8db7-7139b8f5fa72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555010515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.1555010515
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1973099082
Short name T812
Test name
Test status
Simulation time 2315194978 ps
CPU time 2.39 seconds
Started Mar 14 01:13:39 PM PDT 24
Finished Mar 14 01:13:43 PM PDT 24
Peak memory 201200 kb
Host smart-21d13c25-0ffe-4983-906d-982e219b8ef5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973099082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.1973099082
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1897047907
Short name T877
Test name
Test status
Simulation time 42481673481 ps
CPU time 102.89 seconds
Started Mar 14 01:13:41 PM PDT 24
Finished Mar 14 01:15:24 PM PDT 24
Peak memory 201276 kb
Host smart-70e19f0f-dfe2-4345-a07d-0c9341ee490e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897047907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.1897047907
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.916619709
Short name T34
Test name
Test status
Simulation time 2060845248 ps
CPU time 5.81 seconds
Started Mar 14 01:13:50 PM PDT 24
Finished Mar 14 01:13:56 PM PDT 24
Peak memory 201156 kb
Host smart-95e9c90d-1d82-4cdc-9e43-323400dede5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916619709 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.916619709
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3686437518
Short name T872
Test name
Test status
Simulation time 2071760511 ps
CPU time 2.02 seconds
Started Mar 14 01:13:53 PM PDT 24
Finished Mar 14 01:13:55 PM PDT 24
Peak memory 201096 kb
Host smart-b879d167-b6c8-4b8b-a5ad-22dc1a62d5f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686437518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3686437518
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2791584267
Short name T879
Test name
Test status
Simulation time 2010575653 ps
CPU time 5.99 seconds
Started Mar 14 01:13:52 PM PDT 24
Finished Mar 14 01:13:58 PM PDT 24
Peak memory 200592 kb
Host smart-9badc3c3-e8fe-4d7f-bd13-cddd968499e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791584267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.2791584267
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.221028517
Short name T839
Test name
Test status
Simulation time 8491289237 ps
CPU time 5.48 seconds
Started Mar 14 01:13:50 PM PDT 24
Finished Mar 14 01:13:56 PM PDT 24
Peak memory 201324 kb
Host smart-e8275908-b643-43c5-8210-10d9ea0747bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221028517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_same_csr_outstanding.221028517
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1493707443
Short name T851
Test name
Test status
Simulation time 42423606808 ps
CPU time 112.78 seconds
Started Mar 14 01:13:51 PM PDT 24
Finished Mar 14 01:15:44 PM PDT 24
Peak memory 201292 kb
Host smart-94eb41cf-b5e1-4630-817f-2cc47b13e0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493707443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.1493707443
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2567948204
Short name T806
Test name
Test status
Simulation time 2118500878 ps
CPU time 5.84 seconds
Started Mar 14 01:13:57 PM PDT 24
Finished Mar 14 01:14:03 PM PDT 24
Peak memory 201116 kb
Host smart-2fe8c33d-f7ab-4db7-b746-12deb57a342e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567948204 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2567948204
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1372015785
Short name T340
Test name
Test status
Simulation time 2033993466 ps
CPU time 5.87 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:13:55 PM PDT 24
Peak memory 200940 kb
Host smart-cb78b324-574f-4654-926f-7841a53379af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372015785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.1372015785
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.120177243
Short name T862
Test name
Test status
Simulation time 2026914910 ps
CPU time 3.2 seconds
Started Mar 14 01:13:51 PM PDT 24
Finished Mar 14 01:13:54 PM PDT 24
Peak memory 200552 kb
Host smart-9172de78-d141-4d6a-88d1-94b1b11ea7d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120177243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.120177243
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.481977206
Short name T855
Test name
Test status
Simulation time 5155399455 ps
CPU time 3.5 seconds
Started Mar 14 01:13:59 PM PDT 24
Finished Mar 14 01:14:03 PM PDT 24
Peak memory 201292 kb
Host smart-3e52c465-1dc4-4b88-a6ec-230057b11f73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481977206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_same_csr_outstanding.481977206
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.468394316
Short name T836
Test name
Test status
Simulation time 2205486904 ps
CPU time 2.34 seconds
Started Mar 14 01:13:50 PM PDT 24
Finished Mar 14 01:13:53 PM PDT 24
Peak memory 201208 kb
Host smart-c269044e-776d-4168-8953-88ba3e3fd773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468394316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_error
s.468394316
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2541678790
Short name T843
Test name
Test status
Simulation time 22229776711 ps
CPU time 61.71 seconds
Started Mar 14 01:13:48 PM PDT 24
Finished Mar 14 01:14:50 PM PDT 24
Peak memory 201304 kb
Host smart-205f4a5f-e1d7-471c-b793-c48aa2759492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541678790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.2541678790
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2354130675
Short name T913
Test name
Test status
Simulation time 2122834284 ps
CPU time 6.79 seconds
Started Mar 14 01:13:59 PM PDT 24
Finished Mar 14 01:14:06 PM PDT 24
Peak memory 201124 kb
Host smart-2347266a-77d3-43cf-96a3-07659eb01241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354130675 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2354130675
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2831506840
Short name T906
Test name
Test status
Simulation time 2060347051 ps
CPU time 3.56 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:01 PM PDT 24
Peak memory 201092 kb
Host smart-31ff7539-79a8-4605-a0e6-189d7a4788ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831506840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.2831506840
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.4014716947
Short name T823
Test name
Test status
Simulation time 2022174806 ps
CPU time 3.29 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:01 PM PDT 24
Peak memory 200696 kb
Host smart-cfdbb83c-c10f-45d0-9f99-fb8589886bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014716947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.4014716947
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4115036825
Short name T278
Test name
Test status
Simulation time 2224105743 ps
CPU time 4.79 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:03 PM PDT 24
Peak memory 201152 kb
Host smart-5d8a40a6-4142-409c-9da8-bfb381725712
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115036825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.4115036825
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1335893798
Short name T283
Test name
Test status
Simulation time 2135459767 ps
CPU time 6.57 seconds
Started Mar 14 01:14:02 PM PDT 24
Finished Mar 14 01:14:09 PM PDT 24
Peak memory 201164 kb
Host smart-8d75a22e-7acc-4307-8406-ae9916df7cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335893798 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1335893798
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1821849972
Short name T352
Test name
Test status
Simulation time 2069994561 ps
CPU time 1.94 seconds
Started Mar 14 01:13:59 PM PDT 24
Finished Mar 14 01:14:01 PM PDT 24
Peak memory 201052 kb
Host smart-59b4baaa-ed6d-4a5f-8222-e5c28c87656c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821849972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.1821849972
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.648924468
Short name T859
Test name
Test status
Simulation time 2011710940 ps
CPU time 6.12 seconds
Started Mar 14 01:14:01 PM PDT 24
Finished Mar 14 01:14:08 PM PDT 24
Peak memory 200472 kb
Host smart-f376590d-4547-4272-9a4a-2d686861c737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648924468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_tes
t.648924468
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2789033279
Short name T914
Test name
Test status
Simulation time 5123478946 ps
CPU time 6.1 seconds
Started Mar 14 01:14:00 PM PDT 24
Finished Mar 14 01:14:06 PM PDT 24
Peak memory 201284 kb
Host smart-65512122-4647-48d3-aa94-69a8576a8c2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789033279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.2789033279
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.211366439
Short name T850
Test name
Test status
Simulation time 2120097230 ps
CPU time 3.05 seconds
Started Mar 14 01:14:00 PM PDT 24
Finished Mar 14 01:14:03 PM PDT 24
Peak memory 209380 kb
Host smart-46d8f3a5-6b01-4c0f-b066-a9d6cba170cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211366439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.211366439
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3828128704
Short name T878
Test name
Test status
Simulation time 42392974178 ps
CPU time 60.22 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:58 PM PDT 24
Peak memory 201248 kb
Host smart-f3b81937-4440-4fad-8f4b-267b95958090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828128704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.3828128704
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2865927068
Short name T810
Test name
Test status
Simulation time 2044051808 ps
CPU time 6.45 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:05 PM PDT 24
Peak memory 200968 kb
Host smart-e9f0c25c-cd99-4b0f-afbf-7fcc0fcb55ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865927068 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2865927068
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.861218084
Short name T349
Test name
Test status
Simulation time 2032015374 ps
CPU time 5.66 seconds
Started Mar 14 01:14:02 PM PDT 24
Finished Mar 14 01:14:08 PM PDT 24
Peak memory 200968 kb
Host smart-169aaebf-b15c-412b-bac9-4362408b5081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861218084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r
w.861218084
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1554332698
Short name T883
Test name
Test status
Simulation time 2012111469 ps
CPU time 6.25 seconds
Started Mar 14 01:13:59 PM PDT 24
Finished Mar 14 01:14:06 PM PDT 24
Peak memory 200560 kb
Host smart-fbd3cda4-15c0-42ff-9f3d-bb052fd9bc71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554332698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1554332698
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.749844857
Short name T20
Test name
Test status
Simulation time 10179896626 ps
CPU time 33.46 seconds
Started Mar 14 01:13:57 PM PDT 24
Finished Mar 14 01:14:31 PM PDT 24
Peak memory 201336 kb
Host smart-cc09cb49-fb26-4c76-9f0c-89e6ef1bf7d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749844857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_same_csr_outstanding.749844857
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3401757305
Short name T834
Test name
Test status
Simulation time 2114892300 ps
CPU time 3.16 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:01 PM PDT 24
Peak memory 201152 kb
Host smart-1d36c30d-c849-4327-9856-f1dbbf10827e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401757305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.3401757305
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.594712781
Short name T273
Test name
Test status
Simulation time 22256245188 ps
CPU time 29.29 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:28 PM PDT 24
Peak memory 201308 kb
Host smart-e830bedd-2757-400a-9329-cc13b01f4985
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594712781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_tl_intg_err.594712781
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2068842342
Short name T900
Test name
Test status
Simulation time 2318443910 ps
CPU time 1.4 seconds
Started Mar 14 01:13:57 PM PDT 24
Finished Mar 14 01:13:59 PM PDT 24
Peak memory 201348 kb
Host smart-dd9cea5e-b7d0-4b35-bfa1-cd2fa4884091
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068842342 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2068842342
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.383355688
Short name T353
Test name
Test status
Simulation time 2047281310 ps
CPU time 3.31 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:01 PM PDT 24
Peak memory 201008 kb
Host smart-6787a9cb-e1a5-4c1c-9564-e6d02832d7bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383355688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_r
w.383355688
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3324527535
Short name T875
Test name
Test status
Simulation time 2019684778 ps
CPU time 3.18 seconds
Started Mar 14 01:13:56 PM PDT 24
Finished Mar 14 01:14:00 PM PDT 24
Peak memory 200552 kb
Host smart-163be103-6463-4e64-bed5-2521b5917c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324527535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.3324527535
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1967174205
Short name T354
Test name
Test status
Simulation time 5100302827 ps
CPU time 13.66 seconds
Started Mar 14 01:14:01 PM PDT 24
Finished Mar 14 01:14:14 PM PDT 24
Peak memory 201300 kb
Host smart-0cf47b2f-7423-40f0-b1f5-bcd66c6f44c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967174205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.1967174205
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1752675939
Short name T815
Test name
Test status
Simulation time 2196522809 ps
CPU time 4.79 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:03 PM PDT 24
Peak memory 201172 kb
Host smart-666cd6a3-f223-4d5c-961d-7a7f53944858
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752675939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.1752675939
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2795329260
Short name T853
Test name
Test status
Simulation time 22450684722 ps
CPU time 16.87 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:15 PM PDT 24
Peak memory 201300 kb
Host smart-7ae192ff-93fc-4702-9563-27cb80b843e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795329260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.2795329260
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1131596752
Short name T847
Test name
Test status
Simulation time 2077501842 ps
CPU time 5.98 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:04 PM PDT 24
Peak memory 201116 kb
Host smart-f970a43e-1e45-436d-b870-f0a92e097203
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131596752 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1131596752
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3094748892
Short name T860
Test name
Test status
Simulation time 2060778342 ps
CPU time 5.85 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:04 PM PDT 24
Peak memory 201120 kb
Host smart-6f9878ea-810f-446c-8d52-610efd2e3d43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094748892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3094748892
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2155614097
Short name T840
Test name
Test status
Simulation time 2053513271 ps
CPU time 1.97 seconds
Started Mar 14 01:13:58 PM PDT 24
Finished Mar 14 01:14:00 PM PDT 24
Peak memory 200504 kb
Host smart-06c211b5-a2ac-49cb-b5f2-41589968e2f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155614097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.2155614097
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2907771082
Short name T895
Test name
Test status
Simulation time 8379737792 ps
CPU time 21.46 seconds
Started Mar 14 01:13:59 PM PDT 24
Finished Mar 14 01:14:20 PM PDT 24
Peak memory 201304 kb
Host smart-409637c2-0f8c-41ed-bd8c-a63398efe0b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907771082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.2907771082
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2195635863
Short name T814
Test name
Test status
Simulation time 2100414699 ps
CPU time 2.99 seconds
Started Mar 14 01:14:00 PM PDT 24
Finished Mar 14 01:14:03 PM PDT 24
Peak memory 201124 kb
Host smart-7216a308-74d7-4720-9707-c1645048d440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195635863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.2195635863
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2283055737
Short name T828
Test name
Test status
Simulation time 22561938271 ps
CPU time 11.32 seconds
Started Mar 14 01:14:01 PM PDT 24
Finished Mar 14 01:14:13 PM PDT 24
Peak memory 201360 kb
Host smart-b50df94d-7093-4a23-9e93-8e55cb02fddf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283055737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.2283055737
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2468997649
Short name T281
Test name
Test status
Simulation time 2232742107 ps
CPU time 1.99 seconds
Started Mar 14 01:14:18 PM PDT 24
Finished Mar 14 01:14:20 PM PDT 24
Peak memory 209568 kb
Host smart-b44f55aa-fe47-43b5-a749-bfa8d2f648b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468997649 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2468997649
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.4256274289
Short name T894
Test name
Test status
Simulation time 2122362204 ps
CPU time 2.21 seconds
Started Mar 14 01:14:15 PM PDT 24
Finished Mar 14 01:14:18 PM PDT 24
Peak memory 201088 kb
Host smart-9323a023-3582-4a9f-83bf-18653e44106e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256274289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.4256274289
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.172546803
Short name T824
Test name
Test status
Simulation time 2053967063 ps
CPU time 1.72 seconds
Started Mar 14 01:14:14 PM PDT 24
Finished Mar 14 01:14:16 PM PDT 24
Peak memory 200636 kb
Host smart-facce427-caff-40c9-be42-2a4b6c7edced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172546803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_tes
t.172546803
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.145737080
Short name T861
Test name
Test status
Simulation time 5651612266 ps
CPU time 15.48 seconds
Started Mar 14 01:14:15 PM PDT 24
Finished Mar 14 01:14:31 PM PDT 24
Peak memory 201344 kb
Host smart-e487d8b9-3794-46aa-8349-6115a2a6c46e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145737080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.145737080
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.4150045746
Short name T266
Test name
Test status
Simulation time 2085498972 ps
CPU time 7.48 seconds
Started Mar 14 01:14:11 PM PDT 24
Finished Mar 14 01:14:18 PM PDT 24
Peak memory 201120 kb
Host smart-db39a139-1656-4e81-ad75-8f3c4a037082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150045746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.4150045746
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.474585964
Short name T369
Test name
Test status
Simulation time 42370355158 ps
CPU time 61.26 seconds
Started Mar 14 01:14:11 PM PDT 24
Finished Mar 14 01:15:13 PM PDT 24
Peak memory 201260 kb
Host smart-2e3ce41a-1b49-4299-8bfa-681f5daea846
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474585964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_tl_intg_err.474585964
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3711972954
Short name T842
Test name
Test status
Simulation time 2055049283 ps
CPU time 5.65 seconds
Started Mar 14 01:14:13 PM PDT 24
Finished Mar 14 01:14:19 PM PDT 24
Peak memory 201164 kb
Host smart-8ea27c92-702c-4ccd-a699-4dbd73b44d9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711972954 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3711972954
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1129087249
Short name T865
Test name
Test status
Simulation time 2033609566 ps
CPU time 6.43 seconds
Started Mar 14 01:14:14 PM PDT 24
Finished Mar 14 01:14:21 PM PDT 24
Peak memory 201108 kb
Host smart-370df6dc-6689-4832-87d8-5708b3f262a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129087249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.1129087249
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.891538532
Short name T835
Test name
Test status
Simulation time 2036773217 ps
CPU time 2.01 seconds
Started Mar 14 01:14:16 PM PDT 24
Finished Mar 14 01:14:18 PM PDT 24
Peak memory 200604 kb
Host smart-106a8adf-c800-484c-bea1-eb17ae6f0b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891538532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_tes
t.891538532
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2401007429
Short name T905
Test name
Test status
Simulation time 7759245568 ps
CPU time 19.73 seconds
Started Mar 14 01:14:15 PM PDT 24
Finished Mar 14 01:14:35 PM PDT 24
Peak memory 201212 kb
Host smart-fc120b72-d109-46a8-9f58-639ef8b6e6af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401007429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.2401007429
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3738863471
Short name T827
Test name
Test status
Simulation time 22384344297 ps
CPU time 19.25 seconds
Started Mar 14 01:14:12 PM PDT 24
Finished Mar 14 01:14:32 PM PDT 24
Peak memory 201276 kb
Host smart-bf0baf87-fad0-4d60-88a9-7029ff8c1613
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738863471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.3738863471
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3398648123
Short name T821
Test name
Test status
Simulation time 2141568758 ps
CPU time 3.8 seconds
Started Mar 14 01:14:17 PM PDT 24
Finished Mar 14 01:14:21 PM PDT 24
Peak memory 201120 kb
Host smart-f5d35c90-dfae-44f5-b390-12ff4728595d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398648123 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3398648123
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3851176339
Short name T829
Test name
Test status
Simulation time 2019651147 ps
CPU time 3.15 seconds
Started Mar 14 01:14:13 PM PDT 24
Finished Mar 14 01:14:16 PM PDT 24
Peak memory 200504 kb
Host smart-a261f399-8435-4918-b648-3e30994cbb73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851176339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.3851176339
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2756867646
Short name T896
Test name
Test status
Simulation time 10891259655 ps
CPU time 28.85 seconds
Started Mar 14 01:14:14 PM PDT 24
Finished Mar 14 01:14:43 PM PDT 24
Peak memory 201244 kb
Host smart-cddeb330-1f5d-492d-8993-0e37fd7d0065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756867646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.2756867646
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.612732553
Short name T818
Test name
Test status
Simulation time 2067339392 ps
CPU time 7.09 seconds
Started Mar 14 01:14:12 PM PDT 24
Finished Mar 14 01:14:19 PM PDT 24
Peak memory 201108 kb
Host smart-24a8ee78-58fc-44bb-b468-79f0266b5d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612732553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_error
s.612732553
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1217771672
Short name T901
Test name
Test status
Simulation time 22168442050 ps
CPU time 61.63 seconds
Started Mar 14 01:14:16 PM PDT 24
Finished Mar 14 01:15:18 PM PDT 24
Peak memory 201356 kb
Host smart-a8cca763-491c-46a1-b78f-7268e3c19ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217771672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.1217771672
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2645269213
Short name T33
Test name
Test status
Simulation time 3175083172 ps
CPU time 10.17 seconds
Started Mar 14 01:13:37 PM PDT 24
Finished Mar 14 01:13:48 PM PDT 24
Peak memory 201312 kb
Host smart-c33f7094-db89-403d-9d34-a01dbffd0102
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645269213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.2645269213
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3823125881
Short name T388
Test name
Test status
Simulation time 39800075542 ps
CPU time 100.05 seconds
Started Mar 14 01:13:36 PM PDT 24
Finished Mar 14 01:15:18 PM PDT 24
Peak memory 201332 kb
Host smart-8ef0188c-4798-4866-9d07-5cad30ffe16f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823125881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.3823125881
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2928591061
Short name T342
Test name
Test status
Simulation time 4010805575 ps
CPU time 11.92 seconds
Started Mar 14 01:13:35 PM PDT 24
Finished Mar 14 01:13:48 PM PDT 24
Peak memory 201096 kb
Host smart-0ee3dd19-6724-4fc6-ad8d-54f448347209
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928591061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.2928591061
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2241131208
Short name T282
Test name
Test status
Simulation time 2073892873 ps
CPU time 6.19 seconds
Started Mar 14 01:13:39 PM PDT 24
Finished Mar 14 01:13:46 PM PDT 24
Peak memory 201072 kb
Host smart-60d965d8-82d5-4270-a526-8ffc3de378f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241131208 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2241131208
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.720488622
Short name T348
Test name
Test status
Simulation time 2041580830 ps
CPU time 6.09 seconds
Started Mar 14 01:13:36 PM PDT 24
Finished Mar 14 01:13:43 PM PDT 24
Peak memory 200992 kb
Host smart-8e5154fb-848c-4f29-9d67-0c111d4e8bc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720488622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw
.720488622
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3701525732
Short name T813
Test name
Test status
Simulation time 2018304904 ps
CPU time 3.17 seconds
Started Mar 14 01:13:39 PM PDT 24
Finished Mar 14 01:13:43 PM PDT 24
Peak memory 200536 kb
Host smart-5fd9762a-6c91-4d6b-8560-49418f22d447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701525732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.3701525732
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2671851557
Short name T848
Test name
Test status
Simulation time 3606997169 ps
CPU time 4.62 seconds
Started Mar 14 01:13:36 PM PDT 24
Finished Mar 14 01:13:41 PM PDT 24
Peak memory 201120 kb
Host smart-fa74dc5e-23d4-42cc-9436-966f3990619e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671851557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.2671851557
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.694919347
Short name T277
Test name
Test status
Simulation time 2045133316 ps
CPU time 6.65 seconds
Started Mar 14 01:13:36 PM PDT 24
Finished Mar 14 01:13:44 PM PDT 24
Peak memory 201136 kb
Host smart-cf5cfb6d-f2ca-4796-85e0-f23f0ad73dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694919347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors
.694919347
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.801946260
Short name T795
Test name
Test status
Simulation time 2012921422 ps
CPU time 5.55 seconds
Started Mar 14 01:14:11 PM PDT 24
Finished Mar 14 01:14:16 PM PDT 24
Peak memory 200492 kb
Host smart-01e65548-6dac-4fb4-a7ab-f58b3547d230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801946260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_tes
t.801946260
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1873219368
Short name T857
Test name
Test status
Simulation time 2020744092 ps
CPU time 3.26 seconds
Started Mar 14 01:14:11 PM PDT 24
Finished Mar 14 01:14:14 PM PDT 24
Peak memory 200556 kb
Host smart-b1f3d90e-7438-43fd-85a5-094976bf1726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873219368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.1873219368
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2734424587
Short name T816
Test name
Test status
Simulation time 2078542625 ps
CPU time 1.34 seconds
Started Mar 14 01:14:12 PM PDT 24
Finished Mar 14 01:14:13 PM PDT 24
Peak memory 200524 kb
Host smart-dd03116f-ad97-4645-b63e-08394acd29e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734424587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.2734424587
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4228925106
Short name T897
Test name
Test status
Simulation time 2015803338 ps
CPU time 5.76 seconds
Started Mar 14 01:14:15 PM PDT 24
Finished Mar 14 01:14:21 PM PDT 24
Peak memory 200512 kb
Host smart-639cb278-b5a5-4515-87a7-fc5d09e2caa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228925106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.4228925106
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1509731819
Short name T820
Test name
Test status
Simulation time 2009938882 ps
CPU time 6.07 seconds
Started Mar 14 01:14:10 PM PDT 24
Finished Mar 14 01:14:16 PM PDT 24
Peak memory 200564 kb
Host smart-da074d2b-b1f0-47d0-8a62-7f1b51cb33df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509731819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1509731819
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.647001611
Short name T804
Test name
Test status
Simulation time 2010217868 ps
CPU time 5.87 seconds
Started Mar 14 01:14:11 PM PDT 24
Finished Mar 14 01:14:17 PM PDT 24
Peak memory 200520 kb
Host smart-52bd1cbc-e9b6-4841-bb55-bb14dbac85a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647001611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_tes
t.647001611
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1885466856
Short name T858
Test name
Test status
Simulation time 2060020277 ps
CPU time 1.03 seconds
Started Mar 14 01:14:14 PM PDT 24
Finished Mar 14 01:14:15 PM PDT 24
Peak memory 200472 kb
Host smart-a334f8f1-8d68-4e94-8308-5cdf78d45fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885466856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.1885466856
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.985082846
Short name T889
Test name
Test status
Simulation time 2012092923 ps
CPU time 5.76 seconds
Started Mar 14 01:14:17 PM PDT 24
Finished Mar 14 01:14:23 PM PDT 24
Peak memory 200464 kb
Host smart-e7666c36-107d-4557-ad0b-55821bbb8eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985082846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_tes
t.985082846
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2177645791
Short name T799
Test name
Test status
Simulation time 2033822683 ps
CPU time 2.04 seconds
Started Mar 14 01:14:14 PM PDT 24
Finished Mar 14 01:14:16 PM PDT 24
Peak memory 200516 kb
Host smart-9b2d3c2c-d913-40e9-b7ff-456345d8d113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177645791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.2177645791
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1658580802
Short name T890
Test name
Test status
Simulation time 2029638155 ps
CPU time 2.54 seconds
Started Mar 14 01:14:17 PM PDT 24
Finished Mar 14 01:14:19 PM PDT 24
Peak memory 200460 kb
Host smart-59da57c2-83c4-4311-b54d-866bf6ac6e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658580802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.1658580802
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.4124170792
Short name T831
Test name
Test status
Simulation time 3166972508 ps
CPU time 11.65 seconds
Started Mar 14 01:13:38 PM PDT 24
Finished Mar 14 01:13:50 PM PDT 24
Peak memory 201232 kb
Host smart-a3691e6e-1e33-4ed8-9300-e88c098843c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124170792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.4124170792
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2077044103
Short name T346
Test name
Test status
Simulation time 42851648187 ps
CPU time 32.27 seconds
Started Mar 14 01:13:38 PM PDT 24
Finished Mar 14 01:14:11 PM PDT 24
Peak memory 201328 kb
Host smart-8bac4742-c6ee-4f7e-b8dd-59c2c52ca0fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077044103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.2077044103
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1933563151
Short name T864
Test name
Test status
Simulation time 4058885713 ps
CPU time 3.29 seconds
Started Mar 14 01:13:37 PM PDT 24
Finished Mar 14 01:13:41 PM PDT 24
Peak memory 201132 kb
Host smart-8db1ef7a-08ee-4083-af8f-52d4a2d40e6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933563151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.1933563151
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3423740531
Short name T386
Test name
Test status
Simulation time 2148190224 ps
CPU time 3.86 seconds
Started Mar 14 01:13:37 PM PDT 24
Finished Mar 14 01:13:41 PM PDT 24
Peak memory 201220 kb
Host smart-40539a99-339f-464f-afba-5858733dfb1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423740531 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3423740531
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1353148352
Short name T24
Test name
Test status
Simulation time 2051573275 ps
CPU time 6.51 seconds
Started Mar 14 01:13:37 PM PDT 24
Finished Mar 14 01:13:44 PM PDT 24
Peak memory 201076 kb
Host smart-f9417bac-7783-4a87-82ad-88d7bad8136e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353148352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.1353148352
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.4204574859
Short name T849
Test name
Test status
Simulation time 2030890006 ps
CPU time 1.8 seconds
Started Mar 14 01:13:31 PM PDT 24
Finished Mar 14 01:13:33 PM PDT 24
Peak memory 200560 kb
Host smart-f78393c3-89dc-49bc-bb09-4919067bfee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204574859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.4204574859
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3246562479
Short name T355
Test name
Test status
Simulation time 4789879450 ps
CPU time 1.77 seconds
Started Mar 14 01:13:39 PM PDT 24
Finished Mar 14 01:13:42 PM PDT 24
Peak memory 201220 kb
Host smart-105a5a44-a9d8-437f-ac67-fe1fcf9e113e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246562479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.3246562479
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2985484448
Short name T274
Test name
Test status
Simulation time 2036384797 ps
CPU time 7.57 seconds
Started Mar 14 01:13:36 PM PDT 24
Finished Mar 14 01:13:45 PM PDT 24
Peak memory 201164 kb
Host smart-83d40e8a-f09e-4ab4-98fc-5a3fec873635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985484448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.2985484448
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1111060902
Short name T370
Test name
Test status
Simulation time 22500180289 ps
CPU time 14.04 seconds
Started Mar 14 01:13:38 PM PDT 24
Finished Mar 14 01:13:53 PM PDT 24
Peak memory 201292 kb
Host smart-bd19fbb3-8bee-4f3e-8bc1-4567395fb04e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111060902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.1111060902
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.409929277
Short name T891
Test name
Test status
Simulation time 2016224742 ps
CPU time 6.05 seconds
Started Mar 14 01:14:15 PM PDT 24
Finished Mar 14 01:14:21 PM PDT 24
Peak memory 200516 kb
Host smart-a09054aa-4393-4528-ac0c-a113f5674e3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409929277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_tes
t.409929277
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1448532594
Short name T871
Test name
Test status
Simulation time 2012829783 ps
CPU time 5.88 seconds
Started Mar 14 01:14:11 PM PDT 24
Finished Mar 14 01:14:17 PM PDT 24
Peak memory 200556 kb
Host smart-005186d3-6fdd-48be-aeda-7faa3b5be3b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448532594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.1448532594
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3584279636
Short name T868
Test name
Test status
Simulation time 2008448246 ps
CPU time 5.68 seconds
Started Mar 14 01:14:16 PM PDT 24
Finished Mar 14 01:14:22 PM PDT 24
Peak memory 200532 kb
Host smart-758d6232-46e8-47c6-9ad8-b177af050097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584279636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.3584279636
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.149271761
Short name T888
Test name
Test status
Simulation time 2014929610 ps
CPU time 3.38 seconds
Started Mar 14 01:14:16 PM PDT 24
Finished Mar 14 01:14:19 PM PDT 24
Peak memory 200520 kb
Host smart-f5012f3f-7438-4aac-8264-ccf94670dfc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149271761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_tes
t.149271761
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2289318078
Short name T800
Test name
Test status
Simulation time 2023348606 ps
CPU time 2.01 seconds
Started Mar 14 01:14:10 PM PDT 24
Finished Mar 14 01:14:12 PM PDT 24
Peak memory 200480 kb
Host smart-6f88f04f-e0f2-4318-b723-2ba8ee0d64bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289318078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.2289318078
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3189646562
Short name T807
Test name
Test status
Simulation time 2037284814 ps
CPU time 1.92 seconds
Started Mar 14 01:14:14 PM PDT 24
Finished Mar 14 01:14:16 PM PDT 24
Peak memory 200484 kb
Host smart-f2c20bbe-873c-4d07-98db-241bab9379ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189646562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.3189646562
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.560838445
Short name T899
Test name
Test status
Simulation time 2014525863 ps
CPU time 5.74 seconds
Started Mar 14 01:14:16 PM PDT 24
Finished Mar 14 01:14:22 PM PDT 24
Peak memory 200556 kb
Host smart-63749a3d-ca87-4cbb-b4d1-71a879043054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560838445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_tes
t.560838445
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3308544087
Short name T852
Test name
Test status
Simulation time 2012925614 ps
CPU time 5.28 seconds
Started Mar 14 01:14:16 PM PDT 24
Finished Mar 14 01:14:22 PM PDT 24
Peak memory 200504 kb
Host smart-740368f4-bae6-4c01-90fa-8e8b710d3d4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308544087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.3308544087
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1533698058
Short name T832
Test name
Test status
Simulation time 2010564928 ps
CPU time 5.76 seconds
Started Mar 14 01:14:17 PM PDT 24
Finished Mar 14 01:14:22 PM PDT 24
Peak memory 200524 kb
Host smart-03976911-65f0-4a6a-be49-2d314cd69c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533698058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te
st.1533698058
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2319148665
Short name T797
Test name
Test status
Simulation time 2058580322 ps
CPU time 1.74 seconds
Started Mar 14 01:14:14 PM PDT 24
Finished Mar 14 01:14:15 PM PDT 24
Peak memory 200564 kb
Host smart-e3f8b97f-2634-4e53-8a52-4e244f5c5f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319148665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.2319148665
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.888056
Short name T846
Test name
Test status
Simulation time 2818102145 ps
CPU time 6.67 seconds
Started Mar 14 01:13:41 PM PDT 24
Finished Mar 14 01:13:48 PM PDT 24
Peak memory 201184 kb
Host smart-6f066d3f-faa4-4a3c-ae5d-a7e465d264bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr
_aliasing.888056
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1895498779
Short name T343
Test name
Test status
Simulation time 38790017701 ps
CPU time 62.43 seconds
Started Mar 14 01:13:55 PM PDT 24
Finished Mar 14 01:14:57 PM PDT 24
Peak memory 201320 kb
Host smart-f6f88aa8-0caa-45b9-8ccc-42ff6d446601
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895498779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.1895498779
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2338410624
Short name T867
Test name
Test status
Simulation time 6029120854 ps
CPU time 16.27 seconds
Started Mar 14 01:13:40 PM PDT 24
Finished Mar 14 01:13:56 PM PDT 24
Peak memory 201192 kb
Host smart-d1edcbb4-475d-4f6a-a046-7b715e7c7500
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338410624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.2338410624
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.71029971
Short name T826
Test name
Test status
Simulation time 2087557123 ps
CPU time 6.76 seconds
Started Mar 14 01:13:51 PM PDT 24
Finished Mar 14 01:13:58 PM PDT 24
Peak memory 201108 kb
Host smart-02ed7c6d-047f-413f-b936-9e02b3f30d37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71029971 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.71029971
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2541440888
Short name T908
Test name
Test status
Simulation time 2073027746 ps
CPU time 2.28 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:13:51 PM PDT 24
Peak memory 200972 kb
Host smart-ad446333-8551-4abf-9869-aee533ce8d10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541440888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.2541440888
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2501810036
Short name T885
Test name
Test status
Simulation time 2031698354 ps
CPU time 1.83 seconds
Started Mar 14 01:13:36 PM PDT 24
Finished Mar 14 01:13:39 PM PDT 24
Peak memory 200556 kb
Host smart-05bde343-c843-49aa-b53a-970ee003d140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501810036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.2501810036
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2061299623
Short name T856
Test name
Test status
Simulation time 4797019119 ps
CPU time 1.73 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:13:51 PM PDT 24
Peak memory 201204 kb
Host smart-61921023-6f2c-431f-a47b-713899081810
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061299623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.2061299623
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.56106104
Short name T830
Test name
Test status
Simulation time 2025739336 ps
CPU time 6.61 seconds
Started Mar 14 01:13:38 PM PDT 24
Finished Mar 14 01:13:45 PM PDT 24
Peak memory 201080 kb
Host smart-7f7adc96-9a7e-4d61-9478-556f9761f26b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56106104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.56106104
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.320121861
Short name T873
Test name
Test status
Simulation time 22437514620 ps
CPU time 17.1 seconds
Started Mar 14 01:13:38 PM PDT 24
Finished Mar 14 01:13:56 PM PDT 24
Peak memory 201260 kb
Host smart-36db92c5-8b92-4dad-91c3-6800501e744b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320121861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_tl_intg_err.320121861
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.841824936
Short name T892
Test name
Test status
Simulation time 2008934462 ps
CPU time 5.86 seconds
Started Mar 14 01:14:16 PM PDT 24
Finished Mar 14 01:14:22 PM PDT 24
Peak memory 200556 kb
Host smart-dfe81c88-79cf-4d1d-9c2e-5cf4c54c61d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841824936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_tes
t.841824936
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1512292577
Short name T811
Test name
Test status
Simulation time 2012820551 ps
CPU time 5.49 seconds
Started Mar 14 01:14:15 PM PDT 24
Finished Mar 14 01:14:21 PM PDT 24
Peak memory 200492 kb
Host smart-d7ebf776-ba48-423e-9de3-52a5c003b9ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512292577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.1512292577
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2117580600
Short name T798
Test name
Test status
Simulation time 2016084683 ps
CPU time 5.78 seconds
Started Mar 14 01:14:17 PM PDT 24
Finished Mar 14 01:14:23 PM PDT 24
Peak memory 200556 kb
Host smart-c55e486d-1daf-4321-9df1-34b5891da2c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117580600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.2117580600
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.700950295
Short name T874
Test name
Test status
Simulation time 2019915582 ps
CPU time 3.18 seconds
Started Mar 14 01:14:17 PM PDT 24
Finished Mar 14 01:14:20 PM PDT 24
Peak memory 200588 kb
Host smart-5e43215b-17c8-44df-b4dd-876b23b96e45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700950295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.700950295
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1533989517
Short name T809
Test name
Test status
Simulation time 2023153863 ps
CPU time 3.11 seconds
Started Mar 14 01:14:17 PM PDT 24
Finished Mar 14 01:14:20 PM PDT 24
Peak memory 200604 kb
Host smart-7622e187-1a0f-435a-b866-a60f87bf6e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533989517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.1533989517
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.1284517454
Short name T898
Test name
Test status
Simulation time 2041784105 ps
CPU time 2.02 seconds
Started Mar 14 01:14:15 PM PDT 24
Finished Mar 14 01:14:18 PM PDT 24
Peak memory 200556 kb
Host smart-d36ffa03-418b-4ff5-bd83-e99cb6ece58e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284517454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.1284517454
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1784793057
Short name T796
Test name
Test status
Simulation time 2039435835 ps
CPU time 2.16 seconds
Started Mar 14 01:14:18 PM PDT 24
Finished Mar 14 01:14:21 PM PDT 24
Peak memory 200584 kb
Host smart-0b8c0712-55e4-4cc7-9886-d383996be39b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784793057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.1784793057
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3903286101
Short name T893
Test name
Test status
Simulation time 2055978158 ps
CPU time 1.94 seconds
Started Mar 14 01:14:15 PM PDT 24
Finished Mar 14 01:14:17 PM PDT 24
Peak memory 200444 kb
Host smart-1d3171bb-78d3-4053-8f56-a8300e6586b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903286101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3903286101
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.295861366
Short name T802
Test name
Test status
Simulation time 2031123877 ps
CPU time 2.02 seconds
Started Mar 14 01:14:16 PM PDT 24
Finished Mar 14 01:14:19 PM PDT 24
Peak memory 200400 kb
Host smart-32a30644-3307-4e2f-be1e-31ab18a9437a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295861366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_tes
t.295861366
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.3905294736
Short name T833
Test name
Test status
Simulation time 2048592455 ps
CPU time 1.96 seconds
Started Mar 14 01:14:15 PM PDT 24
Finished Mar 14 01:14:17 PM PDT 24
Peak memory 200564 kb
Host smart-f59302d4-098d-4ac9-a410-0c8e9ed27956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905294736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.3905294736
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2331803549
Short name T387
Test name
Test status
Simulation time 2156145225 ps
CPU time 6.2 seconds
Started Mar 14 01:13:54 PM PDT 24
Finished Mar 14 01:14:01 PM PDT 24
Peak memory 201132 kb
Host smart-9df94e1e-7d5b-41b8-ae74-1c9b37c8209c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331803549 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2331803549
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1360881134
Short name T911
Test name
Test status
Simulation time 2066156792 ps
CPU time 2.08 seconds
Started Mar 14 01:13:47 PM PDT 24
Finished Mar 14 01:13:49 PM PDT 24
Peak memory 200992 kb
Host smart-9c3cb39f-c6c4-476f-b41e-5e9f2b39d190
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360881134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.1360881134
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1636384574
Short name T870
Test name
Test status
Simulation time 2025137759 ps
CPU time 3.44 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:13:53 PM PDT 24
Peak memory 200560 kb
Host smart-4fdf9e71-2f51-490b-b096-6ebb16fe3867
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636384574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.1636384574
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3987298859
Short name T22
Test name
Test status
Simulation time 9674615331 ps
CPU time 27.93 seconds
Started Mar 14 01:13:50 PM PDT 24
Finished Mar 14 01:14:18 PM PDT 24
Peak memory 201332 kb
Host smart-61142764-ae1a-4b64-8fee-9450227c4e36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987298859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.3987298859
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3063259192
Short name T275
Test name
Test status
Simulation time 2270118017 ps
CPU time 2.24 seconds
Started Mar 14 01:13:48 PM PDT 24
Finished Mar 14 01:13:50 PM PDT 24
Peak memory 201244 kb
Host smart-7b606001-69b3-4def-86e8-5499dfaff97f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063259192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.3063259192
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.205267582
Short name T904
Test name
Test status
Simulation time 22227340724 ps
CPU time 60.7 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:14:49 PM PDT 24
Peak memory 201296 kb
Host smart-8eb02cc1-b6c2-48a6-87d5-0b8e63bfa77e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205267582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_tl_intg_err.205267582
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2241360373
Short name T909
Test name
Test status
Simulation time 2130288325 ps
CPU time 6.63 seconds
Started Mar 14 01:13:43 PM PDT 24
Finished Mar 14 01:13:50 PM PDT 24
Peak memory 201040 kb
Host smart-78e5923f-b1f4-4b9a-a8b1-4f89d4dd689e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241360373 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2241360373
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3007996135
Short name T23
Test name
Test status
Simulation time 2059019422 ps
CPU time 3.57 seconds
Started Mar 14 01:13:45 PM PDT 24
Finished Mar 14 01:13:48 PM PDT 24
Peak memory 201092 kb
Host smart-d521d4ae-bfe8-405e-830d-f6d5f654d352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007996135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.3007996135
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1741691810
Short name T801
Test name
Test status
Simulation time 2012417812 ps
CPU time 5.9 seconds
Started Mar 14 01:13:48 PM PDT 24
Finished Mar 14 01:13:54 PM PDT 24
Peak memory 200540 kb
Host smart-f8dad473-5d01-4ffc-af35-5b231e5bbf2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741691810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.1741691810
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.140109179
Short name T910
Test name
Test status
Simulation time 7030907945 ps
CPU time 20.48 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:14:10 PM PDT 24
Peak memory 201128 kb
Host smart-62c09aba-39af-44c8-940a-5f6a25637fd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140109179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
sysrst_ctrl_same_csr_outstanding.140109179
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3109791119
Short name T841
Test name
Test status
Simulation time 2032533230 ps
CPU time 6.9 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:13:56 PM PDT 24
Peak memory 201140 kb
Host smart-49e6b2d5-5299-4693-9527-1bf939eb4384
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109791119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.3109791119
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3478409280
Short name T368
Test name
Test status
Simulation time 42778484053 ps
CPU time 31.93 seconds
Started Mar 14 01:13:45 PM PDT 24
Finished Mar 14 01:14:17 PM PDT 24
Peak memory 201276 kb
Host smart-86daf532-4811-48a8-a206-ff31a5085ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478409280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3478409280
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3112912560
Short name T912
Test name
Test status
Simulation time 2308268001 ps
CPU time 1.41 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:13:51 PM PDT 24
Peak memory 201240 kb
Host smart-7e1ffad6-5971-472f-b886-c1a8acfc45bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112912560 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3112912560
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2907304578
Short name T356
Test name
Test status
Simulation time 2051748692 ps
CPU time 6.13 seconds
Started Mar 14 01:13:50 PM PDT 24
Finished Mar 14 01:13:56 PM PDT 24
Peak memory 201088 kb
Host smart-d22485ed-bdd6-4f97-8595-fb10eaba235a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907304578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.2907304578
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.800708638
Short name T822
Test name
Test status
Simulation time 2030874530 ps
CPU time 1.84 seconds
Started Mar 14 01:13:53 PM PDT 24
Finished Mar 14 01:13:55 PM PDT 24
Peak memory 200620 kb
Host smart-01782663-2d74-4feb-95d0-984342a59141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800708638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test
.800708638
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2045530218
Short name T21
Test name
Test status
Simulation time 7394422357 ps
CPU time 5.9 seconds
Started Mar 14 01:13:44 PM PDT 24
Finished Mar 14 01:13:50 PM PDT 24
Peak memory 201256 kb
Host smart-785a04fe-075e-4e3b-991a-b58b33d4e3b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045530218 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2045530218
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1691673596
Short name T907
Test name
Test status
Simulation time 2070729977 ps
CPU time 6.57 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:13:56 PM PDT 24
Peak memory 200928 kb
Host smart-6228f9c2-a9c8-4e4a-8210-27301b2c63c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691673596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1691673596
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2081669732
Short name T869
Test name
Test status
Simulation time 42763838524 ps
CPU time 30.43 seconds
Started Mar 14 01:13:49 PM PDT 24
Finished Mar 14 01:14:19 PM PDT 24
Peak memory 201284 kb
Host smart-e65a79ed-a40b-48ad-93b5-f91205d9d638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081669732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.2081669732
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3002105997
Short name T808
Test name
Test status
Simulation time 2049530669 ps
CPU time 6.08 seconds
Started Mar 14 01:13:52 PM PDT 24
Finished Mar 14 01:13:59 PM PDT 24
Peak memory 201164 kb
Host smart-b211a80d-7901-4841-aa0e-703178173311
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002105997 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3002105997
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.850183047
Short name T345
Test name
Test status
Simulation time 2062431200 ps
CPU time 6.46 seconds
Started Mar 14 01:13:50 PM PDT 24
Finished Mar 14 01:13:57 PM PDT 24
Peak memory 201084 kb
Host smart-61e20f4d-1ef1-422c-9400-d968d009ad6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850183047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw
.850183047
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.883772454
Short name T803
Test name
Test status
Simulation time 2009250934 ps
CPU time 6.1 seconds
Started Mar 14 01:13:50 PM PDT 24
Finished Mar 14 01:13:57 PM PDT 24
Peak memory 200608 kb
Host smart-11e085c6-a34b-4ba5-980a-90818bb22fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883772454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test
.883772454
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2137279016
Short name T881
Test name
Test status
Simulation time 4608294917 ps
CPU time 8.54 seconds
Started Mar 14 01:13:54 PM PDT 24
Finished Mar 14 01:14:03 PM PDT 24
Peak memory 201276 kb
Host smart-d90ea33c-1245-40d0-ada4-3d1f68d7a909
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137279016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.2137279016
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.319344654
Short name T886
Test name
Test status
Simulation time 2129552342 ps
CPU time 3.22 seconds
Started Mar 14 01:13:50 PM PDT 24
Finished Mar 14 01:13:54 PM PDT 24
Peak memory 201068 kb
Host smart-4d188104-288d-4701-a31c-b4c3d8032b16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319344654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors
.319344654
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.987625280
Short name T882
Test name
Test status
Simulation time 42409513977 ps
CPU time 62.9 seconds
Started Mar 14 01:13:50 PM PDT 24
Finished Mar 14 01:14:54 PM PDT 24
Peak memory 201320 kb
Host smart-0eb2497b-0650-41cc-8d95-6ab84a54862e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987625280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_tl_intg_err.987625280
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2560449096
Short name T876
Test name
Test status
Simulation time 2097694643 ps
CPU time 3.61 seconds
Started Mar 14 01:13:52 PM PDT 24
Finished Mar 14 01:13:56 PM PDT 24
Peak memory 201068 kb
Host smart-96303d57-4d90-46aa-bc90-59caa9ea11a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560449096 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2560449096
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.722735809
Short name T347
Test name
Test status
Simulation time 2041295050 ps
CPU time 6.08 seconds
Started Mar 14 01:13:52 PM PDT 24
Finished Mar 14 01:13:59 PM PDT 24
Peak memory 201064 kb
Host smart-988759e5-86f6-40fe-b25c-92f7d45cd188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722735809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw
.722735809
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3516201970
Short name T884
Test name
Test status
Simulation time 2013073758 ps
CPU time 5.51 seconds
Started Mar 14 01:13:55 PM PDT 24
Finished Mar 14 01:14:01 PM PDT 24
Peak memory 200512 kb
Host smart-e9ab9498-ab5d-4277-bc08-0c24817bd92c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516201970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.3516201970
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.3910285434
Short name T845
Test name
Test status
Simulation time 4421525099 ps
CPU time 11.98 seconds
Started Mar 14 01:13:52 PM PDT 24
Finished Mar 14 01:14:04 PM PDT 24
Peak memory 201228 kb
Host smart-9fc6e29d-3aef-4853-971a-7358539adcc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910285434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.3910285434
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.156445439
Short name T276
Test name
Test status
Simulation time 2074890657 ps
CPU time 4.77 seconds
Started Mar 14 01:13:51 PM PDT 24
Finished Mar 14 01:13:56 PM PDT 24
Peak memory 209368 kb
Host smart-357ffd74-511c-4bf8-8ece-9c6a64621639
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156445439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors
.156445439
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.566961157
Short name T903
Test name
Test status
Simulation time 42595761555 ps
CPU time 62.14 seconds
Started Mar 14 01:13:55 PM PDT 24
Finished Mar 14 01:14:57 PM PDT 24
Peak memory 201300 kb
Host smart-5ab44abc-6d2a-4135-aee0-80a86a2bfc1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566961157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_tl_intg_err.566961157
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.1660637806
Short name T77
Test name
Test status
Simulation time 2029349880 ps
CPU time 1.93 seconds
Started Mar 14 01:27:48 PM PDT 24
Finished Mar 14 01:27:51 PM PDT 24
Peak memory 201248 kb
Host smart-51937ef5-8644-4d9e-b5e3-fc7970a26060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660637806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.1660637806
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2908432184
Short name T297
Test name
Test status
Simulation time 3161910257 ps
CPU time 8.67 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:28:01 PM PDT 24
Peak memory 201220 kb
Host smart-03f3042a-a3bd-40b6-89fb-f14d5d52f22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908432184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.2908432184
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.657801361
Short name T252
Test name
Test status
Simulation time 82343256641 ps
CPU time 87.01 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:29:21 PM PDT 24
Peak memory 201420 kb
Host smart-fda1aee5-38d1-4bb7-ad72-26a4ceacba2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657801361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_combo_detect.657801361
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4257077340
Short name T652
Test name
Test status
Simulation time 2252202846 ps
CPU time 5.99 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:28:00 PM PDT 24
Peak memory 201216 kb
Host smart-4caa22ff-4aa9-4c1b-8129-b2158c1dd662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257077340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.4257077340
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3207957530
Short name T777
Test name
Test status
Simulation time 2344961680 ps
CPU time 6.81 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:03 PM PDT 24
Peak memory 200924 kb
Host smart-39295fc0-786f-4bd2-9d62-414602fdffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207957530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3207957530
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2593376390
Short name T250
Test name
Test status
Simulation time 90862810915 ps
CPU time 59.77 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:28:52 PM PDT 24
Peak memory 201396 kb
Host smart-9175bc74-3a63-4d23-86d3-f35760072d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593376390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.2593376390
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.33319571
Short name T651
Test name
Test status
Simulation time 440796432383 ps
CPU time 1159.35 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:47:15 PM PDT 24
Peak memory 201220 kb
Host smart-056226aa-a721-453f-9128-4b5c6c202b54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33319571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_ec_pwr_on_rst.33319571
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2003624620
Short name T3
Test name
Test status
Simulation time 4638077423 ps
CPU time 6.01 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:28:00 PM PDT 24
Peak memory 201192 kb
Host smart-40790766-092e-4197-8cad-0788b1681a5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003624620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.2003624620
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2071408332
Short name T226
Test name
Test status
Simulation time 2629274309 ps
CPU time 2.25 seconds
Started Mar 14 01:27:50 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 201188 kb
Host smart-fe8c7d84-0cd5-4cc7-a989-89f488e81c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071408332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.2071408332
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2515070107
Short name T328
Test name
Test status
Simulation time 2467748734 ps
CPU time 3.8 seconds
Started Mar 14 01:27:51 PM PDT 24
Finished Mar 14 01:27:55 PM PDT 24
Peak memory 200580 kb
Host smart-7e2684da-03a6-4829-929c-f514adb8552d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515070107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.2515070107
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1481626285
Short name T451
Test name
Test status
Simulation time 2098323459 ps
CPU time 2.05 seconds
Started Mar 14 01:27:48 PM PDT 24
Finished Mar 14 01:27:50 PM PDT 24
Peak memory 201084 kb
Host smart-9913fd97-7878-499f-8214-f9df17ac7f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481626285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1481626285
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.568816559
Short name T69
Test name
Test status
Simulation time 2529823946 ps
CPU time 2.55 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:27:56 PM PDT 24
Peak memory 201280 kb
Host smart-99a467fb-411e-4f63-ae3c-acaea906303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568816559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.568816559
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.968813839
Short name T628
Test name
Test status
Simulation time 2137051940 ps
CPU time 1.97 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:27:54 PM PDT 24
Peak memory 201088 kb
Host smart-a32c8c3f-b2d9-4608-a3b4-8b2beb78ecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968813839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.968813839
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.3046732074
Short name T462
Test name
Test status
Simulation time 7074380816 ps
CPU time 5.64 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:02 PM PDT 24
Peak memory 200916 kb
Host smart-1c7d3528-9a83-49d9-a9c5-6f7f200c7d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046732074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.3046732074
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2133054799
Short name T111
Test name
Test status
Simulation time 2863357306 ps
CPU time 4.44 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:27:57 PM PDT 24
Peak memory 200672 kb
Host smart-43801372-0fc2-4aa9-ad1e-af76ad0b010d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133054799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.2133054799
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.509244186
Short name T698
Test name
Test status
Simulation time 2008782571 ps
CPU time 5.84 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:27:59 PM PDT 24
Peak memory 201284 kb
Host smart-29366420-e2a3-4632-b1d9-0122cd3d959b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509244186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test
.509244186
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.2642956808
Short name T653
Test name
Test status
Simulation time 75831373476 ps
CPU time 47.93 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:28:42 PM PDT 24
Peak memory 201248 kb
Host smart-f053d28b-0904-4c0d-8ac5-5b14adb4d97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642956808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.2642956808
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.485525301
Short name T103
Test name
Test status
Simulation time 122079690717 ps
CPU time 330.14 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:33:25 PM PDT 24
Peak memory 201448 kb
Host smart-735ab46e-86d1-4f90-9555-acf2f9617d13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485525301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_combo_detect.485525301
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2421076518
Short name T558
Test name
Test status
Simulation time 2410999164 ps
CPU time 3.46 seconds
Started Mar 14 01:27:51 PM PDT 24
Finished Mar 14 01:27:55 PM PDT 24
Peak memory 201152 kb
Host smart-eaf3a95d-baf2-4eda-8846-74611b46fac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421076518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2421076518
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.27696577
Short name T564
Test name
Test status
Simulation time 2289795722 ps
CPU time 3.52 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:27:59 PM PDT 24
Peak memory 201216 kb
Host smart-58506b25-a039-4c1e-ba02-f849ae2100cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27696577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_c
ond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_dete
ct_ec_rst_with_pre_cond.27696577
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.4279702145
Short name T737
Test name
Test status
Simulation time 26109542836 ps
CPU time 17.85 seconds
Started Mar 14 01:27:50 PM PDT 24
Finished Mar 14 01:28:08 PM PDT 24
Peak memory 201520 kb
Host smart-a31c01b0-d135-459f-9d23-36ac3c717f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279702145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.4279702145
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.760584657
Short name T301
Test name
Test status
Simulation time 3945241334 ps
CPU time 11.22 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:07 PM PDT 24
Peak memory 201204 kb
Host smart-db6f4383-32e1-4190-b822-585d9582fef7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760584657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_ec_pwr_on_rst.760584657
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1262376560
Short name T153
Test name
Test status
Simulation time 3149101664 ps
CPU time 6.34 seconds
Started Mar 14 01:27:50 PM PDT 24
Finished Mar 14 01:27:57 PM PDT 24
Peak memory 201204 kb
Host smart-db09891e-5ace-4285-8814-43aaf8fc338c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262376560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.1262376560
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.4122861127
Short name T642
Test name
Test status
Simulation time 2611993359 ps
CPU time 7.58 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:28:02 PM PDT 24
Peak memory 201196 kb
Host smart-cdf7ca0a-3376-4995-9ee6-d1e55308d068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122861127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.4122861127
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.702303121
Short name T287
Test name
Test status
Simulation time 2454084120 ps
CPU time 8.6 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:05 PM PDT 24
Peak memory 201180 kb
Host smart-58407ac7-f275-4d30-9459-cf72d078a405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702303121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.702303121
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.31195032
Short name T612
Test name
Test status
Simulation time 2048788740 ps
CPU time 2.11 seconds
Started Mar 14 01:27:48 PM PDT 24
Finished Mar 14 01:27:50 PM PDT 24
Peak memory 201112 kb
Host smart-59bee0f2-7697-464b-a391-3b4f8feef841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31195032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.31195032
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.2831659056
Short name T513
Test name
Test status
Simulation time 2537673439 ps
CPU time 2.34 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:27:57 PM PDT 24
Peak memory 201284 kb
Host smart-55b5415e-f1f4-4f40-bb28-9c22d850edec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831659056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.2831659056
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3353732715
Short name T269
Test name
Test status
Simulation time 22061197190 ps
CPU time 14.88 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:11 PM PDT 24
Peak memory 220856 kb
Host smart-0457f5d8-4032-4532-ae5e-6288d64343e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353732715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.3353732715
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.1293523161
Short name T472
Test name
Test status
Simulation time 2113438604 ps
CPU time 5.9 seconds
Started Mar 14 01:27:51 PM PDT 24
Finished Mar 14 01:27:58 PM PDT 24
Peak memory 200484 kb
Host smart-3f2e97d5-4eb2-4a4e-9f99-4b2be859b23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293523161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.1293523161
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.3906208199
Short name T121
Test name
Test status
Simulation time 7833444391 ps
CPU time 17.53 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:28:13 PM PDT 24
Peak memory 201104 kb
Host smart-b13e6abe-6edd-47c4-bafe-65ab640519b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906208199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.3906208199
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2458094324
Short name T88
Test name
Test status
Simulation time 5394912441 ps
CPU time 2.13 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:27:57 PM PDT 24
Peak memory 201220 kb
Host smart-2e9a6883-4daf-4498-addf-e9272d2f8d72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458094324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.2458094324
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.3269008972
Short name T716
Test name
Test status
Simulation time 2015783429 ps
CPU time 3.35 seconds
Started Mar 14 01:28:14 PM PDT 24
Finished Mar 14 01:28:18 PM PDT 24
Peak memory 201220 kb
Host smart-606eb235-db2f-443f-b938-9dbd291f4076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269008972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.3269008972
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3546465714
Short name T227
Test name
Test status
Simulation time 207266613159 ps
CPU time 27.22 seconds
Started Mar 14 01:28:20 PM PDT 24
Finished Mar 14 01:28:48 PM PDT 24
Peak memory 201240 kb
Host smart-9d307058-d8ad-47d4-b5d6-d38aa9e1547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546465714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.3
546465714
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.3578715685
Short name T537
Test name
Test status
Simulation time 157342899512 ps
CPU time 241.14 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:32:22 PM PDT 24
Peak memory 201344 kb
Host smart-dcddf54d-b949-4917-86f5-95f175e8bf38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578715685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.3578715685
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1807961220
Short name T197
Test name
Test status
Simulation time 85162114643 ps
CPU time 51.99 seconds
Started Mar 14 01:28:15 PM PDT 24
Finished Mar 14 01:29:07 PM PDT 24
Peak memory 201468 kb
Host smart-051db3c3-b342-491a-a688-d95107be6ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807961220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.1807961220
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1540351255
Short name T437
Test name
Test status
Simulation time 3710462330 ps
CPU time 10.8 seconds
Started Mar 14 01:28:20 PM PDT 24
Finished Mar 14 01:28:31 PM PDT 24
Peak memory 201168 kb
Host smart-ffe2fb82-30bf-4d4c-81ed-97f58648462b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540351255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.1540351255
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.567362003
Short name T205
Test name
Test status
Simulation time 2580510503 ps
CPU time 1.42 seconds
Started Mar 14 01:28:20 PM PDT 24
Finished Mar 14 01:28:22 PM PDT 24
Peak memory 201180 kb
Host smart-37423dbc-5bcb-418b-8e73-c5760f040b7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567362003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctr
l_edge_detect.567362003
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1960433951
Short name T645
Test name
Test status
Simulation time 2613317830 ps
CPU time 4.42 seconds
Started Mar 14 01:28:09 PM PDT 24
Finished Mar 14 01:28:14 PM PDT 24
Peak memory 201180 kb
Host smart-a72af904-42bb-4f80-8caf-b1db617e24dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960433951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.1960433951
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.423759801
Short name T490
Test name
Test status
Simulation time 2461335328 ps
CPU time 8.19 seconds
Started Mar 14 01:28:15 PM PDT 24
Finished Mar 14 01:28:23 PM PDT 24
Peak memory 201144 kb
Host smart-54a82cc5-4366-473f-88b6-3d89e579ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423759801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.423759801
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3895695234
Short name T321
Test name
Test status
Simulation time 2189309018 ps
CPU time 3.24 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:22 PM PDT 24
Peak memory 201196 kb
Host smart-6be1193d-410f-4cad-b4b4-6cded19c866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895695234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3895695234
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.1648663135
Short name T30
Test name
Test status
Simulation time 2531219930 ps
CPU time 2.36 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:23 PM PDT 24
Peak memory 201236 kb
Host smart-e40c2a78-875b-483e-95d2-1041f0f06543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648663135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.1648663135
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.3357971042
Short name T165
Test name
Test status
Simulation time 2115279521 ps
CPU time 2.98 seconds
Started Mar 14 01:28:14 PM PDT 24
Finished Mar 14 01:28:17 PM PDT 24
Peak memory 201080 kb
Host smart-89a7cf9f-eb2f-4551-9baa-488a16c7cd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357971042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.3357971042
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.197251681
Short name T323
Test name
Test status
Simulation time 8246212961 ps
CPU time 5.36 seconds
Started Mar 14 01:28:16 PM PDT 24
Finished Mar 14 01:28:22 PM PDT 24
Peak memory 201144 kb
Host smart-de84fc43-562d-4409-9946-2f7f01a74f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197251681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_st
ress_all.197251681
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2552110649
Short name T43
Test name
Test status
Simulation time 16609326308 ps
CPU time 43.02 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:49 PM PDT 24
Peak memory 211176 kb
Host smart-6c2f7112-864d-473a-ad68-d17a26d2a7b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552110649 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.2552110649
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.2177276236
Short name T695
Test name
Test status
Simulation time 3940961808 ps
CPU time 1.07 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:20 PM PDT 24
Peak memory 201184 kb
Host smart-6e63d4c2-accc-42f8-a3e6-049e42dfa34c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177276236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.2177276236
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.3732495618
Short name T738
Test name
Test status
Simulation time 2012748432 ps
CPU time 5.54 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:26 PM PDT 24
Peak memory 201168 kb
Host smart-e2455f33-ad81-4350-9429-4468314140aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732495618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.3732495618
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1502774655
Short name T531
Test name
Test status
Simulation time 3488034184 ps
CPU time 10.16 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:31 PM PDT 24
Peak memory 201236 kb
Host smart-af9b3197-9250-4107-be90-6406757193bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502774655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.1
502774655
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1284111512
Short name T100
Test name
Test status
Simulation time 31270903945 ps
CPU time 83.22 seconds
Started Mar 14 01:28:14 PM PDT 24
Finished Mar 14 01:29:37 PM PDT 24
Peak memory 201344 kb
Host smart-0915b307-6e11-4f7d-a224-09523e604254
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284111512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.1284111512
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3028596222
Short name T523
Test name
Test status
Simulation time 61274836292 ps
CPU time 86.21 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:29:47 PM PDT 24
Peak memory 201440 kb
Host smart-740bf0a1-3301-482b-9339-39b94d22398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028596222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.3028596222
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.905742467
Short name T473
Test name
Test status
Simulation time 4065713338 ps
CPU time 3.46 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:23 PM PDT 24
Peak memory 201176 kb
Host smart-23011afd-e736-42b3-a890-7f0435bb5ecd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905742467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ec_pwr_on_rst.905742467
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.2877210873
Short name T158
Test name
Test status
Simulation time 3311267687 ps
CPU time 2.1 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:21 PM PDT 24
Peak memory 201220 kb
Host smart-4ebcfee2-ef8a-4450-b6d5-fb77d2b099bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877210873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.2877210873
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3110619240
Short name T458
Test name
Test status
Simulation time 2638667746 ps
CPU time 2.63 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:22 PM PDT 24
Peak memory 201200 kb
Host smart-b6f0bdcb-3176-48cd-b88a-8631cbe50893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110619240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.3110619240
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1768713990
Short name T665
Test name
Test status
Simulation time 2464285835 ps
CPU time 2.65 seconds
Started Mar 14 01:28:18 PM PDT 24
Finished Mar 14 01:28:21 PM PDT 24
Peak memory 201240 kb
Host smart-6f1f6625-2b16-4486-a6d3-e54bec5432c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768713990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1768713990
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.103336270
Short name T747
Test name
Test status
Simulation time 2068242641 ps
CPU time 1.86 seconds
Started Mar 14 01:28:15 PM PDT 24
Finished Mar 14 01:28:17 PM PDT 24
Peak memory 201084 kb
Host smart-1ce5727b-65db-4311-a3ba-bcccc426a1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103336270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.103336270
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.4181297320
Short name T491
Test name
Test status
Simulation time 2511847596 ps
CPU time 7.35 seconds
Started Mar 14 01:28:17 PM PDT 24
Finished Mar 14 01:28:25 PM PDT 24
Peak memory 201276 kb
Host smart-6e0220fa-9d18-4bf8-8ee6-508a5a56bc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181297320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.4181297320
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.490624683
Short name T759
Test name
Test status
Simulation time 2129757787 ps
CPU time 2.04 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:21 PM PDT 24
Peak memory 201096 kb
Host smart-75d0ad2e-8746-4f9e-9079-f2d4c621fe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490624683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.490624683
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.3620658700
Short name T425
Test name
Test status
Simulation time 8603314801 ps
CPU time 4.58 seconds
Started Mar 14 01:28:20 PM PDT 24
Finished Mar 14 01:28:24 PM PDT 24
Peak memory 201176 kb
Host smart-5229d23c-e829-4753-a3c1-ff97904f963a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620658700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.3620658700
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1685145904
Short name T555
Test name
Test status
Simulation time 39273100247 ps
CPU time 63.24 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:29:23 PM PDT 24
Peak memory 218088 kb
Host smart-916ad6f9-49c1-422f-afa0-baba9bb2007e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685145904 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.1685145904
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.916223147
Short name T690
Test name
Test status
Simulation time 2758578507 ps
CPU time 1.59 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:23 PM PDT 24
Peak memory 201180 kb
Host smart-6f2c4c04-cd5e-4ae0-8ef6-45bb8b64dd1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916223147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ultra_low_pwr.916223147
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1446357856
Short name T687
Test name
Test status
Simulation time 2013324067 ps
CPU time 6.18 seconds
Started Mar 14 01:28:25 PM PDT 24
Finished Mar 14 01:28:31 PM PDT 24
Peak memory 201256 kb
Host smart-8f737262-0fea-4bdb-960a-57bb7d311a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446357856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1446357856
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1056823384
Short name T744
Test name
Test status
Simulation time 3542193430 ps
CPU time 2.07 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:23 PM PDT 24
Peak memory 201324 kb
Host smart-60225e06-0d09-4b14-bd59-1d022a8f76d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056823384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1
056823384
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.1500444016
Short name T637
Test name
Test status
Simulation time 34938634567 ps
CPU time 44.29 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:29:07 PM PDT 24
Peak memory 201348 kb
Host smart-bf029806-1184-478a-b8a3-bbbaef3eae7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500444016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.1500444016
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1634488614
Short name T376
Test name
Test status
Simulation time 51998584818 ps
CPU time 81.14 seconds
Started Mar 14 01:28:24 PM PDT 24
Finished Mar 14 01:29:46 PM PDT 24
Peak memory 201496 kb
Host smart-d9a6c20c-b7aa-4a1a-b848-7de254be770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634488614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.1634488614
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3245069160
Short name T484
Test name
Test status
Simulation time 3887356374 ps
CPU time 10.68 seconds
Started Mar 14 01:28:24 PM PDT 24
Finished Mar 14 01:28:35 PM PDT 24
Peak memory 201208 kb
Host smart-dbc7d85e-88a0-42e3-b2a2-e0eb97ec287a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245069160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.3245069160
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.2019060700
Short name T573
Test name
Test status
Simulation time 2582748140 ps
CPU time 3.9 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:25 PM PDT 24
Peak memory 201192 kb
Host smart-bc34d664-a0e0-4222-b700-a4c091acaffd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019060700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.2019060700
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.4237937755
Short name T399
Test name
Test status
Simulation time 2610929766 ps
CPU time 7.17 seconds
Started Mar 14 01:28:24 PM PDT 24
Finished Mar 14 01:28:31 PM PDT 24
Peak memory 201176 kb
Host smart-0fa2f890-9d39-460c-a4ff-37a500f553f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237937755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.4237937755
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.1837390839
Short name T28
Test name
Test status
Simulation time 2461492926 ps
CPU time 4 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:25 PM PDT 24
Peak memory 201176 kb
Host smart-70d7d415-ffc6-4bd4-ba61-b4ae573d28b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837390839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.1837390839
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.2828087540
Short name T509
Test name
Test status
Simulation time 2261074754 ps
CPU time 1.85 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:28:25 PM PDT 24
Peak memory 201176 kb
Host smart-b899a904-6dcb-4b5b-ad3b-cfa416aac329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828087540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.2828087540
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3609109547
Short name T316
Test name
Test status
Simulation time 2523459975 ps
CPU time 3.17 seconds
Started Mar 14 01:28:29 PM PDT 24
Finished Mar 14 01:28:32 PM PDT 24
Peak memory 201304 kb
Host smart-606a5835-6c46-409e-90fd-a7eb97832f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609109547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3609109547
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.613403940
Short name T776
Test name
Test status
Simulation time 2161087619 ps
CPU time 1.44 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:28:24 PM PDT 24
Peak memory 201148 kb
Host smart-42323edc-49a8-467a-af7d-ea3edc902d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613403940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.613403940
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.2223596009
Short name T733
Test name
Test status
Simulation time 120562949151 ps
CPU time 89.73 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:29:51 PM PDT 24
Peak memory 201364 kb
Host smart-6c9a9e27-3a44-4304-b3dc-b945e7dd7333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223596009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.2223596009
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3940363197
Short name T117
Test name
Test status
Simulation time 69625389117 ps
CPU time 82.7 seconds
Started Mar 14 01:28:24 PM PDT 24
Finished Mar 14 01:29:47 PM PDT 24
Peak memory 218008 kb
Host smart-a0d963c0-8a25-4642-9ab8-1bfe5905dc56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940363197 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3940363197
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2174979356
Short name T57
Test name
Test status
Simulation time 3731600129 ps
CPU time 1.74 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:28:24 PM PDT 24
Peak memory 201180 kb
Host smart-b163e91c-0b2d-42f8-9935-826eb1fe6913
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174979356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.2174979356
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.1867923863
Short name T259
Test name
Test status
Simulation time 2012077697 ps
CPU time 5.15 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:28:27 PM PDT 24
Peak memory 201308 kb
Host smart-a7e49171-0fb3-44c2-bec5-5cb4ef5013dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867923863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.1867923863
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.201825721
Short name T658
Test name
Test status
Simulation time 111831800016 ps
CPU time 299 seconds
Started Mar 14 01:28:24 PM PDT 24
Finished Mar 14 01:33:24 PM PDT 24
Peak memory 201448 kb
Host smart-20072131-8af3-4d37-b447-10609f1e59ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201825721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_combo_detect.201825721
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.803024463
Short name T560
Test name
Test status
Simulation time 36160643565 ps
CPU time 53.52 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:29:15 PM PDT 24
Peak memory 201496 kb
Host smart-aa9b59a3-adca-4589-904e-690e02b8b7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803024463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_wi
th_pre_cond.803024463
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.2870978528
Short name T787
Test name
Test status
Simulation time 2808465799 ps
CPU time 4.45 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:25 PM PDT 24
Peak memory 201196 kb
Host smart-9df1b7f4-b08c-4007-b691-6d73ec18a596
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870978528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.2870978528
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.4124667026
Short name T577
Test name
Test status
Simulation time 2946177993 ps
CPU time 1.92 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:21 PM PDT 24
Peak memory 201204 kb
Host smart-520e8a27-24fb-4c11-b492-d3afc6953119
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124667026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.4124667026
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1635497593
Short name T736
Test name
Test status
Simulation time 2623620154 ps
CPU time 4.35 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:28:27 PM PDT 24
Peak memory 201168 kb
Host smart-86555a87-d624-428a-b0f4-0534a955fd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635497593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.1635497593
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.1476496572
Short name T293
Test name
Test status
Simulation time 2462835283 ps
CPU time 2.35 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:28:26 PM PDT 24
Peak memory 201188 kb
Host smart-7883767f-023f-4a0b-b286-e90142c2a911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476496572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.1476496572
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.582133089
Short name T547
Test name
Test status
Simulation time 2029665173 ps
CPU time 2.07 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:23 PM PDT 24
Peak memory 201112 kb
Host smart-7d7f37a5-c0d0-40a7-88b0-d8e95de5f084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582133089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.582133089
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.4154254136
Short name T681
Test name
Test status
Simulation time 2540284449 ps
CPU time 2.26 seconds
Started Mar 14 01:28:29 PM PDT 24
Finished Mar 14 01:28:31 PM PDT 24
Peak memory 201304 kb
Host smart-7e8a3470-2c62-4ec4-9fd1-0f8f43b79ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154254136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.4154254136
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.494420940
Short name T412
Test name
Test status
Simulation time 2111267411 ps
CPU time 5.84 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:28:28 PM PDT 24
Peak memory 201068 kb
Host smart-fa8aa08c-92ae-4345-806f-a8739be8529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494420940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.494420940
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.3529713378
Short name T83
Test name
Test status
Simulation time 139766273072 ps
CPU time 379.67 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:34:43 PM PDT 24
Peak memory 201492 kb
Host smart-d8bce4d9-3ba6-4d6e-bb50-06abc596f792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529713378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.3529713378
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.439697178
Short name T152
Test name
Test status
Simulation time 2856378776 ps
CPU time 2 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:28:24 PM PDT 24
Peak memory 201168 kb
Host smart-66918207-737d-4c3c-befb-5c916870f339
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439697178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_ultra_low_pwr.439697178
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.3882082927
Short name T782
Test name
Test status
Simulation time 2088285124 ps
CPU time 1.16 seconds
Started Mar 14 01:28:24 PM PDT 24
Finished Mar 14 01:28:25 PM PDT 24
Peak memory 201292 kb
Host smart-691a0b46-d7ea-4ee9-a6f3-0ffb73384533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882082927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.3882082927
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.4216721609
Short name T450
Test name
Test status
Simulation time 3073779180 ps
CPU time 8.69 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:28:32 PM PDT 24
Peak memory 201288 kb
Host smart-2d16abe9-5c62-4ded-b318-3b70e0ed10fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216721609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.4
216721609
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1781732030
Short name T11
Test name
Test status
Simulation time 157406035055 ps
CPU time 95.64 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:29:57 PM PDT 24
Peak memory 201380 kb
Host smart-878a2c29-d135-4dde-a631-af20e977c590
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781732030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.1781732030
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3386284391
Short name T241
Test name
Test status
Simulation time 29110357658 ps
CPU time 19.82 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:28:43 PM PDT 24
Peak memory 201468 kb
Host smart-1c3318d8-b24e-4354-8fc6-e47736c83a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386284391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.3386284391
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3647716495
Short name T565
Test name
Test status
Simulation time 2524731203 ps
CPU time 5.03 seconds
Started Mar 14 01:28:24 PM PDT 24
Finished Mar 14 01:28:29 PM PDT 24
Peak memory 201176 kb
Host smart-d81342c5-1015-4402-9dfc-eca6e68b7d31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647716495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.3647716495
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.674874453
Short name T146
Test name
Test status
Simulation time 1005317558290 ps
CPU time 328.07 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:33:50 PM PDT 24
Peak memory 201184 kb
Host smart-474283f4-de86-47b7-b299-d415218659e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674874453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_edge_detect.674874453
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.7847415
Short name T582
Test name
Test status
Simulation time 2628361413 ps
CPU time 2.35 seconds
Started Mar 14 01:28:27 PM PDT 24
Finished Mar 14 01:28:29 PM PDT 24
Peak memory 201236 kb
Host smart-b1472494-4813-45f0-b8ac-9a525d951a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7847415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.7847415
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.3249505419
Short name T673
Test name
Test status
Simulation time 2473104906 ps
CPU time 6.94 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:28:30 PM PDT 24
Peak memory 201184 kb
Host smart-4e2257cf-ca25-4957-90d6-5a76bf375d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249505419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.3249505419
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3125485887
Short name T190
Test name
Test status
Simulation time 2137902894 ps
CPU time 5.92 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:27 PM PDT 24
Peak memory 200992 kb
Host smart-55ec4156-1534-421c-895c-84385d74d72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125485887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3125485887
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1928201195
Short name T724
Test name
Test status
Simulation time 2536258508 ps
CPU time 1.75 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:28:24 PM PDT 24
Peak memory 201284 kb
Host smart-43d91646-9b11-4217-a850-0eba0d31318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928201195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1928201195
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3710353596
Short name T424
Test name
Test status
Simulation time 2124785824 ps
CPU time 1.97 seconds
Started Mar 14 01:28:21 PM PDT 24
Finished Mar 14 01:28:23 PM PDT 24
Peak memory 201052 kb
Host smart-7924a74b-f70e-4fe7-9be6-59e8da657fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710353596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3710353596
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.3847952248
Short name T667
Test name
Test status
Simulation time 16941502926 ps
CPU time 22.75 seconds
Started Mar 14 01:28:27 PM PDT 24
Finished Mar 14 01:28:51 PM PDT 24
Peak memory 201256 kb
Host smart-03322a67-48f7-4a09-9e24-70417eea1998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847952248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.3847952248
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.2531686011
Short name T141
Test name
Test status
Simulation time 52401731181 ps
CPU time 37.41 seconds
Started Mar 14 01:28:27 PM PDT 24
Finished Mar 14 01:29:05 PM PDT 24
Peak memory 209940 kb
Host smart-f21454b1-90c7-43f4-b9d1-5f969d256b0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531686011 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.2531686011
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3933180381
Short name T670
Test name
Test status
Simulation time 7230624584 ps
CPU time 8.57 seconds
Started Mar 14 01:28:22 PM PDT 24
Finished Mar 14 01:28:31 PM PDT 24
Peak memory 201212 kb
Host smart-74286869-0d63-4b7c-aa6f-11fce3e961ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933180381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.3933180381
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.1552620003
Short name T546
Test name
Test status
Simulation time 2015942621 ps
CPU time 4.48 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:28:44 PM PDT 24
Peak memory 201276 kb
Host smart-faf880b4-8cd1-4572-a8b1-eb9e4ef1ef0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552620003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.1552620003
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2915598777
Short name T296
Test name
Test status
Simulation time 3330535985 ps
CPU time 1.16 seconds
Started Mar 14 01:28:35 PM PDT 24
Finished Mar 14 01:28:37 PM PDT 24
Peak memory 201220 kb
Host smart-2c874756-db00-4680-b0b5-665f9005cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915598777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
915598777
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.1507883945
Short name T92
Test name
Test status
Simulation time 45319017764 ps
CPU time 31.16 seconds
Started Mar 14 01:28:37 PM PDT 24
Finished Mar 14 01:29:09 PM PDT 24
Peak memory 201428 kb
Host smart-852b5701-1db4-47bd-8b4d-2bb0b9c6d75a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507883945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.1507883945
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.133725418
Short name T500
Test name
Test status
Simulation time 70200870097 ps
CPU time 96.83 seconds
Started Mar 14 01:28:41 PM PDT 24
Finished Mar 14 01:30:19 PM PDT 24
Peak memory 201496 kb
Host smart-bf6bae37-437b-474d-84b7-5133a1062fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133725418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_wi
th_pre_cond.133725418
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.988003706
Short name T528
Test name
Test status
Simulation time 2532180606 ps
CPU time 7.36 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:28:46 PM PDT 24
Peak memory 201240 kb
Host smart-141701c3-cb67-42b0-8fba-d4834d79990c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988003706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_ec_pwr_on_rst.988003706
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.940742554
Short name T452
Test name
Test status
Simulation time 2619676658 ps
CPU time 3.99 seconds
Started Mar 14 01:28:35 PM PDT 24
Finished Mar 14 01:28:39 PM PDT 24
Peak memory 201140 kb
Host smart-56f0af45-9284-407f-906c-4bf460a908fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940742554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.940742554
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.646465048
Short name T331
Test name
Test status
Simulation time 2450349024 ps
CPU time 7.63 seconds
Started Mar 14 01:28:25 PM PDT 24
Finished Mar 14 01:28:33 PM PDT 24
Peak memory 201172 kb
Host smart-70a579bb-d03d-4ca6-91be-96a192c38ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646465048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.646465048
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.3478766832
Short name T107
Test name
Test status
Simulation time 2034882203 ps
CPU time 5.86 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:28:45 PM PDT 24
Peak memory 201036 kb
Host smart-8f2b432a-6e63-4a79-a3cd-066e92c7063d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478766832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3478766832
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2316749382
Short name T771
Test name
Test status
Simulation time 2514792404 ps
CPU time 4.04 seconds
Started Mar 14 01:28:39 PM PDT 24
Finished Mar 14 01:28:44 PM PDT 24
Peak memory 201260 kb
Host smart-be7a1394-5572-4081-b1a5-6aefe628f72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316749382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2316749382
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.974307504
Short name T419
Test name
Test status
Simulation time 2111860800 ps
CPU time 5.83 seconds
Started Mar 14 01:28:23 PM PDT 24
Finished Mar 14 01:28:29 PM PDT 24
Peak memory 201116 kb
Host smart-a1ad61fc-01f4-40eb-9342-cc9a62515f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974307504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.974307504
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.2809259973
Short name T52
Test name
Test status
Simulation time 89874840845 ps
CPU time 64.25 seconds
Started Mar 14 01:28:41 PM PDT 24
Finished Mar 14 01:29:46 PM PDT 24
Peak memory 201400 kb
Host smart-ea86763b-55e9-4ba7-bba0-2c7afacfee28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809259973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.2809259973
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2696212558
Short name T304
Test name
Test status
Simulation time 29821822784 ps
CPU time 74.16 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:29:53 PM PDT 24
Peak memory 211360 kb
Host smart-7c31f1a8-9571-47b9-a3fc-559bb3dc8183
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696212558 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2696212558
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2416654726
Short name T59
Test name
Test status
Simulation time 13407542751 ps
CPU time 3.44 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:28:43 PM PDT 24
Peak memory 201200 kb
Host smart-51d7792f-5068-44c3-970c-cac338ed1e62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416654726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.2416654726
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.356738508
Short name T659
Test name
Test status
Simulation time 2010615839 ps
CPU time 6.35 seconds
Started Mar 14 01:28:37 PM PDT 24
Finished Mar 14 01:28:43 PM PDT 24
Peak memory 201296 kb
Host smart-80325488-7d64-4e30-b412-801bec33e5ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356738508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.356738508
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3949865967
Short name T405
Test name
Test status
Simulation time 22943646773 ps
CPU time 17.16 seconds
Started Mar 14 01:28:36 PM PDT 24
Finished Mar 14 01:28:54 PM PDT 24
Peak memory 201208 kb
Host smart-fc3acb5e-63c1-415f-9203-5e13d8348585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949865967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.3
949865967
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.2324579293
Short name T615
Test name
Test status
Simulation time 139154231106 ps
CPU time 90.66 seconds
Started Mar 14 01:28:35 PM PDT 24
Finished Mar 14 01:30:06 PM PDT 24
Peak memory 201372 kb
Host smart-fbc626be-6cca-4cf7-9808-fce4ab4e2968
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324579293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.2324579293
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1918985428
Short name T761
Test name
Test status
Simulation time 112171283204 ps
CPU time 310.85 seconds
Started Mar 14 01:28:33 PM PDT 24
Finished Mar 14 01:33:45 PM PDT 24
Peak memory 201536 kb
Host smart-d6023425-3c9e-483d-8d30-2c97bf0e3924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918985428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.1918985428
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.650389088
Short name T669
Test name
Test status
Simulation time 635052503593 ps
CPU time 436.97 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:35:56 PM PDT 24
Peak memory 201188 kb
Host smart-6e3cb7c2-4ad0-4133-b20f-be1ced00386b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650389088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_ec_pwr_on_rst.650389088
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.1935689070
Short name T160
Test name
Test status
Simulation time 3200758461 ps
CPU time 2.31 seconds
Started Mar 14 01:28:39 PM PDT 24
Finished Mar 14 01:28:42 PM PDT 24
Peak memory 201212 kb
Host smart-fec4d375-eba1-4258-ac4b-ec6be4054849
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935689070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.1935689070
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2089415999
Short name T408
Test name
Test status
Simulation time 2622720130 ps
CPU time 2.36 seconds
Started Mar 14 01:28:39 PM PDT 24
Finished Mar 14 01:28:42 PM PDT 24
Peak memory 201156 kb
Host smart-2553f3fd-5184-4465-913b-bf5337cf886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089415999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.2089415999
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2956434231
Short name T201
Test name
Test status
Simulation time 2458466047 ps
CPU time 7.04 seconds
Started Mar 14 01:28:36 PM PDT 24
Finished Mar 14 01:28:43 PM PDT 24
Peak memory 201212 kb
Host smart-c6bf862f-aff4-4f37-a327-734518699281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956434231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2956434231
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.873763867
Short name T728
Test name
Test status
Simulation time 2096689198 ps
CPU time 2.57 seconds
Started Mar 14 01:28:37 PM PDT 24
Finished Mar 14 01:28:40 PM PDT 24
Peak memory 201136 kb
Host smart-09e0d1ca-52f5-4401-9216-676d4fdef413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873763867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.873763867
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2787949649
Short name T210
Test name
Test status
Simulation time 2512878495 ps
CPU time 7.29 seconds
Started Mar 14 01:28:41 PM PDT 24
Finished Mar 14 01:28:49 PM PDT 24
Peak memory 201236 kb
Host smart-adba0f6b-6dbf-464b-a12d-f0930b57c848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787949649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2787949649
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.3140379276
Short name T495
Test name
Test status
Simulation time 2130558140 ps
CPU time 2.06 seconds
Started Mar 14 01:28:36 PM PDT 24
Finished Mar 14 01:28:39 PM PDT 24
Peak memory 201084 kb
Host smart-20f32106-721a-427f-aa84-e072036aeade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140379276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.3140379276
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.1262632030
Short name T91
Test name
Test status
Simulation time 23870003558 ps
CPU time 10.83 seconds
Started Mar 14 01:28:35 PM PDT 24
Finished Mar 14 01:28:46 PM PDT 24
Peak memory 201252 kb
Host smart-ffb35e06-e8af-4c84-8f81-713118108b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262632030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.1262632030
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.2134906275
Short name T411
Test name
Test status
Simulation time 2044801504 ps
CPU time 1.96 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:28:41 PM PDT 24
Peak memory 201268 kb
Host smart-84df662b-a34c-444d-88b5-ac02d9469db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134906275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.2134906275
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1098636637
Short name T650
Test name
Test status
Simulation time 3546245644 ps
CPU time 3.95 seconds
Started Mar 14 01:28:33 PM PDT 24
Finished Mar 14 01:28:37 PM PDT 24
Peak memory 201232 kb
Host smart-bd78d919-7284-4522-8048-ef27753d966f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098636637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
098636637
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.487802089
Short name T788
Test name
Test status
Simulation time 66765694854 ps
CPU time 45.91 seconds
Started Mar 14 01:28:34 PM PDT 24
Finished Mar 14 01:29:21 PM PDT 24
Peak memory 201452 kb
Host smart-896efce3-e020-46e2-8efe-1ffe829b6bc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487802089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.487802089
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.4162666223
Short name T684
Test name
Test status
Simulation time 135804151753 ps
CPU time 121.51 seconds
Started Mar 14 01:28:37 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 201456 kb
Host smart-ad70f7d7-66f7-42e5-aac0-26bf862f8173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162666223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.4162666223
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2772484270
Short name T601
Test name
Test status
Simulation time 4314331491 ps
CPU time 11.3 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:28:51 PM PDT 24
Peak memory 201160 kb
Host smart-9ceb0fb6-138f-4d54-8f32-705b35d4bb2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772484270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.2772484270
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.2310826508
Short name T188
Test name
Test status
Simulation time 4387268271 ps
CPU time 2.88 seconds
Started Mar 14 01:28:34 PM PDT 24
Finished Mar 14 01:28:38 PM PDT 24
Peak memory 201184 kb
Host smart-0c3503be-6805-4186-8164-6992b1dcad69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310826508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.2310826508
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1770971797
Short name T700
Test name
Test status
Simulation time 2643488497 ps
CPU time 2.03 seconds
Started Mar 14 01:28:33 PM PDT 24
Finished Mar 14 01:28:35 PM PDT 24
Peak memory 201220 kb
Host smart-1d4ae6c4-89af-4f06-a419-d63bdc3f774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770971797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.1770971797
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.2654828157
Short name T61
Test name
Test status
Simulation time 2460341761 ps
CPU time 6.36 seconds
Started Mar 14 01:28:41 PM PDT 24
Finished Mar 14 01:28:48 PM PDT 24
Peak memory 201212 kb
Host smart-c1032264-1b2a-4269-8eb6-99fe8a1926ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654828157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.2654828157
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.4122647481
Short name T741
Test name
Test status
Simulation time 2227456776 ps
CPU time 2.45 seconds
Started Mar 14 01:28:34 PM PDT 24
Finished Mar 14 01:28:37 PM PDT 24
Peak memory 201244 kb
Host smart-ae7cf7e3-78ab-4b85-b584-aaf6d418f4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122647481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.4122647481
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1913619928
Short name T229
Test name
Test status
Simulation time 2541603839 ps
CPU time 2.26 seconds
Started Mar 14 01:28:34 PM PDT 24
Finished Mar 14 01:28:37 PM PDT 24
Peak memory 201296 kb
Host smart-38fc569e-bdfd-442b-9b88-4eb2760bdb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913619928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.1913619928
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.3893308123
Short name T629
Test name
Test status
Simulation time 2167449065 ps
CPU time 1.42 seconds
Started Mar 14 01:28:35 PM PDT 24
Finished Mar 14 01:28:37 PM PDT 24
Peak memory 201188 kb
Host smart-90a6257c-1398-476c-82dc-ed6bcb3bc8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893308123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.3893308123
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.4282292400
Short name T431
Test name
Test status
Simulation time 13057207129 ps
CPU time 36.68 seconds
Started Mar 14 01:28:36 PM PDT 24
Finished Mar 14 01:29:13 PM PDT 24
Peak memory 201200 kb
Host smart-905a09d0-1917-47a7-813e-72c27ef25c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282292400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.4282292400
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3301831944
Short name T203
Test name
Test status
Simulation time 28555591522 ps
CPU time 74.7 seconds
Started Mar 14 01:28:36 PM PDT 24
Finished Mar 14 01:29:51 PM PDT 24
Peak memory 217772 kb
Host smart-5e0e8e14-2ccd-4d74-8a5f-7597d07489cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301831944 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.3301831944
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1491008524
Short name T706
Test name
Test status
Simulation time 3235625798 ps
CPU time 2.03 seconds
Started Mar 14 01:28:34 PM PDT 24
Finished Mar 14 01:28:37 PM PDT 24
Peak memory 201196 kb
Host smart-60094b1a-108c-422e-bd3c-f2afef80f76f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491008524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.1491008524
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3768086938
Short name T289
Test name
Test status
Simulation time 2026140333 ps
CPU time 1.88 seconds
Started Mar 14 01:28:41 PM PDT 24
Finished Mar 14 01:28:44 PM PDT 24
Peak memory 201232 kb
Host smart-89ce743a-0da2-4789-a152-597b888ad489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768086938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3768086938
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1992069192
Short name T483
Test name
Test status
Simulation time 3020342160 ps
CPU time 4.42 seconds
Started Mar 14 01:28:39 PM PDT 24
Finished Mar 14 01:28:44 PM PDT 24
Peak memory 201292 kb
Host smart-2aabbf24-d3b0-4935-86a6-9249b004ac64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992069192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1
992069192
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.2862282513
Short name T613
Test name
Test status
Simulation time 39616889541 ps
CPU time 106.46 seconds
Started Mar 14 01:28:37 PM PDT 24
Finished Mar 14 01:30:25 PM PDT 24
Peak memory 201476 kb
Host smart-36f1af03-6657-431a-8ee3-9003c5a21866
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862282513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.2862282513
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.4055410660
Short name T242
Test name
Test status
Simulation time 37106418114 ps
CPU time 57.33 seconds
Started Mar 14 01:28:33 PM PDT 24
Finished Mar 14 01:29:31 PM PDT 24
Peak memory 201420 kb
Host smart-66b35b65-c0b7-4263-8acb-ec9252310ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055410660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.4055410660
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2274182584
Short name T403
Test name
Test status
Simulation time 2690580855 ps
CPU time 2.67 seconds
Started Mar 14 01:28:34 PM PDT 24
Finished Mar 14 01:28:37 PM PDT 24
Peak memory 201200 kb
Host smart-eeb30f12-f1ce-40a0-9b95-65203b629f56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274182584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.2274182584
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.3740969944
Short name T133
Test name
Test status
Simulation time 3267281594 ps
CPU time 1.93 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:28:42 PM PDT 24
Peak memory 201192 kb
Host smart-6ff3d2f2-1273-41d6-9cf1-78eea5eb6db5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740969944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.3740969944
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1602421849
Short name T666
Test name
Test status
Simulation time 2630473609 ps
CPU time 1.81 seconds
Started Mar 14 01:28:35 PM PDT 24
Finished Mar 14 01:28:37 PM PDT 24
Peak memory 201172 kb
Host smart-07933b47-4bf1-4d64-b367-a850be013339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602421849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1602421849
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3256264120
Short name T332
Test name
Test status
Simulation time 2479753270 ps
CPU time 2.41 seconds
Started Mar 14 01:28:39 PM PDT 24
Finished Mar 14 01:28:42 PM PDT 24
Peak memory 201172 kb
Host smart-ac3ab647-5f59-49c2-b9b2-5472d2864696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256264120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.3256264120
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3518223969
Short name T550
Test name
Test status
Simulation time 2196638460 ps
CPU time 6.56 seconds
Started Mar 14 01:28:40 PM PDT 24
Finished Mar 14 01:28:47 PM PDT 24
Peak memory 201204 kb
Host smart-4ddc8540-e0fa-4c87-8b76-5a4c67eea671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518223969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3518223969
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2572908030
Short name T396
Test name
Test status
Simulation time 2511110094 ps
CPU time 7.34 seconds
Started Mar 14 01:28:34 PM PDT 24
Finished Mar 14 01:28:42 PM PDT 24
Peak memory 201240 kb
Host smart-23424773-e13c-4e57-a09d-6a32fb820803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572908030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.2572908030
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.142666887
Short name T632
Test name
Test status
Simulation time 2148107783 ps
CPU time 1.42 seconds
Started Mar 14 01:28:39 PM PDT 24
Finished Mar 14 01:28:41 PM PDT 24
Peak memory 201192 kb
Host smart-901766c9-3d68-4e60-8938-d1b5cde0c88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142666887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.142666887
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.2538222455
Short name T441
Test name
Test status
Simulation time 11080459321 ps
CPU time 24.15 seconds
Started Mar 14 01:28:34 PM PDT 24
Finished Mar 14 01:28:58 PM PDT 24
Peak memory 201280 kb
Host smart-b5fefa55-daa8-48b7-bae8-ca7f3b056ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538222455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.2538222455
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.184902388
Short name T134
Test name
Test status
Simulation time 66536519366 ps
CPU time 41.92 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:29:20 PM PDT 24
Peak memory 217556 kb
Host smart-35c2cf13-5639-43be-9270-5472263d5047
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184902388 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.184902388
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3364746333
Short name T338
Test name
Test status
Simulation time 7126138165 ps
CPU time 4.52 seconds
Started Mar 14 01:28:38 PM PDT 24
Finished Mar 14 01:28:44 PM PDT 24
Peak memory 201200 kb
Host smart-3fcc0f0b-b096-4961-bf99-7bed5cf42ac1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364746333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.3364746333
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.1031948910
Short name T579
Test name
Test status
Simulation time 2059883463 ps
CPU time 1.31 seconds
Started Mar 14 01:28:48 PM PDT 24
Finished Mar 14 01:28:50 PM PDT 24
Peak memory 201272 kb
Host smart-af27ccd2-d889-4ebe-a44d-fa7697aa0c34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031948910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.1031948910
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1533994193
Short name T310
Test name
Test status
Simulation time 3235509805 ps
CPU time 4.85 seconds
Started Mar 14 01:28:33 PM PDT 24
Finished Mar 14 01:28:39 PM PDT 24
Peak memory 201260 kb
Host smart-c43836ff-fa85-4eba-8745-3afb86665c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533994193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1
533994193
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.1173813807
Short name T238
Test name
Test status
Simulation time 120403768778 ps
CPU time 81.15 seconds
Started Mar 14 01:28:35 PM PDT 24
Finished Mar 14 01:29:57 PM PDT 24
Peak memory 201364 kb
Host smart-cec74412-db0c-4379-b75c-b9d4e0290667
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173813807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.1173813807
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.385263000
Short name T674
Test name
Test status
Simulation time 2694481178 ps
CPU time 7.36 seconds
Started Mar 14 01:28:34 PM PDT 24
Finished Mar 14 01:28:42 PM PDT 24
Peak memory 201116 kb
Host smart-6191ef79-08bf-4a4f-abc0-c98dd94f0c40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385263000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.385263000
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.3064261961
Short name T144
Test name
Test status
Simulation time 3207596734 ps
CPU time 2.24 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:28:49 PM PDT 24
Peak memory 201200 kb
Host smart-4478b0b1-7321-4f84-9426-aff42d9a1294
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064261961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.3064261961
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1178748135
Short name T202
Test name
Test status
Simulation time 2786559505 ps
CPU time 1.03 seconds
Started Mar 14 01:28:37 PM PDT 24
Finished Mar 14 01:28:39 PM PDT 24
Peak memory 201152 kb
Host smart-f2ae6bb2-8046-4607-aadb-cdb1aad6605f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178748135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.1178748135
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.7232667
Short name T63
Test name
Test status
Simulation time 2488132106 ps
CPU time 7.38 seconds
Started Mar 14 01:28:35 PM PDT 24
Finished Mar 14 01:28:43 PM PDT 24
Peak memory 201184 kb
Host smart-5de6f9fc-d17d-408c-90e8-a1634d844ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7232667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.7232667
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1731284284
Short name T421
Test name
Test status
Simulation time 2079447928 ps
CPU time 6.15 seconds
Started Mar 14 01:28:37 PM PDT 24
Finished Mar 14 01:28:44 PM PDT 24
Peak memory 201132 kb
Host smart-fd98fd17-aa91-4498-af1b-48a8ce14df92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731284284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.1731284284
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1323988258
Short name T170
Test name
Test status
Simulation time 2574411309 ps
CPU time 1.36 seconds
Started Mar 14 01:28:37 PM PDT 24
Finished Mar 14 01:28:39 PM PDT 24
Peak memory 201252 kb
Host smart-1511f0ec-3a39-47bc-9420-f98b86b8f669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323988258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.1323988258
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.2765679868
Short name T442
Test name
Test status
Simulation time 2111243098 ps
CPU time 5.88 seconds
Started Mar 14 01:28:36 PM PDT 24
Finished Mar 14 01:28:42 PM PDT 24
Peak memory 200900 kb
Host smart-c9125335-6291-4a86-afd3-1848051f8d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765679868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.2765679868
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.2954656596
Short name T689
Test name
Test status
Simulation time 72197344276 ps
CPU time 178.51 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:31:45 PM PDT 24
Peak memory 201432 kb
Host smart-0cd9f02c-f433-460e-b3e6-a3dd3ccc3ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954656596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.2954656596
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3461132921
Short name T339
Test name
Test status
Simulation time 107664999066 ps
CPU time 17.75 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:29:03 PM PDT 24
Peak memory 218076 kb
Host smart-e64eed01-8468-4010-ab3e-8f7a778e236d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461132921 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.3461132921
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1809864281
Short name T570
Test name
Test status
Simulation time 8744807591 ps
CPU time 2.38 seconds
Started Mar 14 01:28:41 PM PDT 24
Finished Mar 14 01:28:44 PM PDT 24
Peak memory 201184 kb
Host smart-4941a9c8-9494-4fca-abc4-c1cd73408f04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809864281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.1809864281
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.4280829387
Short name T207
Test name
Test status
Simulation time 2015700592 ps
CPU time 5.64 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:27:58 PM PDT 24
Peak memory 201256 kb
Host smart-7221fc9a-17dd-4746-99bb-b4c05b1798a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280829387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.4280829387
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1037755085
Short name T594
Test name
Test status
Simulation time 164870184463 ps
CPU time 453.31 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:35:26 PM PDT 24
Peak memory 201288 kb
Host smart-6e5435d7-2f84-4c47-a563-c2212d710e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037755085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1037755085
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.2335165959
Short name T199
Test name
Test status
Simulation time 211031964118 ps
CPU time 131.23 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:30:05 PM PDT 24
Peak memory 201364 kb
Host smart-95093e39-3eab-49c6-b05d-5c46c4eedbd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335165959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.2335165959
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1366219179
Short name T449
Test name
Test status
Simulation time 2291291844 ps
CPU time 1.1 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 201196 kb
Host smart-1080c97e-1554-4ac9-9b3e-5c0f36661c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366219179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.1366219179
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2368763873
Short name T693
Test name
Test status
Simulation time 2349777029 ps
CPU time 1.39 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 201156 kb
Host smart-6c52a32a-779a-47a7-9a86-2c11d664325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368763873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2368763873
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3299142287
Short name T311
Test name
Test status
Simulation time 2931389312 ps
CPU time 2.61 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:27:56 PM PDT 24
Peak memory 201216 kb
Host smart-70609f92-c835-4dc3-af41-f4d58ac1144b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299142287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.3299142287
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1679481278
Short name T206
Test name
Test status
Simulation time 3095517194 ps
CPU time 4.06 seconds
Started Mar 14 01:27:49 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 201164 kb
Host smart-12c98243-dd6b-4c5a-a0f8-8f35c205102c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679481278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.1679481278
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.770203527
Short name T479
Test name
Test status
Simulation time 2610652282 ps
CPU time 7.71 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:28:00 PM PDT 24
Peak memory 201120 kb
Host smart-4db10287-16af-4b7c-aebc-bd78dcc567f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770203527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.770203527
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1958695128
Short name T481
Test name
Test status
Simulation time 2457623568 ps
CPU time 7.22 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:03 PM PDT 24
Peak memory 201200 kb
Host smart-2dc415e1-eb88-47ea-9326-45424dbd8dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958695128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.1958695128
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2661754407
Short name T221
Test name
Test status
Simulation time 2126309401 ps
CPU time 2.11 seconds
Started Mar 14 01:27:51 PM PDT 24
Finished Mar 14 01:27:54 PM PDT 24
Peak memory 201124 kb
Host smart-7658fde6-7036-4f58-a2cb-c173e5fe02d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661754407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2661754407
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1795446066
Short name T767
Test name
Test status
Simulation time 2514666033 ps
CPU time 7.4 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:28:03 PM PDT 24
Peak memory 201256 kb
Host smart-794979ba-52eb-4611-908b-63391115ed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795446066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1795446066
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.790533111
Short name T285
Test name
Test status
Simulation time 42073492209 ps
CPU time 37.57 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:28:32 PM PDT 24
Peak memory 221456 kb
Host smart-b2e75e78-24e2-4f84-94a4-eb5cf0a1dc89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790533111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.790533111
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.1224450601
Short name T538
Test name
Test status
Simulation time 2112193259 ps
CPU time 5.87 seconds
Started Mar 14 01:27:52 PM PDT 24
Finished Mar 14 01:27:58 PM PDT 24
Peak memory 200768 kb
Host smart-81e9404e-5266-4c59-b9f5-67e20ffcc7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224450601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1224450601
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.3143306372
Short name T649
Test name
Test status
Simulation time 411437191557 ps
CPU time 1140.67 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:46:56 PM PDT 24
Peak memory 200900 kb
Host smart-d5f88212-ea99-47fe-904f-7aed934e0610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143306372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.3143306372
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1582643313
Short name T307
Test name
Test status
Simulation time 36563680087 ps
CPU time 17.96 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:14 PM PDT 24
Peak memory 210596 kb
Host smart-dc7879f9-85e5-4b90-adfe-832a51e9002b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582643313 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1582643313
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.301514515
Short name T590
Test name
Test status
Simulation time 11627334096 ps
CPU time 7.74 seconds
Started Mar 14 01:27:54 PM PDT 24
Finished Mar 14 01:28:03 PM PDT 24
Peak memory 201196 kb
Host smart-566aa19a-251c-4b4a-a480-16a3d2f660ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301514515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ultra_low_pwr.301514515
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.1076210884
Short name T603
Test name
Test status
Simulation time 2012642485 ps
CPU time 5.82 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:54 PM PDT 24
Peak memory 201272 kb
Host smart-b1b5f667-340d-4f6f-88a8-c0544b30986e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076210884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.1076210884
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3718259495
Short name T200
Test name
Test status
Simulation time 3303065559 ps
CPU time 1.68 seconds
Started Mar 14 01:28:43 PM PDT 24
Finished Mar 14 01:28:45 PM PDT 24
Peak memory 201248 kb
Host smart-0b4cb26f-39c6-4ca5-a987-3c6a426597d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718259495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3
718259495
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.411347294
Short name T262
Test name
Test status
Simulation time 130129458049 ps
CPU time 335.64 seconds
Started Mar 14 01:28:42 PM PDT 24
Finished Mar 14 01:34:18 PM PDT 24
Peak memory 201404 kb
Host smart-4af3497c-a395-4a11-95d2-77de07031f0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411347294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_combo_detect.411347294
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.190648265
Short name T589
Test name
Test status
Simulation time 102429722702 ps
CPU time 283.22 seconds
Started Mar 14 01:28:44 PM PDT 24
Finished Mar 14 01:33:28 PM PDT 24
Peak memory 201516 kb
Host smart-969c33c7-8abf-41eb-84db-51d883f7a856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190648265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_wi
th_pre_cond.190648265
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.5158775
Short name T492
Test name
Test status
Simulation time 4442534102 ps
CPU time 10.52 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:28:55 PM PDT 24
Peak memory 201212 kb
Host smart-162c6f3f-9d6a-495f-8da4-88fb8369ac49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5158775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctr
l_ec_pwr_on_rst.5158775
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.505525086
Short name T662
Test name
Test status
Simulation time 2669994550 ps
CPU time 6.29 seconds
Started Mar 14 01:28:51 PM PDT 24
Finished Mar 14 01:28:57 PM PDT 24
Peak memory 201208 kb
Host smart-dd3ab911-ff26-4f3c-8611-207326e5bd9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505525086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctr
l_edge_detect.505525086
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.4185805588
Short name T604
Test name
Test status
Simulation time 2651996745 ps
CPU time 1.75 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:28:49 PM PDT 24
Peak memory 201156 kb
Host smart-8db4b169-4961-47eb-84ca-4ffcb21e5818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185805588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.4185805588
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.125753163
Short name T587
Test name
Test status
Simulation time 2515281801 ps
CPU time 1.26 seconds
Started Mar 14 01:28:51 PM PDT 24
Finished Mar 14 01:28:53 PM PDT 24
Peak memory 201204 kb
Host smart-d48aeaef-c678-45e8-8928-392bdb0342a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125753163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.125753163
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.2524761769
Short name T644
Test name
Test status
Simulation time 2162229373 ps
CPU time 6.44 seconds
Started Mar 14 01:28:50 PM PDT 24
Finished Mar 14 01:28:57 PM PDT 24
Peak memory 201160 kb
Host smart-f380ad58-abc9-4893-977e-4642298ea7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524761769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.2524761769
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2708529402
Short name T67
Test name
Test status
Simulation time 2529251420 ps
CPU time 2.3 seconds
Started Mar 14 01:28:44 PM PDT 24
Finished Mar 14 01:28:47 PM PDT 24
Peak memory 201312 kb
Host smart-a874b690-8b09-499c-be88-1961e4b142a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708529402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.2708529402
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.616868851
Short name T499
Test name
Test status
Simulation time 2132441325 ps
CPU time 2.11 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:28:47 PM PDT 24
Peak memory 201088 kb
Host smart-6ebf6d0b-8b9c-493e-86bf-0f7b70763e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616868851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.616868851
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.471546401
Short name T104
Test name
Test status
Simulation time 6631020169 ps
CPU time 11.79 seconds
Started Mar 14 01:28:48 PM PDT 24
Finished Mar 14 01:29:00 PM PDT 24
Peak memory 201240 kb
Host smart-8f369a5c-d8ee-4b46-840d-cd3e7b4a2fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471546401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_st
ress_all.471546401
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2069290438
Short name T740
Test name
Test status
Simulation time 5332274264 ps
CPU time 2.31 seconds
Started Mar 14 01:28:52 PM PDT 24
Finished Mar 14 01:28:54 PM PDT 24
Peak memory 201156 kb
Host smart-62f7dad1-dfe7-42b2-938b-05777f7396f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069290438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.2069290438
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.3134392088
Short name T696
Test name
Test status
Simulation time 2017335674 ps
CPU time 3.13 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:28:49 PM PDT 24
Peak memory 201260 kb
Host smart-60d8e951-f69c-4f04-ac57-256c79f0c509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134392088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.3134392088
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.98492899
Short name T697
Test name
Test status
Simulation time 148251019294 ps
CPU time 95.62 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:30:20 PM PDT 24
Peak memory 201312 kb
Host smart-5eef5e3b-6e9d-48af-9169-74f09b0d0ecd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98492899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctr
l_combo_detect.98492899
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3859393630
Short name T488
Test name
Test status
Simulation time 22612955782 ps
CPU time 15.16 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:29:03 PM PDT 24
Peak memory 201500 kb
Host smart-1e879d96-d7e3-4248-9ad2-f545ab3bfda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859393630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.3859393630
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1203253207
Short name T224
Test name
Test status
Simulation time 4443181638 ps
CPU time 11.55 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:59 PM PDT 24
Peak memory 201196 kb
Host smart-150b15ea-8e40-47c4-9a96-4436067c4ae7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203253207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.1203253207
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.1743599967
Short name T161
Test name
Test status
Simulation time 610949639953 ps
CPU time 413.9 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:35:42 PM PDT 24
Peak memory 201220 kb
Host smart-0bfd7c7a-a2c7-4aae-b926-546f9e309670
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743599967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.1743599967
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1645499701
Short name T522
Test name
Test status
Simulation time 2662300259 ps
CPU time 1.33 seconds
Started Mar 14 01:28:44 PM PDT 24
Finished Mar 14 01:28:46 PM PDT 24
Peak memory 201156 kb
Host smart-620117d9-ab84-4322-8bdc-912ffd19b25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645499701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.1645499701
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3270257855
Short name T493
Test name
Test status
Simulation time 2445720707 ps
CPU time 8.17 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:28:53 PM PDT 24
Peak memory 201244 kb
Host smart-170a07e6-b1b4-42d2-bfad-2696ee6482fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270257855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.3270257855
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3124687809
Short name T398
Test name
Test status
Simulation time 2172056026 ps
CPU time 1.98 seconds
Started Mar 14 01:28:44 PM PDT 24
Finished Mar 14 01:28:46 PM PDT 24
Peak memory 201168 kb
Host smart-78bcd08e-1924-4449-9774-a87a96369b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124687809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.3124687809
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.992712610
Short name T19
Test name
Test status
Simulation time 2518310571 ps
CPU time 4.23 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:51 PM PDT 24
Peak memory 201284 kb
Host smart-e7fd628a-d567-49a4-9305-51d3ecdc46fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992712610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.992712610
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.1826783452
Short name T756
Test name
Test status
Simulation time 2110258828 ps
CPU time 6.24 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:28:52 PM PDT 24
Peak memory 201144 kb
Host smart-cd454e75-b78a-4bd7-bc93-06ae88eda6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826783452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1826783452
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.765041114
Short name T549
Test name
Test status
Simulation time 15226664170 ps
CPU time 44.54 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:29:31 PM PDT 24
Peak memory 201284 kb
Host smart-d7fc55c0-5f8f-4602-a787-c543b282ff0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765041114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_st
ress_all.765041114
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1443292062
Short name T433
Test name
Test status
Simulation time 3302399123 ps
CPU time 3.74 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:28:51 PM PDT 24
Peak memory 201204 kb
Host smart-52e4b221-f228-4bfd-a996-2354f95803d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443292062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.1443292062
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2997481962
Short name T784
Test name
Test status
Simulation time 2896336611 ps
CPU time 8.57 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:56 PM PDT 24
Peak memory 201268 kb
Host smart-6331e2a2-ecd1-4bd9-9f81-45f3c49bf5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997481962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2
997481962
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3550173985
Short name T10
Test name
Test status
Simulation time 64899899544 ps
CPU time 159.19 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:31:27 PM PDT 24
Peak memory 201364 kb
Host smart-e99dc3ee-a608-47e5-8101-68b6494542ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550173985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.3550173985
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2881571156
Short name T384
Test name
Test status
Simulation time 74428847652 ps
CPU time 94.62 seconds
Started Mar 14 01:28:50 PM PDT 24
Finished Mar 14 01:30:25 PM PDT 24
Peak memory 201416 kb
Host smart-64b535c1-ced6-44ae-b94e-f8d103520b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881571156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.2881571156
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.621032071
Short name T14
Test name
Test status
Simulation time 2581947048 ps
CPU time 7.21 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:55 PM PDT 24
Peak memory 201188 kb
Host smart-57237ac9-0623-4ad5-a36a-7e7403e77848
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621032071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_ec_pwr_on_rst.621032071
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.2667155129
Short name T189
Test name
Test status
Simulation time 4876930628 ps
CPU time 4.11 seconds
Started Mar 14 01:28:51 PM PDT 24
Finished Mar 14 01:28:55 PM PDT 24
Peak memory 201208 kb
Host smart-805717ff-e15e-47f9-9154-16cdc985253b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667155129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.2667155129
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1003403029
Short name T149
Test name
Test status
Simulation time 2611573896 ps
CPU time 7.64 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:28:53 PM PDT 24
Peak memory 201156 kb
Host smart-7e67b73f-f361-4195-aabd-dcd0bdcadc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003403029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.1003403029
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.452300745
Short name T605
Test name
Test status
Simulation time 2465066301 ps
CPU time 3.92 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:52 PM PDT 24
Peak memory 201204 kb
Host smart-82132034-00d6-4037-860e-657ca41fafb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452300745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.452300745
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3553671922
Short name T233
Test name
Test status
Simulation time 2062390360 ps
CPU time 1.39 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:28:48 PM PDT 24
Peak memory 201124 kb
Host smart-693dac11-7318-4db2-9b02-c43e418dfae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553671922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3553671922
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2286832915
Short name T562
Test name
Test status
Simulation time 2512510341 ps
CPU time 3.86 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:28:49 PM PDT 24
Peak memory 201192 kb
Host smart-054c6d2c-924d-49eb-b477-97d0f163b130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286832915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2286832915
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.1950931896
Short name T563
Test name
Test status
Simulation time 2114443060 ps
CPU time 3.53 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:51 PM PDT 24
Peak memory 201136 kb
Host smart-c2811717-f530-4764-8a4c-182ebf6495ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950931896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1950931896
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.3294145094
Short name T619
Test name
Test status
Simulation time 6587233929 ps
CPU time 4.82 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:28:50 PM PDT 24
Peak memory 201196 kb
Host smart-b921a055-bd8e-4fd7-a247-e25338587acd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294145094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.3294145094
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3156281547
Short name T154
Test name
Test status
Simulation time 563037430294 ps
CPU time 65.79 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:29:53 PM PDT 24
Peak memory 201188 kb
Host smart-7568c704-6da8-4959-99bd-c4753f89befd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156281547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3156281547
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.1491760320
Short name T633
Test name
Test status
Simulation time 2021604616 ps
CPU time 3.46 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:51 PM PDT 24
Peak memory 201272 kb
Host smart-f803ed0a-4f72-48c7-9230-f46cc4e43c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491760320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.1491760320
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3550166797
Short name T794
Test name
Test status
Simulation time 3318067289 ps
CPU time 3.52 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:28:51 PM PDT 24
Peak memory 201276 kb
Host smart-fc6efccb-f59a-48c0-97f2-ca86fa0912a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550166797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3
550166797
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.2074369951
Short name T358
Test name
Test status
Simulation time 128421545742 ps
CPU time 334.96 seconds
Started Mar 14 01:28:48 PM PDT 24
Finished Mar 14 01:34:23 PM PDT 24
Peak memory 201368 kb
Host smart-8bbd40d6-a7a3-457a-aeb5-919babebf4fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074369951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.2074369951
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1377265143
Short name T567
Test name
Test status
Simulation time 3866451889 ps
CPU time 10.22 seconds
Started Mar 14 01:28:48 PM PDT 24
Finished Mar 14 01:28:59 PM PDT 24
Peak memory 201124 kb
Host smart-7a419396-517f-4c90-bdcf-0975608fcf9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377265143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.1377265143
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.1755700333
Short name T610
Test name
Test status
Simulation time 4577710321 ps
CPU time 10.56 seconds
Started Mar 14 01:28:43 PM PDT 24
Finished Mar 14 01:28:54 PM PDT 24
Peak memory 201176 kb
Host smart-05643a71-7905-47f9-b4e0-269cc36d2dce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755700333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.1755700333
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2242969383
Short name T551
Test name
Test status
Simulation time 2611225052 ps
CPU time 7.48 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:56 PM PDT 24
Peak memory 201200 kb
Host smart-1574d54b-d4ab-4da9-8aa5-40b7604405b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242969383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.2242969383
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.798223688
Short name T214
Test name
Test status
Simulation time 2454539541 ps
CPU time 6.73 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:55 PM PDT 24
Peak memory 201204 kb
Host smart-36446bba-e090-43fb-8d9f-8e2385781b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798223688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.798223688
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3978608291
Short name T303
Test name
Test status
Simulation time 2261824590 ps
CPU time 3.74 seconds
Started Mar 14 01:28:51 PM PDT 24
Finished Mar 14 01:28:55 PM PDT 24
Peak memory 201188 kb
Host smart-3b1d5f28-8ac7-4248-8b9b-ff4e1bea8436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978608291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.3978608291
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2586755433
Short name T561
Test name
Test status
Simulation time 2518406131 ps
CPU time 3.92 seconds
Started Mar 14 01:28:52 PM PDT 24
Finished Mar 14 01:28:56 PM PDT 24
Peak memory 201236 kb
Host smart-fc0f9766-74e3-4a2c-81df-724370936f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586755433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2586755433
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.4080085401
Short name T454
Test name
Test status
Simulation time 2118312040 ps
CPU time 3.52 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:28:49 PM PDT 24
Peak memory 201100 kb
Host smart-3fbbd08a-da71-43cf-841d-901a0fc27f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080085401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.4080085401
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.4114814602
Short name T540
Test name
Test status
Simulation time 9057040889 ps
CPU time 27.84 seconds
Started Mar 14 01:28:46 PM PDT 24
Finished Mar 14 01:29:14 PM PDT 24
Peak memory 201196 kb
Host smart-724a2dd6-2e22-4643-ad37-331c8b088812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114814602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.4114814602
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.935730691
Short name T114
Test name
Test status
Simulation time 45256404204 ps
CPU time 120.9 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 209860 kb
Host smart-6b5c4c38-da42-4840-9f2e-125d4cb5e3c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935730691 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.935730691
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2706324565
Short name T542
Test name
Test status
Simulation time 4626881675 ps
CPU time 2.12 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:50 PM PDT 24
Peak memory 201220 kb
Host smart-a78b8b49-9c2e-4982-ba75-44ac5d17207c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706324565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.2706324565
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.4158248029
Short name T675
Test name
Test status
Simulation time 2033853880 ps
CPU time 2.02 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:03 PM PDT 24
Peak memory 201288 kb
Host smart-04a8d4e8-d80b-46d8-a14a-6f712ccbb0da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158248029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.4158248029
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2223182914
Short name T463
Test name
Test status
Simulation time 3300346967 ps
CPU time 2.71 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:51 PM PDT 24
Peak memory 201208 kb
Host smart-f26417be-9b3f-4083-b6ed-d790e99c4d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223182914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.2
223182914
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.3966189057
Short name T256
Test name
Test status
Simulation time 64501324191 ps
CPU time 169.46 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:31:46 PM PDT 24
Peak memory 201392 kb
Host smart-b066f7df-2574-4adc-8ec8-31700c8cda97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966189057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.3966189057
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2399834802
Short name T636
Test name
Test status
Simulation time 69234795244 ps
CPU time 43.74 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:29:40 PM PDT 24
Peak memory 201380 kb
Host smart-399cfb12-f312-4a1c-99d2-2e873a299d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399834802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.2399834802
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3723738359
Short name T630
Test name
Test status
Simulation time 2564049579 ps
CPU time 7.74 seconds
Started Mar 14 01:28:47 PM PDT 24
Finished Mar 14 01:28:56 PM PDT 24
Peak memory 201148 kb
Host smart-48ab441b-cd12-41d2-9e1c-527d6f5a0729
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723738359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.3723738359
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2679902024
Short name T580
Test name
Test status
Simulation time 2612207519 ps
CPU time 4.09 seconds
Started Mar 14 01:28:50 PM PDT 24
Finished Mar 14 01:28:54 PM PDT 24
Peak memory 201172 kb
Host smart-e6585649-5370-4fca-8d0e-e9d67ab0e359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679902024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.2679902024
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.1724656844
Short name T526
Test name
Test status
Simulation time 2493417749 ps
CPU time 2.33 seconds
Started Mar 14 01:28:50 PM PDT 24
Finished Mar 14 01:28:53 PM PDT 24
Peak memory 201196 kb
Host smart-b037b96e-1e19-4aab-b4ec-7b9138ca9686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724656844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.1724656844
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.4251017452
Short name T734
Test name
Test status
Simulation time 2046572671 ps
CPU time 5.72 seconds
Started Mar 14 01:28:48 PM PDT 24
Finished Mar 14 01:28:54 PM PDT 24
Peak memory 201148 kb
Host smart-e3a97543-a7f4-4416-8441-ff73c09bdc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251017452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.4251017452
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.1865697991
Short name T440
Test name
Test status
Simulation time 2545654467 ps
CPU time 2.13 seconds
Started Mar 14 01:28:50 PM PDT 24
Finished Mar 14 01:28:52 PM PDT 24
Peak memory 201268 kb
Host smart-a24b333e-3b2a-44d0-8ffd-8ac96f0edeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865697991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.1865697991
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.800489349
Short name T525
Test name
Test status
Simulation time 2117631989 ps
CPU time 3.24 seconds
Started Mar 14 01:28:45 PM PDT 24
Finished Mar 14 01:28:48 PM PDT 24
Peak memory 201112 kb
Host smart-fb4b16eb-7439-4d18-a486-57caceb045ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800489349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.800489349
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1628472391
Short name T308
Test name
Test status
Simulation time 54170698817 ps
CPU time 37.37 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:29:34 PM PDT 24
Peak memory 217992 kb
Host smart-c527c3b1-ec97-452d-bb10-f0958d410f81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628472391 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1628472391
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1111522936
Short name T426
Test name
Test status
Simulation time 2378649398 ps
CPU time 3.49 seconds
Started Mar 14 01:28:55 PM PDT 24
Finished Mar 14 01:28:59 PM PDT 24
Peak memory 201240 kb
Host smart-3695c3f5-5b33-4173-8397-18105a75b0fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111522936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1111522936
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.3474908891
Short name T685
Test name
Test status
Simulation time 2058911310 ps
CPU time 1.9 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:28:58 PM PDT 24
Peak memory 201240 kb
Host smart-7ff2c077-9c9b-4588-96a0-19d59b628b76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474908891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.3474908891
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2230187309
Short name T237
Test name
Test status
Simulation time 3585051493 ps
CPU time 10.66 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:08 PM PDT 24
Peak memory 201232 kb
Host smart-4d08407e-37eb-4c45-9b0b-9a086aa03b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230187309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.2
230187309
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1433903851
Short name T264
Test name
Test status
Simulation time 90139001711 ps
CPU time 241.12 seconds
Started Mar 14 01:28:59 PM PDT 24
Finished Mar 14 01:33:00 PM PDT 24
Peak memory 201464 kb
Host smart-cf5c6ae2-3f63-464c-a8ae-281ccabc2f45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433903851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.1433903851
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2088328737
Short name T625
Test name
Test status
Simulation time 117242742140 ps
CPU time 64.93 seconds
Started Mar 14 01:28:58 PM PDT 24
Finished Mar 14 01:30:04 PM PDT 24
Peak memory 201520 kb
Host smart-445f25b2-d0fb-4f22-9b6c-8e22e2a13301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088328737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.2088328737
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.3019271100
Short name T126
Test name
Test status
Simulation time 4901302923 ps
CPU time 7.68 seconds
Started Mar 14 01:28:59 PM PDT 24
Finished Mar 14 01:29:07 PM PDT 24
Peak memory 201164 kb
Host smart-c2941349-b0b7-4e83-88e3-7cba59c464f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019271100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.3019271100
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.1493099926
Short name T688
Test name
Test status
Simulation time 2613026982 ps
CPU time 7.67 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:05 PM PDT 24
Peak memory 201164 kb
Host smart-e42267aa-c518-4dda-bf7b-3862a996cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493099926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.1493099926
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1670509866
Short name T127
Test name
Test status
Simulation time 2441240261 ps
CPU time 4.37 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:29:01 PM PDT 24
Peak memory 201184 kb
Host smart-9a2331c8-d90d-41f0-8bd5-a78974ac1385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670509866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1670509866
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.74176061
Short name T578
Test name
Test status
Simulation time 2205720728 ps
CPU time 1.95 seconds
Started Mar 14 01:29:05 PM PDT 24
Finished Mar 14 01:29:07 PM PDT 24
Peak memory 201196 kb
Host smart-6399eb84-0a87-47c3-917a-8d32b99498b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74176061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.74176061
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3387804274
Short name T623
Test name
Test status
Simulation time 2510949299 ps
CPU time 6.84 seconds
Started Mar 14 01:28:59 PM PDT 24
Finished Mar 14 01:29:06 PM PDT 24
Peak memory 201224 kb
Host smart-f67f8a26-cd3e-4355-94e6-a2632f41558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387804274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.3387804274
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.2321142898
Short name T191
Test name
Test status
Simulation time 2110047327 ps
CPU time 6.17 seconds
Started Mar 14 01:28:54 PM PDT 24
Finished Mar 14 01:29:00 PM PDT 24
Peak memory 201112 kb
Host smart-9aef09f6-c0eb-4c16-815a-57948ddb32a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321142898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2321142898
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2293579486
Short name T752
Test name
Test status
Simulation time 28262717814 ps
CPU time 17.66 seconds
Started Mar 14 01:29:01 PM PDT 24
Finished Mar 14 01:29:19 PM PDT 24
Peak memory 201556 kb
Host smart-85cb9c80-5d0f-4918-92ff-0edaaf98aed0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293579486 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2293579486
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.735069361
Short name T147
Test name
Test status
Simulation time 6996547561 ps
CPU time 7.35 seconds
Started Mar 14 01:28:58 PM PDT 24
Finished Mar 14 01:29:06 PM PDT 24
Peak memory 201180 kb
Host smart-30ee3a94-13c0-460e-9e68-c4c6f3113c85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735069361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ultra_low_pwr.735069361
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.1808849152
Short name T330
Test name
Test status
Simulation time 2055218257 ps
CPU time 1.55 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:28:58 PM PDT 24
Peak memory 201312 kb
Host smart-d161723e-d9bb-495d-a6e4-6b3a53237736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808849152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.1808849152
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2286575530
Short name T511
Test name
Test status
Simulation time 41248807203 ps
CPU time 8.53 seconds
Started Mar 14 01:29:01 PM PDT 24
Finished Mar 14 01:29:10 PM PDT 24
Peak memory 201208 kb
Host smart-6a26d09e-2867-44f4-95f3-2c9c20e82a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286575530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2
286575530
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3832242950
Short name T389
Test name
Test status
Simulation time 94884963504 ps
CPU time 57.22 seconds
Started Mar 14 01:28:58 PM PDT 24
Finished Mar 14 01:29:56 PM PDT 24
Peak memory 201300 kb
Host smart-303fa145-488d-4102-8843-5eee4d1da390
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832242950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.3832242950
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3801005114
Short name T457
Test name
Test status
Simulation time 92826316609 ps
CPU time 116.06 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:30:52 PM PDT 24
Peak memory 201448 kb
Host smart-049b9222-28cc-446e-b31c-9cc9b1b70739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801005114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.3801005114
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2231820867
Short name T556
Test name
Test status
Simulation time 3652643545 ps
CPU time 9.17 seconds
Started Mar 14 01:28:55 PM PDT 24
Finished Mar 14 01:29:05 PM PDT 24
Peak memory 201180 kb
Host smart-3c547c18-52d4-472f-9b70-9558ad0a26a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231820867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.2231820867
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.3480667910
Short name T185
Test name
Test status
Simulation time 2533062835 ps
CPU time 2.43 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:00 PM PDT 24
Peak memory 201192 kb
Host smart-c55da5f0-2e0a-4251-9edc-dab60b4a657b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480667910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.3480667910
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.94577268
Short name T168
Test name
Test status
Simulation time 2607402426 ps
CPU time 7.29 seconds
Started Mar 14 01:28:59 PM PDT 24
Finished Mar 14 01:29:07 PM PDT 24
Peak memory 201156 kb
Host smart-d2fa9528-b078-43c9-abdf-d58557a4f08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94577268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.94577268
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2246476064
Short name T678
Test name
Test status
Simulation time 2472167612 ps
CPU time 2.24 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:28:58 PM PDT 24
Peak memory 201176 kb
Host smart-8af97446-9c5f-4d2f-9fd0-d5297b132da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246476064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.2246476064
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.585900892
Short name T599
Test name
Test status
Simulation time 2166783651 ps
CPU time 6.01 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:07 PM PDT 24
Peak memory 201220 kb
Host smart-d1d355c5-0d51-408b-ae94-fcacb8599354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585900892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.585900892
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3467414845
Short name T212
Test name
Test status
Simulation time 2522169520 ps
CPU time 2.34 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:00 PM PDT 24
Peak memory 201240 kb
Host smart-8f092ce9-0d44-4b4f-b3a4-05033bcd3019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467414845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3467414845
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.32226315
Short name T105
Test name
Test status
Simulation time 2111234911 ps
CPU time 6.29 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:03 PM PDT 24
Peak memory 201120 kb
Host smart-fdf19e2f-cf8d-4a06-894b-2cf9f0edf035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32226315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.32226315
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.185038790
Short name T514
Test name
Test status
Simulation time 7219906147 ps
CPU time 18.43 seconds
Started Mar 14 01:28:58 PM PDT 24
Finished Mar 14 01:29:17 PM PDT 24
Peak memory 201120 kb
Host smart-755065a1-f093-4173-a9cc-c51660517723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185038790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_st
ress_all.185038790
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.4247234392
Short name T336
Test name
Test status
Simulation time 4472170181 ps
CPU time 6.05 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:29:02 PM PDT 24
Peak memory 201192 kb
Host smart-7aa95429-f173-446c-a70f-2b87feaa573d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247234392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.4247234392
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.1557361388
Short name T576
Test name
Test status
Simulation time 2021965240 ps
CPU time 2.93 seconds
Started Mar 14 01:29:01 PM PDT 24
Finished Mar 14 01:29:05 PM PDT 24
Peak memory 201280 kb
Host smart-256d36ea-7ea0-43f0-8f88-561dfb52a853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557361388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.1557361388
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2753983575
Short name T44
Test name
Test status
Simulation time 3643257738 ps
CPU time 5.1 seconds
Started Mar 14 01:29:02 PM PDT 24
Finished Mar 14 01:29:07 PM PDT 24
Peak memory 201284 kb
Host smart-d058561a-8636-4e72-86e5-8577cefa8a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753983575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
753983575
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.4201229802
Short name T718
Test name
Test status
Simulation time 160745091445 ps
CPU time 116.88 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:30:54 PM PDT 24
Peak memory 201364 kb
Host smart-a8601b8d-ee66-4f36-9609-4625bf9fae85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201229802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.4201229802
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3823327036
Short name T748
Test name
Test status
Simulation time 119648625559 ps
CPU time 149.22 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:31:29 PM PDT 24
Peak memory 201536 kb
Host smart-1c3bacfd-cceb-4132-91f9-e7d6d884ed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823327036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.3823327036
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.742704853
Short name T545
Test name
Test status
Simulation time 232232455342 ps
CPU time 307.72 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:34:04 PM PDT 24
Peak memory 201240 kb
Host smart-f953a87c-5e2b-4683-ac7f-246a764f6483
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742704853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ec_pwr_on_rst.742704853
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.4104087523
Short name T219
Test name
Test status
Simulation time 4962501665 ps
CPU time 1.17 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:28:57 PM PDT 24
Peak memory 201188 kb
Host smart-87877519-530c-4661-9745-def774b40e53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104087523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.4104087523
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.4281230284
Short name T608
Test name
Test status
Simulation time 2610532780 ps
CPU time 7.61 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:05 PM PDT 24
Peak memory 201216 kb
Host smart-8a9d7bff-240f-4b41-a858-9ceb533e7435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281230284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.4281230284
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3198025716
Short name T635
Test name
Test status
Simulation time 2472013373 ps
CPU time 2.34 seconds
Started Mar 14 01:29:05 PM PDT 24
Finished Mar 14 01:29:08 PM PDT 24
Peak memory 201196 kb
Host smart-f813ed2f-52aa-454a-8347-250fb4d0f972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198025716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3198025716
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.2790317568
Short name T234
Test name
Test status
Simulation time 2188030502 ps
CPU time 3.69 seconds
Started Mar 14 01:28:54 PM PDT 24
Finished Mar 14 01:28:58 PM PDT 24
Peak memory 201188 kb
Host smart-98fd6f9d-ba4b-4e70-9073-208e13f2a55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790317568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.2790317568
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.905917972
Short name T422
Test name
Test status
Simulation time 2512596570 ps
CPU time 6.59 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:06 PM PDT 24
Peak memory 201268 kb
Host smart-fe66a4cd-7a86-49b4-a3a2-00a46c160d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905917972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.905917972
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.265421896
Short name T246
Test name
Test status
Simulation time 2113942954 ps
CPU time 6.29 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:06 PM PDT 24
Peak memory 201100 kb
Host smart-55a0c794-262e-4652-943e-a3eacf14cf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265421896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.265421896
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.2611190277
Short name T193
Test name
Test status
Simulation time 247501815097 ps
CPU time 172.06 seconds
Started Mar 14 01:28:59 PM PDT 24
Finished Mar 14 01:31:51 PM PDT 24
Peak memory 201264 kb
Host smart-894dca25-3720-464b-a8e4-a81863468e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611190277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.2611190277
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.377434159
Short name T279
Test name
Test status
Simulation time 43960804843 ps
CPU time 104.95 seconds
Started Mar 14 01:28:59 PM PDT 24
Finished Mar 14 01:30:44 PM PDT 24
Peak memory 209880 kb
Host smart-e88068e4-6cf0-4ba9-97c7-785e454b44dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377434159 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.377434159
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.300674467
Short name T701
Test name
Test status
Simulation time 9064857703 ps
CPU time 2.38 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:00 PM PDT 24
Peak memory 201204 kb
Host smart-93ad884b-4698-43fa-baa5-b1b2452d79cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300674467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ultra_low_pwr.300674467
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.1331515826
Short name T497
Test name
Test status
Simulation time 2014124420 ps
CPU time 5.86 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:07 PM PDT 24
Peak memory 201272 kb
Host smart-d9a61e49-c027-4f3e-8e4f-f000cba2ad4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331515826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.1331515826
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.1492599007
Short name T455
Test name
Test status
Simulation time 3309844947 ps
CPU time 7.72 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:05 PM PDT 24
Peak memory 201276 kb
Host smart-e4db7f05-4b93-4791-af77-46170f084e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492599007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.1
492599007
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2412136848
Short name T101
Test name
Test status
Simulation time 95917936254 ps
CPU time 20.67 seconds
Started Mar 14 01:28:59 PM PDT 24
Finished Mar 14 01:29:19 PM PDT 24
Peak memory 201432 kb
Host smart-2e4f85b3-0ba6-4f47-9ecb-a743f4b0b176
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412136848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.2412136848
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.547240406
Short name T614
Test name
Test status
Simulation time 34453948181 ps
CPU time 75.99 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:30:17 PM PDT 24
Peak memory 201492 kb
Host smart-7cd2909c-6c5d-4fcb-9a29-6490931e2951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547240406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_wi
th_pre_cond.547240406
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.470988087
Short name T501
Test name
Test status
Simulation time 2578679771 ps
CPU time 1.62 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:02 PM PDT 24
Peak memory 201224 kb
Host smart-e202ff4b-94ad-4dd8-bacf-8503f78e3893
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470988087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_ec_pwr_on_rst.470988087
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1754380046
Short name T159
Test name
Test status
Simulation time 4964749821 ps
CPU time 9.81 seconds
Started Mar 14 01:28:59 PM PDT 24
Finished Mar 14 01:29:09 PM PDT 24
Peak memory 201240 kb
Host smart-ceb6ae2e-fa8c-4218-8757-e80220be0590
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754380046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.1754380046
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2275151455
Short name T785
Test name
Test status
Simulation time 2628475364 ps
CPU time 2.38 seconds
Started Mar 14 01:28:56 PM PDT 24
Finished Mar 14 01:28:59 PM PDT 24
Peak memory 201184 kb
Host smart-e0d2d219-ca88-448a-8ef9-f9cbbd1795fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275151455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2275151455
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1593162142
Short name T407
Test name
Test status
Simulation time 2462263136 ps
CPU time 3.94 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:01 PM PDT 24
Peak memory 201196 kb
Host smart-418f430a-d773-44a8-be8c-9962c0f2fad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593162142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.1593162142
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.2345073278
Short name T327
Test name
Test status
Simulation time 2096724136 ps
CPU time 6.27 seconds
Started Mar 14 01:28:58 PM PDT 24
Finished Mar 14 01:29:05 PM PDT 24
Peak memory 201128 kb
Host smart-ae73297c-86be-44df-9203-2cacd9dc1fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345073278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2345073278
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1843337815
Short name T745
Test name
Test status
Simulation time 2514187448 ps
CPU time 6.91 seconds
Started Mar 14 01:29:01 PM PDT 24
Finished Mar 14 01:29:09 PM PDT 24
Peak memory 201280 kb
Host smart-982757a2-bb40-4c72-8d2a-7fbe3d6a8603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843337815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1843337815
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.2311402838
Short name T5
Test name
Test status
Simulation time 2134694080 ps
CPU time 1.79 seconds
Started Mar 14 01:29:01 PM PDT 24
Finished Mar 14 01:29:03 PM PDT 24
Peak memory 201164 kb
Host smart-06063fb0-a870-44c7-b7a1-bcf040e6fee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311402838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.2311402838
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.1175319740
Short name T337
Test name
Test status
Simulation time 266811487085 ps
CPU time 43.06 seconds
Started Mar 14 01:28:57 PM PDT 24
Finished Mar 14 01:29:41 PM PDT 24
Peak memory 201276 kb
Host smart-0d803bbf-8dec-4a60-84fa-a731762adc31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175319740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.1175319740
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.571617686
Short name T436
Test name
Test status
Simulation time 16478940765 ps
CPU time 22.4 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:23 PM PDT 24
Peak memory 209860 kb
Host smart-128baa0a-4dd3-42dd-adbd-a782db4753a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571617686 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.571617686
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.3076810253
Short name T173
Test name
Test status
Simulation time 2017792768 ps
CPU time 3.24 seconds
Started Mar 14 01:29:10 PM PDT 24
Finished Mar 14 01:29:14 PM PDT 24
Peak memory 201248 kb
Host smart-68268196-75c9-4477-9ce4-ad7975098b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076810253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.3076810253
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2228501902
Short name T48
Test name
Test status
Simulation time 434558743820 ps
CPU time 1203.82 seconds
Started Mar 14 01:29:01 PM PDT 24
Finished Mar 14 01:49:05 PM PDT 24
Peak memory 201272 kb
Host smart-3f0bf360-3721-496c-af7c-d1c6c9442995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228501902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.2
228501902
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2286738287
Short name T553
Test name
Test status
Simulation time 3075900264 ps
CPU time 4.66 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:05 PM PDT 24
Peak memory 201248 kb
Host smart-5945256b-08d5-48c2-9687-5dcf79b1d554
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286738287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.2286738287
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.723249518
Short name T731
Test name
Test status
Simulation time 3657856988 ps
CPU time 1.66 seconds
Started Mar 14 01:29:08 PM PDT 24
Finished Mar 14 01:29:10 PM PDT 24
Peak memory 201180 kb
Host smart-4b58397d-adee-4a6e-865b-26395f93ebce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723249518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctr
l_edge_detect.723249518
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1926404680
Short name T53
Test name
Test status
Simulation time 2755734426 ps
CPU time 1.02 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:01 PM PDT 24
Peak memory 201228 kb
Host smart-a5e38f3a-d754-4e82-b016-b478f2e6d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926404680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1926404680
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.1525155271
Short name T130
Test name
Test status
Simulation time 2454412045 ps
CPU time 7.18 seconds
Started Mar 14 01:29:01 PM PDT 24
Finished Mar 14 01:29:08 PM PDT 24
Peak memory 201208 kb
Host smart-a676621c-6cbb-4194-ac66-d8e454cf64f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525155271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.1525155271
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.2832316978
Short name T322
Test name
Test status
Simulation time 2048223432 ps
CPU time 5.27 seconds
Started Mar 14 01:29:01 PM PDT 24
Finished Mar 14 01:29:06 PM PDT 24
Peak memory 201140 kb
Host smart-4b17e4ea-147b-4abd-bcbe-b9a5e79ec3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832316978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.2832316978
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1952478429
Short name T469
Test name
Test status
Simulation time 2529428034 ps
CPU time 2.36 seconds
Started Mar 14 01:28:55 PM PDT 24
Finished Mar 14 01:28:57 PM PDT 24
Peak memory 201248 kb
Host smart-060953dd-e9a2-4242-8570-ff8354f3290c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952478429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.1952478429
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.3047873248
Short name T581
Test name
Test status
Simulation time 2123774247 ps
CPU time 2.01 seconds
Started Mar 14 01:29:01 PM PDT 24
Finished Mar 14 01:29:03 PM PDT 24
Peak memory 201160 kb
Host smart-b8e55302-304a-4dc1-8f88-7507944c6d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047873248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3047873248
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.1298261851
Short name T231
Test name
Test status
Simulation time 15877767096 ps
CPU time 43.19 seconds
Started Mar 14 01:29:07 PM PDT 24
Finished Mar 14 01:29:51 PM PDT 24
Peak memory 201288 kb
Host smart-07e52a11-c3e1-4eec-80ae-89e4c92f0358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298261851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.1298261851
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2054565462
Short name T280
Test name
Test status
Simulation time 25335021507 ps
CPU time 53.13 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:30:04 PM PDT 24
Peak memory 209876 kb
Host smart-400e7eb3-b4cf-48d2-836c-1ac03b9d9660
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054565462 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2054565462
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2452278637
Short name T119
Test name
Test status
Simulation time 92026378497 ps
CPU time 7.63 seconds
Started Mar 14 01:29:00 PM PDT 24
Finished Mar 14 01:29:08 PM PDT 24
Peak memory 201252 kb
Host smart-58a91033-8263-4412-8e6d-17c5e5df1e27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452278637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2452278637
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.1721114835
Short name T435
Test name
Test status
Simulation time 2040443144 ps
CPU time 1.9 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:28:06 PM PDT 24
Peak memory 201164 kb
Host smart-37012004-3e12-4fc3-b883-616df447e682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721114835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.1721114835
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3071891336
Short name T46
Test name
Test status
Simulation time 3600393045 ps
CPU time 2.3 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:27:57 PM PDT 24
Peak memory 201236 kb
Host smart-bce35b99-0a2a-454e-9c16-46e6e6506855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071891336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3071891336
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.512469766
Short name T655
Test name
Test status
Simulation time 45638878542 ps
CPU time 58.78 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:28:52 PM PDT 24
Peak memory 201404 kb
Host smart-70a1143b-8ac1-461b-bd92-2f382cb0d52d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512469766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_combo_detect.512469766
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.407379064
Short name T626
Test name
Test status
Simulation time 2228722019 ps
CPU time 1.41 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:27:55 PM PDT 24
Peak memory 201180 kb
Host smart-78e77e9e-3b2b-4770-8e05-b1ecf68744ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407379064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.407379064
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3131905083
Short name T179
Test name
Test status
Simulation time 2528698506 ps
CPU time 2.41 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:27:56 PM PDT 24
Peak memory 201164 kb
Host smart-19df6027-d908-4113-bd04-e85105065190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131905083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3131905083
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1597465062
Short name T132
Test name
Test status
Simulation time 60255603765 ps
CPU time 157.94 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:30:34 PM PDT 24
Peak memory 201116 kb
Host smart-b0c64ab9-c07f-449f-9cb5-ff26702d7898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597465062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.1597465062
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1086301795
Short name T768
Test name
Test status
Simulation time 3730353613 ps
CPU time 10.53 seconds
Started Mar 14 01:27:48 PM PDT 24
Finished Mar 14 01:27:58 PM PDT 24
Peak memory 201180 kb
Host smart-2719cee1-09d1-4a76-8a88-b15ef58ebefc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086301795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.1086301795
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3779952241
Short name T534
Test name
Test status
Simulation time 3022988267 ps
CPU time 8.21 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:04 PM PDT 24
Peak memory 201132 kb
Host smart-6af20d05-45d0-439f-9d08-59c521dfad1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779952241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.3779952241
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.4007710311
Short name T70
Test name
Test status
Simulation time 2608707612 ps
CPU time 7.61 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:04 PM PDT 24
Peak memory 201120 kb
Host smart-67ef7ab5-890a-449f-931d-e74ecec77828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007710311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.4007710311
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.4149272137
Short name T333
Test name
Test status
Simulation time 2458448608 ps
CPU time 3.96 seconds
Started Mar 14 01:27:49 PM PDT 24
Finished Mar 14 01:27:53 PM PDT 24
Peak memory 201212 kb
Host smart-0b42846c-b724-4221-b1f9-fdc6d277ae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149272137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.4149272137
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1413569139
Short name T415
Test name
Test status
Simulation time 2151004788 ps
CPU time 6.38 seconds
Started Mar 14 01:27:46 PM PDT 24
Finished Mar 14 01:27:52 PM PDT 24
Peak memory 201168 kb
Host smart-fac83f42-b2c5-4f11-9064-e3879d8c81fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413569139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.1413569139
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.3598085419
Short name T429
Test name
Test status
Simulation time 2518753735 ps
CPU time 3.92 seconds
Started Mar 14 01:27:53 PM PDT 24
Finished Mar 14 01:27:58 PM PDT 24
Peak memory 201268 kb
Host smart-691df370-48ce-4a90-9c62-cb70ed0ec648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598085419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.3598085419
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.451603706
Short name T270
Test name
Test status
Simulation time 22017873733 ps
CPU time 32.2 seconds
Started Mar 14 01:28:03 PM PDT 24
Finished Mar 14 01:28:36 PM PDT 24
Peak memory 220864 kb
Host smart-70a6a598-2986-4aa4-9bbb-caaccca368f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451603706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.451603706
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2329656783
Short name T704
Test name
Test status
Simulation time 2117582144 ps
CPU time 3.45 seconds
Started Mar 14 01:27:48 PM PDT 24
Finished Mar 14 01:27:52 PM PDT 24
Peak memory 201180 kb
Host smart-9f6d2f92-795c-4578-9a66-d3782504dc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329656783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2329656783
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.3985470448
Short name T394
Test name
Test status
Simulation time 16109060792 ps
CPU time 23.04 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:28:19 PM PDT 24
Peak memory 201196 kb
Host smart-b60642bd-6ded-4f2e-a62a-a51c6102ab5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985470448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.3985470448
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3925561803
Short name T305
Test name
Test status
Simulation time 103953098146 ps
CPU time 203.1 seconds
Started Mar 14 01:27:56 PM PDT 24
Finished Mar 14 01:31:19 PM PDT 24
Peak memory 209724 kb
Host smart-d25f543a-e4d3-436b-8460-9b2de8960894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925561803 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.3925561803
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1642767695
Short name T730
Test name
Test status
Simulation time 3682729346 ps
CPU time 2.16 seconds
Started Mar 14 01:27:49 PM PDT 24
Finished Mar 14 01:27:51 PM PDT 24
Peak memory 201172 kb
Host smart-34e34eb5-6f1d-4435-bd37-e72c2658dd56
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642767695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.1642767695
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.617602160
Short name T512
Test name
Test status
Simulation time 2010763156 ps
CPU time 5.66 seconds
Started Mar 14 01:29:08 PM PDT 24
Finished Mar 14 01:29:14 PM PDT 24
Peak memory 201328 kb
Host smart-8f64be3e-faf2-4905-b7eb-242487707304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617602160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_tes
t.617602160
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3237938050
Short name T49
Test name
Test status
Simulation time 3436291543 ps
CPU time 5.08 seconds
Started Mar 14 01:29:10 PM PDT 24
Finished Mar 14 01:29:17 PM PDT 24
Peak memory 201268 kb
Host smart-66ed8b88-cdf7-40d2-9b6d-46125e73420a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237938050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.3
237938050
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.3412640315
Short name T385
Test name
Test status
Simulation time 172170706151 ps
CPU time 393.25 seconds
Started Mar 14 01:29:10 PM PDT 24
Finished Mar 14 01:35:45 PM PDT 24
Peak memory 201392 kb
Host smart-86280035-dcb4-4285-aaa7-d90398e3ddbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412640315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.3412640315
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.825156139
Short name T392
Test name
Test status
Simulation time 101952536447 ps
CPU time 274.43 seconds
Started Mar 14 01:29:08 PM PDT 24
Finished Mar 14 01:33:43 PM PDT 24
Peak memory 201416 kb
Host smart-02c3157e-3ccc-411b-92c6-ed965694f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825156139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_wi
th_pre_cond.825156139
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1554823408
Short name T169
Test name
Test status
Simulation time 3221270607 ps
CPU time 2.66 seconds
Started Mar 14 01:29:10 PM PDT 24
Finished Mar 14 01:29:14 PM PDT 24
Peak memory 201232 kb
Host smart-7d78681d-5211-4bf0-bb9b-7e7f6803e4a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554823408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.1554823408
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1339224060
Short name T477
Test name
Test status
Simulation time 2613344573 ps
CPU time 7.51 seconds
Started Mar 14 01:29:08 PM PDT 24
Finished Mar 14 01:29:16 PM PDT 24
Peak memory 201220 kb
Host smart-ccc2c284-4098-40ad-9ad9-0f6acdda43aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339224060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1339224060
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.784737542
Short name T668
Test name
Test status
Simulation time 2444487328 ps
CPU time 7.73 seconds
Started Mar 14 01:29:08 PM PDT 24
Finished Mar 14 01:29:16 PM PDT 24
Peak memory 201184 kb
Host smart-74dc0352-2c08-47f8-8935-cd91792c8681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784737542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.784737542
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3410098748
Short name T571
Test name
Test status
Simulation time 2148282876 ps
CPU time 3.66 seconds
Started Mar 14 01:29:10 PM PDT 24
Finished Mar 14 01:29:14 PM PDT 24
Peak memory 201184 kb
Host smart-81dc9cd5-d8a8-43a5-82fb-046297418672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410098748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3410098748
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.853811143
Short name T326
Test name
Test status
Simulation time 2617806403 ps
CPU time 1.21 seconds
Started Mar 14 01:29:06 PM PDT 24
Finished Mar 14 01:29:08 PM PDT 24
Peak memory 201312 kb
Host smart-f17d3941-ad88-45ea-a092-8110cf1983c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853811143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.853811143
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.4156834131
Short name T596
Test name
Test status
Simulation time 2152936990 ps
CPU time 1.52 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:11 PM PDT 24
Peak memory 201196 kb
Host smart-6aa0b796-8b17-4337-bed4-95acffd7fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156834131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.4156834131
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.3418750104
Short name T557
Test name
Test status
Simulation time 14905585430 ps
CPU time 20.87 seconds
Started Mar 14 01:29:07 PM PDT 24
Finished Mar 14 01:29:28 PM PDT 24
Peak memory 201372 kb
Host smart-b571c99e-e1b3-4041-8d38-8685a2e1a162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418750104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.3418750104
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1647899140
Short name T763
Test name
Test status
Simulation time 13346985646 ps
CPU time 10.65 seconds
Started Mar 14 01:29:08 PM PDT 24
Finished Mar 14 01:29:20 PM PDT 24
Peak memory 201172 kb
Host smart-ceff98c2-6d75-45ae-8071-4f0e85235282
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647899140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.1647899140
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.877247746
Short name T569
Test name
Test status
Simulation time 2011992019 ps
CPU time 6.03 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:16 PM PDT 24
Peak memory 201280 kb
Host smart-0454b506-447c-4662-bead-e9258abab126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877247746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_tes
t.877247746
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3284055473
Short name T181
Test name
Test status
Simulation time 3140589943 ps
CPU time 2.36 seconds
Started Mar 14 01:29:08 PM PDT 24
Finished Mar 14 01:29:11 PM PDT 24
Peak memory 201256 kb
Host smart-65a146a5-653a-4634-b760-669607bb5518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284055473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3
284055473
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.3933626900
Short name T254
Test name
Test status
Simulation time 79648079640 ps
CPU time 204.67 seconds
Started Mar 14 01:29:07 PM PDT 24
Finished Mar 14 01:32:33 PM PDT 24
Peak memory 201300 kb
Host smart-0873efc2-12ca-471c-be3e-b9ff182f87db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933626900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.3933626900
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1915819566
Short name T420
Test name
Test status
Simulation time 3543813731 ps
CPU time 5.34 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:16 PM PDT 24
Peak memory 201164 kb
Host smart-b54e4e65-3de7-46f7-9d13-2648a18699a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915819566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.1915819566
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.3824146192
Short name T194
Test name
Test status
Simulation time 2812988648 ps
CPU time 1.06 seconds
Started Mar 14 01:29:10 PM PDT 24
Finished Mar 14 01:29:12 PM PDT 24
Peak memory 201172 kb
Host smart-28a72d81-3d21-45f2-8a55-036f96797b8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824146192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.3824146192
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2921602629
Short name T792
Test name
Test status
Simulation time 2612547650 ps
CPU time 6.91 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:17 PM PDT 24
Peak memory 201180 kb
Host smart-f57971ae-493d-40da-a0b9-51473a66a278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921602629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2921602629
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2492690267
Short name T416
Test name
Test status
Simulation time 2502139341 ps
CPU time 1.59 seconds
Started Mar 14 01:29:07 PM PDT 24
Finished Mar 14 01:29:10 PM PDT 24
Peak memory 201260 kb
Host smart-ba8e9ca4-a500-4a9d-a104-6aba69fa1af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492690267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.2492690267
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.1579868086
Short name T622
Test name
Test status
Simulation time 2037294823 ps
CPU time 6.29 seconds
Started Mar 14 01:29:07 PM PDT 24
Finished Mar 14 01:29:14 PM PDT 24
Peak memory 201104 kb
Host smart-4d61dfbf-57e1-487c-beb7-593d787ab673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579868086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1579868086
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.1081421496
Short name T486
Test name
Test status
Simulation time 2511261104 ps
CPU time 7.78 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:19 PM PDT 24
Peak memory 201276 kb
Host smart-cdc0d683-19f6-4b35-87e2-7135e343504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081421496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.1081421496
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.2940214899
Short name T108
Test name
Test status
Simulation time 2113938388 ps
CPU time 3.5 seconds
Started Mar 14 01:29:10 PM PDT 24
Finished Mar 14 01:29:14 PM PDT 24
Peak memory 201140 kb
Host smart-dad23e43-92f7-4215-b580-8cf81edc8d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940214899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.2940214899
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.178308312
Short name T515
Test name
Test status
Simulation time 17002533770 ps
CPU time 12.29 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:22 PM PDT 24
Peak memory 201260 kb
Host smart-b5da54f2-6f7b-4fb3-a53b-380ebe8197f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178308312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_st
ress_all.178308312
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1946702580
Short name T474
Test name
Test status
Simulation time 8905932815 ps
CPU time 2.95 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:13 PM PDT 24
Peak memory 201200 kb
Host smart-9380b85f-7cc1-493b-b675-e463eae47d27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946702580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.1946702580
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.1674412478
Short name T760
Test name
Test status
Simulation time 2017429953 ps
CPU time 3.23 seconds
Started Mar 14 01:29:14 PM PDT 24
Finished Mar 14 01:29:18 PM PDT 24
Peak memory 201280 kb
Host smart-3c0fa0d4-1f01-4d83-b2ec-3bf62615dcef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674412478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.1674412478
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2181480907
Short name T298
Test name
Test status
Simulation time 3437197508 ps
CPU time 9.27 seconds
Started Mar 14 01:29:10 PM PDT 24
Finished Mar 14 01:29:20 PM PDT 24
Peak memory 201252 kb
Host smart-a509ac93-9d17-4488-b805-342578f697b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181480907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2
181480907
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.2178029525
Short name T97
Test name
Test status
Simulation time 106680811657 ps
CPU time 139.86 seconds
Started Mar 14 01:29:13 PM PDT 24
Finished Mar 14 01:31:33 PM PDT 24
Peak memory 201412 kb
Host smart-8b987fea-4602-454b-b3e4-d501aaf59e1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178029525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.2178029525
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.996166879
Short name T171
Test name
Test status
Simulation time 32087035644 ps
CPU time 41.42 seconds
Started Mar 14 01:29:14 PM PDT 24
Finished Mar 14 01:29:55 PM PDT 24
Peak memory 201480 kb
Host smart-d866f33a-5435-4117-853f-d5601eb97797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996166879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_wi
th_pre_cond.996166879
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2282622584
Short name T634
Test name
Test status
Simulation time 2558844760 ps
CPU time 6.73 seconds
Started Mar 14 01:29:13 PM PDT 24
Finished Mar 14 01:29:20 PM PDT 24
Peak memory 201148 kb
Host smart-20d642a3-4a0a-44d2-ab32-2aaa7cf2d6d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282622584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.2282622584
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.157291723
Short name T155
Test name
Test status
Simulation time 5059187237 ps
CPU time 5.82 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:17 PM PDT 24
Peak memory 201192 kb
Host smart-af872103-e823-41cb-b5eb-bc791768b3cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157291723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctr
l_edge_detect.157291723
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1014042933
Short name T66
Test name
Test status
Simulation time 2615437982 ps
CPU time 4.01 seconds
Started Mar 14 01:29:10 PM PDT 24
Finished Mar 14 01:29:14 PM PDT 24
Peak memory 201172 kb
Host smart-c1e5386e-ceb1-44de-b508-465e07051d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014042933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.1014042933
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3291541054
Short name T505
Test name
Test status
Simulation time 2452410354 ps
CPU time 7.72 seconds
Started Mar 14 01:29:14 PM PDT 24
Finished Mar 14 01:29:22 PM PDT 24
Peak memory 201144 kb
Host smart-5cb76525-0c34-48a6-aefb-fb9678526c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291541054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3291541054
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1867791419
Short name T584
Test name
Test status
Simulation time 2115802537 ps
CPU time 1.59 seconds
Started Mar 14 01:29:13 PM PDT 24
Finished Mar 14 01:29:15 PM PDT 24
Peak memory 201108 kb
Host smart-ae38add5-1a5e-40e2-ab38-dab004d67153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867791419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1867791419
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.2863867703
Short name T290
Test name
Test status
Simulation time 2511215435 ps
CPU time 6.93 seconds
Started Mar 14 01:29:13 PM PDT 24
Finished Mar 14 01:29:21 PM PDT 24
Peak memory 201224 kb
Host smart-92282956-db45-4b6e-89d6-8b1b88fdc9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863867703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2863867703
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.3598078364
Short name T162
Test name
Test status
Simulation time 2127298123 ps
CPU time 2.01 seconds
Started Mar 14 01:29:08 PM PDT 24
Finished Mar 14 01:29:10 PM PDT 24
Peak memory 201112 kb
Host smart-6711ffe7-0857-466f-a17a-0f9eb53f5914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598078364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3598078364
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.268425224
Short name T661
Test name
Test status
Simulation time 7142600978 ps
CPU time 4.58 seconds
Started Mar 14 01:29:13 PM PDT 24
Finished Mar 14 01:29:17 PM PDT 24
Peak memory 201180 kb
Host smart-13543270-58fd-401a-8daa-113f2d9e3878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268425224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_st
ress_all.268425224
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1239688027
Short name T530
Test name
Test status
Simulation time 11727975615 ps
CPU time 1.15 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:12 PM PDT 24
Peak memory 201196 kb
Host smart-8ca73d75-f326-4033-a634-4f3d6799722a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239688027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.1239688027
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.2832987138
Short name T244
Test name
Test status
Simulation time 2012123652 ps
CPU time 5.69 seconds
Started Mar 14 01:29:13 PM PDT 24
Finished Mar 14 01:29:19 PM PDT 24
Peak memory 201236 kb
Host smart-fd860b12-ff12-4f41-a154-b63a0fa7c551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832987138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.2832987138
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3073402781
Short name T82
Test name
Test status
Simulation time 3821554442 ps
CPU time 2.97 seconds
Started Mar 14 01:29:11 PM PDT 24
Finished Mar 14 01:29:15 PM PDT 24
Peak memory 201264 kb
Host smart-1ce06a3c-722d-4a74-82e4-6220ef03fa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073402781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.3
073402781
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2308484423
Short name T372
Test name
Test status
Simulation time 55473210260 ps
CPU time 159.71 seconds
Started Mar 14 01:29:13 PM PDT 24
Finished Mar 14 01:31:53 PM PDT 24
Peak memory 201520 kb
Host smart-e470e393-d7a6-47b6-9b3f-02ef910cf6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308484423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.2308484423
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1936194443
Short name T508
Test name
Test status
Simulation time 2721826345 ps
CPU time 1.96 seconds
Started Mar 14 01:29:11 PM PDT 24
Finished Mar 14 01:29:13 PM PDT 24
Peak memory 201196 kb
Host smart-5069dc7a-7de1-4bff-a7db-940e8b2faa75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936194443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.1936194443
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3730051167
Short name T184
Test name
Test status
Simulation time 3363093566 ps
CPU time 4.69 seconds
Started Mar 14 01:29:12 PM PDT 24
Finished Mar 14 01:29:18 PM PDT 24
Peak memory 201176 kb
Host smart-e025c9f4-1248-40b7-9e21-fde4afd2600e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730051167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3730051167
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3427682212
Short name T717
Test name
Test status
Simulation time 2610944967 ps
CPU time 7.06 seconds
Started Mar 14 01:29:14 PM PDT 24
Finished Mar 14 01:29:21 PM PDT 24
Peak memory 200756 kb
Host smart-2f62880c-2264-42a6-a521-da3eac9f1c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427682212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3427682212
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.3497724246
Short name T62
Test name
Test status
Simulation time 2594641201 ps
CPU time 1.05 seconds
Started Mar 14 01:29:13 PM PDT 24
Finished Mar 14 01:29:15 PM PDT 24
Peak memory 201196 kb
Host smart-120e682e-74ec-4c85-a7fd-866d01ebd79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497724246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.3497724246
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.630446873
Short name T324
Test name
Test status
Simulation time 2112619552 ps
CPU time 4.83 seconds
Started Mar 14 01:29:11 PM PDT 24
Finished Mar 14 01:29:17 PM PDT 24
Peak memory 201160 kb
Host smart-b3703ae5-d096-446d-83fd-3a022ecbe77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630446873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.630446873
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.3351998772
Short name T427
Test name
Test status
Simulation time 2549348920 ps
CPU time 1.56 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:12 PM PDT 24
Peak memory 201252 kb
Host smart-b32551a8-2bc6-4421-af1d-57a9c099cef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351998772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.3351998772
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.2272881200
Short name T423
Test name
Test status
Simulation time 2123320407 ps
CPU time 1.81 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:12 PM PDT 24
Peak memory 201132 kb
Host smart-18a7685a-9247-4cbc-aa35-e88f8911798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272881200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.2272881200
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2352867092
Short name T196
Test name
Test status
Simulation time 3933329089 ps
CPU time 2.07 seconds
Started Mar 14 01:29:16 PM PDT 24
Finished Mar 14 01:29:19 PM PDT 24
Peak memory 201208 kb
Host smart-491808c9-b102-49e5-8de6-4b6619e0c5b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352867092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.2352867092
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.3169615209
Short name T13
Test name
Test status
Simulation time 2019259278 ps
CPU time 3.23 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:29:25 PM PDT 24
Peak memory 201216 kb
Host smart-ebca22e0-b8cf-4046-b298-c534f9705115
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169615209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.3169615209
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2134151036
Short name T418
Test name
Test status
Simulation time 3314831111 ps
CPU time 6.94 seconds
Started Mar 14 01:29:20 PM PDT 24
Finished Mar 14 01:29:27 PM PDT 24
Peak memory 201244 kb
Host smart-4d15b14a-92b0-4303-97de-858c018b61aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134151036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2
134151036
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.1056736284
Short name T300
Test name
Test status
Simulation time 108236383826 ps
CPU time 134.03 seconds
Started Mar 14 01:29:21 PM PDT 24
Finished Mar 14 01:31:36 PM PDT 24
Peak memory 201464 kb
Host smart-e70a790e-6e10-4848-a489-f9f271c976e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056736284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.1056736284
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.1159073213
Short name T507
Test name
Test status
Simulation time 3012725942 ps
CPU time 1.8 seconds
Started Mar 14 01:29:07 PM PDT 24
Finished Mar 14 01:29:10 PM PDT 24
Peak memory 201180 kb
Host smart-048ac91c-6550-4769-b7d6-32cad8a53f90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159073213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.1159073213
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.564866994
Short name T176
Test name
Test status
Simulation time 4407273554 ps
CPU time 3.55 seconds
Started Mar 14 01:29:19 PM PDT 24
Finished Mar 14 01:29:23 PM PDT 24
Peak memory 201204 kb
Host smart-672fc342-78c8-43ec-aa0f-03e889b148d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564866994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctr
l_edge_detect.564866994
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1591562182
Short name T113
Test name
Test status
Simulation time 2612039025 ps
CPU time 6.93 seconds
Started Mar 14 01:29:16 PM PDT 24
Finished Mar 14 01:29:23 PM PDT 24
Peak memory 201192 kb
Host smart-229a8480-56d5-4661-a44c-7e6153272bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591562182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1591562182
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.688465428
Short name T294
Test name
Test status
Simulation time 2455000189 ps
CPU time 7.23 seconds
Started Mar 14 01:29:13 PM PDT 24
Finished Mar 14 01:29:20 PM PDT 24
Peak memory 201160 kb
Host smart-6b324a4d-2b7f-4267-b76d-5fdd533f2052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688465428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.688465428
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.3222399670
Short name T536
Test name
Test status
Simulation time 2128336611 ps
CPU time 1.91 seconds
Started Mar 14 01:29:14 PM PDT 24
Finished Mar 14 01:29:16 PM PDT 24
Peak memory 201108 kb
Host smart-b60f960e-2e16-4c24-8f82-3fc2a282c271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222399670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.3222399670
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.128605201
Short name T583
Test name
Test status
Simulation time 2516713521 ps
CPU time 3.82 seconds
Started Mar 14 01:29:09 PM PDT 24
Finished Mar 14 01:29:15 PM PDT 24
Peak memory 201304 kb
Host smart-1a01a4fd-e310-4762-a031-6f3092d78337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128605201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.128605201
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.422410138
Short name T245
Test name
Test status
Simulation time 2135681330 ps
CPU time 2.12 seconds
Started Mar 14 01:29:16 PM PDT 24
Finished Mar 14 01:29:18 PM PDT 24
Peak memory 201124 kb
Host smart-c72682b4-a90a-4604-b074-9857f42d12e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422410138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.422410138
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.2070443637
Short name T516
Test name
Test status
Simulation time 6566794350 ps
CPU time 17.25 seconds
Started Mar 14 01:29:21 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 201188 kb
Host smart-310b4648-f4d1-457d-912d-bec147682838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070443637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.2070443637
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.839103015
Short name T115
Test name
Test status
Simulation time 69236920333 ps
CPU time 38.79 seconds
Started Mar 14 01:29:20 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 209732 kb
Host smart-e07933cb-774d-40f1-b253-85f0fff8fea3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839103015 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.839103015
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.720975079
Short name T86
Test name
Test status
Simulation time 6004304251 ps
CPU time 2.36 seconds
Started Mar 14 01:29:19 PM PDT 24
Finished Mar 14 01:29:21 PM PDT 24
Peak memory 201228 kb
Host smart-8328cb55-0570-4a28-a805-279e1e4d414e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720975079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_ultra_low_pwr.720975079
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.1815826531
Short name T783
Test name
Test status
Simulation time 2014989181 ps
CPU time 5.79 seconds
Started Mar 14 01:29:23 PM PDT 24
Finished Mar 14 01:29:29 PM PDT 24
Peak memory 201260 kb
Host smart-275589f3-d35f-49d2-ac97-59750b5469c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815826531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.1815826531
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.537708694
Short name T519
Test name
Test status
Simulation time 170221220216 ps
CPU time 112.78 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:31:15 PM PDT 24
Peak memory 201256 kb
Host smart-78596e0e-7c0e-4a88-8954-7e1544e6cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537708694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.537708694
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3203411155
Short name T465
Test name
Test status
Simulation time 3104018410 ps
CPU time 8.55 seconds
Started Mar 14 01:29:21 PM PDT 24
Finished Mar 14 01:29:30 PM PDT 24
Peak memory 201136 kb
Host smart-ba2b4e36-f45b-4228-8fc2-3dc528b33670
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203411155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.3203411155
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.4185724279
Short name T712
Test name
Test status
Simulation time 4199468146 ps
CPU time 1.41 seconds
Started Mar 14 01:29:20 PM PDT 24
Finished Mar 14 01:29:22 PM PDT 24
Peak memory 201264 kb
Host smart-7c6e016c-df9e-49cf-ad84-2e4c2c8807e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185724279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.4185724279
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2410744684
Short name T624
Test name
Test status
Simulation time 2622295734 ps
CPU time 3.82 seconds
Started Mar 14 01:29:20 PM PDT 24
Finished Mar 14 01:29:24 PM PDT 24
Peak memory 201208 kb
Host smart-9980f175-f7f2-4a62-a05f-9d432ddd42b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410744684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2410744684
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.485403809
Short name T533
Test name
Test status
Simulation time 2448851383 ps
CPU time 6.9 seconds
Started Mar 14 01:29:20 PM PDT 24
Finished Mar 14 01:29:27 PM PDT 24
Peak memory 201184 kb
Host smart-3c082d8d-981c-4e18-8338-60eaf9a1eefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485403809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.485403809
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.3766104179
Short name T775
Test name
Test status
Simulation time 2147676838 ps
CPU time 1.72 seconds
Started Mar 14 01:29:20 PM PDT 24
Finished Mar 14 01:29:22 PM PDT 24
Peak memory 201152 kb
Host smart-45532e53-2ea4-42ee-a5c8-17a8aff5fa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766104179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.3766104179
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2839182580
Short name T198
Test name
Test status
Simulation time 2513058891 ps
CPU time 7.48 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:29:29 PM PDT 24
Peak memory 201268 kb
Host smart-d1c1c51b-7542-4f9e-a502-f08905e928ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839182580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2839182580
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.2054820569
Short name T448
Test name
Test status
Simulation time 2133040773 ps
CPU time 1.99 seconds
Started Mar 14 01:29:21 PM PDT 24
Finished Mar 14 01:29:23 PM PDT 24
Peak memory 201136 kb
Host smart-f3a9bf7a-d2e8-4cc1-9fe6-300380cbffe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054820569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2054820569
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.1578987319
Short name T151
Test name
Test status
Simulation time 71013393170 ps
CPU time 17.6 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:29:40 PM PDT 24
Peak memory 201388 kb
Host smart-0fcd3c64-3090-426e-8e85-7d44bddaf2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578987319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.1578987319
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3789698537
Short name T56
Test name
Test status
Simulation time 3727144414 ps
CPU time 7.08 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:29:29 PM PDT 24
Peak memory 201196 kb
Host smart-a3995c4e-4f8a-4eaa-8cfb-58df791307cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789698537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.3789698537
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.950323121
Short name T216
Test name
Test status
Simulation time 2015384228 ps
CPU time 6.05 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:29:28 PM PDT 24
Peak memory 201268 kb
Host smart-8c2fa1a2-2ba3-4199-bb22-01bd1c2edaa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950323121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_tes
t.950323121
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.968511712
Short name T225
Test name
Test status
Simulation time 3513219634 ps
CPU time 5.43 seconds
Started Mar 14 01:29:21 PM PDT 24
Finished Mar 14 01:29:27 PM PDT 24
Peak memory 201272 kb
Host smart-842afae6-ffa3-4883-a972-d88c44053367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968511712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.968511712
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.870564916
Short name T90
Test name
Test status
Simulation time 129209255446 ps
CPU time 85.49 seconds
Started Mar 14 01:29:20 PM PDT 24
Finished Mar 14 01:30:46 PM PDT 24
Peak memory 201360 kb
Host smart-a1f77b8b-aad0-49a1-b082-b8304a570616
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870564916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.870564916
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3467777166
Short name T71
Test name
Test status
Simulation time 26595388205 ps
CPU time 18.76 seconds
Started Mar 14 01:29:21 PM PDT 24
Finished Mar 14 01:29:40 PM PDT 24
Peak memory 201536 kb
Host smart-275ff414-48b9-4b05-968a-d5b3f90eccef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467777166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.3467777166
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3774246852
Short name T575
Test name
Test status
Simulation time 4743414690 ps
CPU time 12.8 seconds
Started Mar 14 01:29:23 PM PDT 24
Finished Mar 14 01:29:36 PM PDT 24
Peak memory 201224 kb
Host smart-72d1a544-2cf4-49d6-a069-b01c103f75f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774246852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.3774246852
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1596523608
Short name T559
Test name
Test status
Simulation time 2787299430 ps
CPU time 8.2 seconds
Started Mar 14 01:29:23 PM PDT 24
Finished Mar 14 01:29:32 PM PDT 24
Peak memory 201232 kb
Host smart-5289afd7-b130-4f00-9476-0955136b7bd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596523608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.1596523608
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1780181438
Short name T417
Test name
Test status
Simulation time 2610793316 ps
CPU time 7.25 seconds
Started Mar 14 01:29:25 PM PDT 24
Finished Mar 14 01:29:32 PM PDT 24
Peak memory 201208 kb
Host smart-51b5359d-a263-4680-a456-2054a6381a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780181438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1780181438
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3052947970
Short name T574
Test name
Test status
Simulation time 2495202488 ps
CPU time 1.72 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:29:24 PM PDT 24
Peak memory 201196 kb
Host smart-93ce2ffd-bb03-4ac1-8685-2f04e299542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052947970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3052947970
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2684457391
Short name T215
Test name
Test status
Simulation time 2175164895 ps
CPU time 1.49 seconds
Started Mar 14 01:29:20 PM PDT 24
Finished Mar 14 01:29:21 PM PDT 24
Peak memory 201192 kb
Host smart-99c07bdd-a0b7-4923-8444-6b2cc00b1924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684457391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2684457391
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.556874680
Short name T164
Test name
Test status
Simulation time 2139261673 ps
CPU time 1.94 seconds
Started Mar 14 01:29:20 PM PDT 24
Finished Mar 14 01:29:22 PM PDT 24
Peak memory 201072 kb
Host smart-16491b43-a28b-4952-b3a5-2725be886855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556874680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.556874680
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.2106473858
Short name T291
Test name
Test status
Simulation time 172432657415 ps
CPU time 113.11 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:31:16 PM PDT 24
Peak memory 201436 kb
Host smart-574cb21e-ea91-4879-bdd1-e3bb8f797699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106473858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.2106473858
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.797508458
Short name T725
Test name
Test status
Simulation time 12102851269 ps
CPU time 15.49 seconds
Started Mar 14 01:29:23 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 201632 kb
Host smart-28aa48e5-88a0-4582-ae80-d9213edb2690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797508458 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.797508458
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2502131467
Short name T617
Test name
Test status
Simulation time 8906994576 ps
CPU time 2.64 seconds
Started Mar 14 01:29:22 PM PDT 24
Finished Mar 14 01:29:25 PM PDT 24
Peak memory 201216 kb
Host smart-a60e62d1-c92f-4565-b25f-117cc8205d34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502131467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.2502131467
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.1368282058
Short name T778
Test name
Test status
Simulation time 2009561048 ps
CPU time 6.43 seconds
Started Mar 14 01:29:42 PM PDT 24
Finished Mar 14 01:29:49 PM PDT 24
Peak memory 201232 kb
Host smart-dc51c08f-1e61-4cdf-987a-bb73e10aec2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368282058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.1368282058
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2208585884
Short name T444
Test name
Test status
Simulation time 3307985018 ps
CPU time 2.68 seconds
Started Mar 14 01:29:28 PM PDT 24
Finished Mar 14 01:29:31 PM PDT 24
Peak memory 201228 kb
Host smart-cd7922ff-42bc-4dda-9288-680d9d6a07f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208585884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2
208585884
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3975161440
Short name T683
Test name
Test status
Simulation time 39983826735 ps
CPU time 24.45 seconds
Started Mar 14 01:29:27 PM PDT 24
Finished Mar 14 01:29:52 PM PDT 24
Peak memory 201352 kb
Host smart-662af025-7edf-4191-a15a-99b40ad8919d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975161440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.3975161440
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.649149428
Short name T73
Test name
Test status
Simulation time 23805067755 ps
CPU time 10.11 seconds
Started Mar 14 01:29:28 PM PDT 24
Finished Mar 14 01:29:38 PM PDT 24
Peak memory 201496 kb
Host smart-9d74cc33-c359-4805-98a2-877a2cc9a99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649149428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi
th_pre_cond.649149428
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1123956701
Short name T657
Test name
Test status
Simulation time 3837972879 ps
CPU time 9.87 seconds
Started Mar 14 01:29:28 PM PDT 24
Finished Mar 14 01:29:38 PM PDT 24
Peak memory 201152 kb
Host smart-aadb8a09-1f98-417a-8c52-4ae4c148fbc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123956701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.1123956701
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.2583339192
Short name T175
Test name
Test status
Simulation time 2567588106 ps
CPU time 7.04 seconds
Started Mar 14 01:29:26 PM PDT 24
Finished Mar 14 01:29:34 PM PDT 24
Peak memory 201172 kb
Host smart-2513846b-d156-4ea0-a993-3b6ed1a543d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583339192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.2583339192
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3577803244
Short name T414
Test name
Test status
Simulation time 2626512914 ps
CPU time 2.32 seconds
Started Mar 14 01:29:24 PM PDT 24
Finished Mar 14 01:29:27 PM PDT 24
Peak memory 201192 kb
Host smart-8bda597a-9ce7-481b-b911-b6022d7b45e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577803244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3577803244
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2537593283
Short name T686
Test name
Test status
Simulation time 2472844886 ps
CPU time 2.29 seconds
Started Mar 14 01:29:24 PM PDT 24
Finished Mar 14 01:29:26 PM PDT 24
Peak memory 201216 kb
Host smart-c4de4546-bd34-4d05-a253-46c5d2def169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537593283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2537593283
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2075901662
Short name T51
Test name
Test status
Simulation time 2074171770 ps
CPU time 6.12 seconds
Started Mar 14 01:29:24 PM PDT 24
Finished Mar 14 01:29:30 PM PDT 24
Peak memory 201116 kb
Host smart-39d055b2-4f17-40a1-af42-ac4680790c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075901662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.2075901662
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.291142994
Short name T438
Test name
Test status
Simulation time 2588865904 ps
CPU time 1.4 seconds
Started Mar 14 01:29:23 PM PDT 24
Finished Mar 14 01:29:25 PM PDT 24
Peak memory 201256 kb
Host smart-6764150d-f86e-44a4-8ed0-550d07d3af24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291142994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.291142994
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.4285564506
Short name T654
Test name
Test status
Simulation time 2112413435 ps
CPU time 4.05 seconds
Started Mar 14 01:29:23 PM PDT 24
Finished Mar 14 01:29:27 PM PDT 24
Peak memory 201112 kb
Host smart-a818bbd2-49fd-4268-bc9e-905071b6b893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285564506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.4285564506
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.1666157805
Short name T735
Test name
Test status
Simulation time 7658768308 ps
CPU time 10.26 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:49 PM PDT 24
Peak memory 201256 kb
Host smart-6ddcbcda-0b0f-4013-aa81-46bc2fd486db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666157805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.1666157805
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1985896148
Short name T464
Test name
Test status
Simulation time 18441584266 ps
CPU time 33.93 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:30:13 PM PDT 24
Peak memory 209892 kb
Host smart-9f77a2ad-7703-4705-b3ef-429453a3e892
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985896148 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.1985896148
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1072502825
Short name T769
Test name
Test status
Simulation time 2624543963 ps
CPU time 2.14 seconds
Started Mar 14 01:29:27 PM PDT 24
Finished Mar 14 01:29:29 PM PDT 24
Peak memory 201184 kb
Host smart-c6eb0a97-7d64-4d3b-9718-85931fa9d955
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072502825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.1072502825
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3938968430
Short name T480
Test name
Test status
Simulation time 2014204928 ps
CPU time 6.05 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:29:43 PM PDT 24
Peak memory 201244 kb
Host smart-3874dfa1-c29a-485b-bdf4-fd2b00b7fbb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938968430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3938968430
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2168296113
Short name T620
Test name
Test status
Simulation time 3331744210 ps
CPU time 2.82 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:41 PM PDT 24
Peak memory 201244 kb
Host smart-467de5af-e1ae-4559-a27c-d6d9e88a19f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168296113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.2
168296113
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.654251093
Short name T363
Test name
Test status
Simulation time 167733219978 ps
CPU time 112.14 seconds
Started Mar 14 01:29:40 PM PDT 24
Finished Mar 14 01:31:33 PM PDT 24
Peak memory 200984 kb
Host smart-9842818c-de1e-4b5b-ad94-3f719f8cab11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654251093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_combo_detect.654251093
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3821078597
Short name T18
Test name
Test status
Simulation time 23867789304 ps
CPU time 12.52 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:50 PM PDT 24
Peak memory 201436 kb
Host smart-60813194-1554-4fe6-97bc-4189d3a2879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821078597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.3821078597
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1282802644
Short name T460
Test name
Test status
Simulation time 3177993942 ps
CPU time 1.22 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 201180 kb
Host smart-2141fbf0-e91d-4ce0-986d-569798ce02fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282802644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.1282802644
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3318445531
Short name T680
Test name
Test status
Simulation time 5678049778 ps
CPU time 6.85 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:29:44 PM PDT 24
Peak memory 201212 kb
Host smart-dd264e57-ee15-45bc-a82f-fd501c59b258
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318445531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.3318445531
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.377004590
Short name T209
Test name
Test status
Simulation time 2613549353 ps
CPU time 7.69 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:45 PM PDT 24
Peak memory 201208 kb
Host smart-3bbbadcd-eb9b-44aa-9118-c730415f307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377004590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.377004590
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.4031485617
Short name T572
Test name
Test status
Simulation time 2453966705 ps
CPU time 6.96 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:45 PM PDT 24
Peak memory 201188 kb
Host smart-64c4e5b1-cfdc-46a5-8693-a92bd657fd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031485617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.4031485617
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.2718308715
Short name T593
Test name
Test status
Simulation time 2245031006 ps
CPU time 3.64 seconds
Started Mar 14 01:29:35 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 201152 kb
Host smart-0fbc8911-3f95-482d-926c-85fabeed4f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718308715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.2718308715
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.708887661
Short name T705
Test name
Test status
Simulation time 2523584504 ps
CPU time 2.56 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 201316 kb
Host smart-08296810-510f-476a-a593-decd196a2a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708887661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.708887661
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.2554787216
Short name T643
Test name
Test status
Simulation time 2111686667 ps
CPU time 6.27 seconds
Started Mar 14 01:29:36 PM PDT 24
Finished Mar 14 01:29:43 PM PDT 24
Peak memory 201132 kb
Host smart-5351db77-19b4-47c8-a5a7-985785637c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554787216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2554787216
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.3164046015
Short name T26
Test name
Test status
Simulation time 18100032362 ps
CPU time 31.66 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:30:11 PM PDT 24
Peak memory 201176 kb
Host smart-e004066d-75aa-411a-a0cc-4baa6c3b9143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164046015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.3164046015
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2581781940
Short name T76
Test name
Test status
Simulation time 5601341996 ps
CPU time 7.44 seconds
Started Mar 14 01:29:36 PM PDT 24
Finished Mar 14 01:29:44 PM PDT 24
Peak memory 201252 kb
Host smart-3c30bf28-5779-41c7-a4bf-ac3d43a585a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581781940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.2581781940
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3629184614
Short name T319
Test name
Test status
Simulation time 2032355375 ps
CPU time 2 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:41 PM PDT 24
Peak memory 201260 kb
Host smart-895eca37-0587-4297-8d29-ccc7f0922471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629184614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3629184614
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.133984100
Short name T618
Test name
Test status
Simulation time 3877177918 ps
CPU time 2.74 seconds
Started Mar 14 01:29:40 PM PDT 24
Finished Mar 14 01:29:43 PM PDT 24
Peak memory 201272 kb
Host smart-bb480620-6de5-44bb-b375-78b42c769cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133984100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.133984100
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.3210386835
Short name T265
Test name
Test status
Simulation time 164187112015 ps
CPU time 110.73 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:31:29 PM PDT 24
Peak memory 201464 kb
Host smart-dc0edc8f-1173-457b-b139-328cb4b1a661
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210386835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.3210386835
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2520655862
Short name T249
Test name
Test status
Simulation time 78666457763 ps
CPU time 110.67 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:31:29 PM PDT 24
Peak memory 201544 kb
Host smart-4a15a0f7-954e-4fa9-bbf8-80a8457c3e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520655862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.2520655862
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3349070539
Short name T566
Test name
Test status
Simulation time 2939522928 ps
CPU time 7.79 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:47 PM PDT 24
Peak memory 201184 kb
Host smart-86f14188-62ba-4c56-bb49-a66475095eb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349070539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.3349070539
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.2534408896
Short name T156
Test name
Test status
Simulation time 4195153597 ps
CPU time 3 seconds
Started Mar 14 01:29:36 PM PDT 24
Finished Mar 14 01:29:40 PM PDT 24
Peak memory 201196 kb
Host smart-afaed48f-a9f6-4ae6-996b-2b2645c3ec46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534408896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.2534408896
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2835426052
Short name T439
Test name
Test status
Simulation time 2614074478 ps
CPU time 7.19 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:46 PM PDT 24
Peak memory 201200 kb
Host smart-07af7141-4eee-41d3-974a-c9ce64b15b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835426052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.2835426052
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.3001539320
Short name T517
Test name
Test status
Simulation time 2440843901 ps
CPU time 6.38 seconds
Started Mar 14 01:29:40 PM PDT 24
Finished Mar 14 01:29:46 PM PDT 24
Peak memory 201152 kb
Host smart-1afe25f5-a8b3-4c1f-abfe-d509eaddec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001539320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3001539320
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2316649172
Short name T292
Test name
Test status
Simulation time 2206686756 ps
CPU time 6.53 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:45 PM PDT 24
Peak memory 201192 kb
Host smart-a41060c2-b902-4f8a-8f1d-be6a7a3578fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316649172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2316649172
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.251246729
Short name T663
Test name
Test status
Simulation time 2514140913 ps
CPU time 7.4 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:45 PM PDT 24
Peak memory 201256 kb
Host smart-c21e4e19-b6c0-421b-8a4e-03909976444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251246729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.251246729
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.658745992
Short name T150
Test name
Test status
Simulation time 2113903809 ps
CPU time 3.63 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:42 PM PDT 24
Peak memory 201108 kb
Host smart-e2531f7b-9d23-4155-bddd-d26111bf2e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658745992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.658745992
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.2591438585
Short name T476
Test name
Test status
Simulation time 7764923382 ps
CPU time 13.52 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:51 PM PDT 24
Peak memory 201232 kb
Host smart-07addbfd-0e76-4e23-9e22-d3b774546029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591438585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.2591438585
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3965498848
Short name T598
Test name
Test status
Simulation time 24342867101 ps
CPU time 29.37 seconds
Started Mar 14 01:29:41 PM PDT 24
Finished Mar 14 01:30:10 PM PDT 24
Peak memory 217936 kb
Host smart-a77ee43f-5e93-4bf3-8968-a16e93a5d1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965498848 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.3965498848
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2674314914
Short name T58
Test name
Test status
Simulation time 6483217087 ps
CPU time 2.6 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 201224 kb
Host smart-aab97f19-0199-4de2-8e02-f0c880b6023a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674314914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.2674314914
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.3045835023
Short name T15
Test name
Test status
Simulation time 2027978048 ps
CPU time 2.05 seconds
Started Mar 14 01:28:05 PM PDT 24
Finished Mar 14 01:28:07 PM PDT 24
Peak memory 201296 kb
Host smart-d4539c5d-d112-4408-b197-96670207a146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045835023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.3045835023
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2238277126
Short name T406
Test name
Test status
Simulation time 3973034617 ps
CPU time 2.93 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 201228 kb
Host smart-bfb81667-0ae4-41b5-9328-ececdf06e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238277126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2238277126
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.2414279557
Short name T679
Test name
Test status
Simulation time 57684203246 ps
CPU time 39.69 seconds
Started Mar 14 01:28:05 PM PDT 24
Finished Mar 14 01:28:45 PM PDT 24
Peak memory 201460 kb
Host smart-88ab60a9-ccfc-4f19-affa-9003859e169a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414279557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.2414279557
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2701412992
Short name T648
Test name
Test status
Simulation time 2224200679 ps
CPU time 6.35 seconds
Started Mar 14 01:28:01 PM PDT 24
Finished Mar 14 01:28:08 PM PDT 24
Peak memory 201128 kb
Host smart-b996f15c-48c0-43d6-bbb2-d81059799fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701412992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2701412992
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3918702978
Short name T641
Test name
Test status
Simulation time 2299903257 ps
CPU time 3.51 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:28:07 PM PDT 24
Peak memory 201236 kb
Host smart-3536df66-65fd-4dcf-95b4-5bc8e69db08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918702978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3918702978
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.112713352
Short name T409
Test name
Test status
Simulation time 2728396794 ps
CPU time 8.21 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:14 PM PDT 24
Peak memory 201180 kb
Host smart-4aef17b2-413a-46c0-8bab-da516e5a533c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112713352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ec_pwr_on_rst.112713352
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2082494504
Short name T38
Test name
Test status
Simulation time 275700343925 ps
CPU time 188.17 seconds
Started Mar 14 01:27:55 PM PDT 24
Finished Mar 14 01:31:04 PM PDT 24
Peak memory 201204 kb
Host smart-12434cf8-820a-4235-9e04-b2bf499b330a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082494504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.2082494504
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2745747262
Short name T315
Test name
Test status
Simulation time 2637572214 ps
CPU time 2.43 seconds
Started Mar 14 01:28:02 PM PDT 24
Finished Mar 14 01:28:04 PM PDT 24
Peak memory 201204 kb
Host smart-dddbbdc7-0e5b-4966-90d7-a0ec27ebdb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745747262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2745747262
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.1062188477
Short name T430
Test name
Test status
Simulation time 2491407008 ps
CPU time 2.21 seconds
Started Mar 14 01:28:05 PM PDT 24
Finished Mar 14 01:28:07 PM PDT 24
Peak memory 201140 kb
Host smart-c8e40ed1-7f50-4fa3-b4bb-4d74aa6197df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062188477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.1062188477
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3383387957
Short name T129
Test name
Test status
Simulation time 2169980928 ps
CPU time 3.44 seconds
Started Mar 14 01:28:08 PM PDT 24
Finished Mar 14 01:28:12 PM PDT 24
Peak memory 201188 kb
Host smart-bb37cd23-2e83-4ece-a5a5-95d7077f1551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383387957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3383387957
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1369093133
Short name T504
Test name
Test status
Simulation time 2519853048 ps
CPU time 3.94 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:10 PM PDT 24
Peak memory 201268 kb
Host smart-0537a8f3-0195-4d4d-b818-61661cdeeb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369093133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1369093133
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.3341651131
Short name T268
Test name
Test status
Simulation time 22070410294 ps
CPU time 53.04 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:29:01 PM PDT 24
Peak memory 220812 kb
Host smart-143c91b5-a29a-4e87-aed5-55f1938b53bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341651131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3341651131
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.3133316048
Short name T548
Test name
Test status
Simulation time 2112903029 ps
CPU time 6.25 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:28:13 PM PDT 24
Peak memory 201104 kb
Host smart-b65332ba-547f-4740-80c9-acea616ad2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133316048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.3133316048
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.1809178560
Short name T65
Test name
Test status
Simulation time 9586592767 ps
CPU time 13.38 seconds
Started Mar 14 01:28:03 PM PDT 24
Finished Mar 14 01:28:17 PM PDT 24
Peak memory 201256 kb
Host smart-d2e531eb-5e3c-41ac-8528-fa360bd01d9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809178560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.1809178560
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2087625926
Short name T263
Test name
Test status
Simulation time 422186393045 ps
CPU time 160.57 seconds
Started Mar 14 01:28:10 PM PDT 24
Finished Mar 14 01:30:51 PM PDT 24
Peak memory 218064 kb
Host smart-811edd2b-4c38-4a28-be89-ddbc76e09e30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087625926 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.2087625926
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2043223556
Short name T335
Test name
Test status
Simulation time 9402722317 ps
CPU time 2.31 seconds
Started Mar 14 01:28:09 PM PDT 24
Finished Mar 14 01:28:11 PM PDT 24
Peak memory 201188 kb
Host smart-b13d3912-42f2-4a27-aa60-fb33745ec48c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043223556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.2043223556
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.280971798
Short name T489
Test name
Test status
Simulation time 2035656784 ps
CPU time 2.01 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:42 PM PDT 24
Peak memory 201244 kb
Host smart-f915bc29-bbf1-4f88-9196-b4146f2e816d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280971798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.280971798
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2600638627
Short name T195
Test name
Test status
Simulation time 3461610521 ps
CPU time 2.43 seconds
Started Mar 14 01:29:40 PM PDT 24
Finished Mar 14 01:29:42 PM PDT 24
Peak memory 201272 kb
Host smart-93691bcd-74ec-41b2-a46f-30261b042a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600638627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.2
600638627
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.626065377
Short name T260
Test name
Test status
Simulation time 78097647365 ps
CPU time 44.94 seconds
Started Mar 14 01:29:41 PM PDT 24
Finished Mar 14 01:30:26 PM PDT 24
Peak memory 201428 kb
Host smart-f56ead5d-dfad-4319-a5d3-2b6c7ff072b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626065377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_combo_detect.626065377
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.994251694
Short name T243
Test name
Test status
Simulation time 99175278344 ps
CPU time 274.6 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:34:12 PM PDT 24
Peak memory 201400 kb
Host smart-d1c65152-33fc-461c-b8af-f5f9109f218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994251694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_wi
th_pre_cond.994251694
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1072793316
Short name T638
Test name
Test status
Simulation time 3177689237 ps
CPU time 7.6 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:46 PM PDT 24
Peak memory 201180 kb
Host smart-b1f44cf6-0e10-41f8-aaf5-0a8c4d6ecc02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072793316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.1072793316
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.519387030
Short name T138
Test name
Test status
Simulation time 5831162819 ps
CPU time 1.39 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:29:38 PM PDT 24
Peak memory 201176 kb
Host smart-0df642c8-e476-41b0-8c53-e46e9db28ecb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519387030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctr
l_edge_detect.519387030
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2824893067
Short name T68
Test name
Test status
Simulation time 2608668078 ps
CPU time 6.98 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:29:44 PM PDT 24
Peak memory 201188 kb
Host smart-858ed9c2-4cf1-453a-900b-392c99e29f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824893067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.2824893067
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.300856286
Short name T482
Test name
Test status
Simulation time 2467751553 ps
CPU time 7.79 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:46 PM PDT 24
Peak memory 201224 kb
Host smart-17e82e39-5cf5-4653-bd84-ba5a89d805b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300856286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.300856286
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.102096998
Short name T552
Test name
Test status
Simulation time 2083665135 ps
CPU time 5.79 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:44 PM PDT 24
Peak memory 201128 kb
Host smart-f83e5efa-c5a2-4353-ad61-333e8c759bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102096998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.102096998
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1468015589
Short name T699
Test name
Test status
Simulation time 2535491842 ps
CPU time 1.94 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 201272 kb
Host smart-8b4ff56f-9434-4acf-8e83-0320735cd49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468015589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.1468015589
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.4196338069
Short name T726
Test name
Test status
Simulation time 2129714068 ps
CPU time 2.01 seconds
Started Mar 14 01:29:43 PM PDT 24
Finished Mar 14 01:29:45 PM PDT 24
Peak memory 201092 kb
Host smart-ca9eda54-c0d2-4b97-b925-d2405e46ce91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196338069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.4196338069
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.613663161
Short name T78
Test name
Test status
Simulation time 88342224527 ps
CPU time 56.25 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:30:35 PM PDT 24
Peak memory 201376 kb
Host smart-1c97963e-64d7-44f1-b9d3-e16b7a0094f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613663161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_st
ress_all.613663161
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1162402315
Short name T204
Test name
Test status
Simulation time 155809065327 ps
CPU time 106.94 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:31:24 PM PDT 24
Peak memory 209776 kb
Host smart-29b20ab6-30e8-4074-b19c-e20950e00744
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162402315 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1162402315
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.429603097
Short name T607
Test name
Test status
Simulation time 11016832814 ps
CPU time 1.97 seconds
Started Mar 14 01:29:43 PM PDT 24
Finished Mar 14 01:29:45 PM PDT 24
Peak memory 201168 kb
Host smart-7a2593eb-df1c-4dd6-b33f-653faea5dfc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429603097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ultra_low_pwr.429603097
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.3190911389
Short name T722
Test name
Test status
Simulation time 2023795499 ps
CPU time 3.12 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:41 PM PDT 24
Peak memory 201236 kb
Host smart-ceb18e19-afea-4624-98d9-6d4e273b638a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190911389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.3190911389
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.223988017
Short name T236
Test name
Test status
Simulation time 3610283837 ps
CPU time 2.28 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:41 PM PDT 24
Peak memory 201232 kb
Host smart-76f7d1e2-2b90-4288-9313-70a82f6c3f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223988017 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.223988017
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.651471727
Short name T251
Test name
Test status
Simulation time 121646925394 ps
CPU time 21.05 seconds
Started Mar 14 01:29:36 PM PDT 24
Finished Mar 14 01:29:57 PM PDT 24
Peak memory 201416 kb
Host smart-9a966552-506c-428b-901d-c1d626edb8d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651471727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_combo_detect.651471727
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.4111350605
Short name T715
Test name
Test status
Simulation time 56849547621 ps
CPU time 151.35 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:32:11 PM PDT 24
Peak memory 201444 kb
Host smart-3a61ce3d-1104-4bfb-a36e-33fe70d1457d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111350605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.4111350605
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4183350672
Short name T770
Test name
Test status
Simulation time 4367427853 ps
CPU time 12.53 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:52 PM PDT 24
Peak memory 201180 kb
Host smart-e4010b10-85b3-4d52-b9b3-9a34291326de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183350672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ec_pwr_on_rst.4183350672
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.4022663948
Short name T135
Test name
Test status
Simulation time 4805617081 ps
CPU time 13.59 seconds
Started Mar 14 01:29:43 PM PDT 24
Finished Mar 14 01:29:57 PM PDT 24
Peak memory 201172 kb
Host smart-e172cda1-a185-4352-b9de-045119f19b71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022663948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.4022663948
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2263402325
Short name T506
Test name
Test status
Simulation time 2633785471 ps
CPU time 2.44 seconds
Started Mar 14 01:29:40 PM PDT 24
Finished Mar 14 01:29:43 PM PDT 24
Peak memory 201200 kb
Host smart-e4ecfa4a-579c-43f2-93cf-446860331a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263402325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2263402325
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.638953890
Short name T541
Test name
Test status
Simulation time 2461133947 ps
CPU time 3.78 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:42 PM PDT 24
Peak memory 201192 kb
Host smart-8109d4f9-4c30-423c-b80f-4b0923c053ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638953890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.638953890
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.3680916064
Short name T591
Test name
Test status
Simulation time 2022984376 ps
CPU time 3.35 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:43 PM PDT 24
Peak memory 201120 kb
Host smart-f93f1dd1-62ec-45d0-a637-eeaf22d2a27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680916064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.3680916064
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2170707272
Short name T461
Test name
Test status
Simulation time 2527180812 ps
CPU time 2.69 seconds
Started Mar 14 01:29:40 PM PDT 24
Finished Mar 14 01:29:43 PM PDT 24
Peak memory 200744 kb
Host smart-70718a71-9d02-406a-97c7-78a5d5a6ba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170707272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.2170707272
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1923318884
Short name T288
Test name
Test status
Simulation time 2107778637 ps
CPU time 5.91 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:29:43 PM PDT 24
Peak memory 201140 kb
Host smart-18c41ca1-0c42-4b5d-886f-66e56e98647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923318884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1923318884
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.2682196902
Short name T702
Test name
Test status
Simulation time 13620350557 ps
CPU time 37.07 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:30:14 PM PDT 24
Peak memory 201264 kb
Host smart-e62f445b-668f-43df-9593-a60d43d6912f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682196902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.2682196902
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.76082452
Short name T239
Test name
Test status
Simulation time 71522167858 ps
CPU time 22.33 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:30:00 PM PDT 24
Peak memory 209872 kb
Host smart-ada31c50-1b01-4288-b988-3d7c8ba948b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76082452 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.76082452
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1950364288
Short name T597
Test name
Test status
Simulation time 3631819624 ps
CPU time 3.17 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:42 PM PDT 24
Peak memory 201204 kb
Host smart-b88b5bd0-0f32-430d-a5b5-f81eefb8af5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950364288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.1950364288
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.388612927
Short name T682
Test name
Test status
Simulation time 2031269935 ps
CPU time 1.8 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:29:53 PM PDT 24
Peak memory 201296 kb
Host smart-e8e5a44f-63fc-47f2-aebf-e6b5b46ccfa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388612927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_tes
t.388612927
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1213099568
Short name T727
Test name
Test status
Simulation time 3828098916 ps
CPU time 5.62 seconds
Started Mar 14 01:29:49 PM PDT 24
Finished Mar 14 01:29:55 PM PDT 24
Peak memory 201304 kb
Host smart-5299728c-d763-4c52-9b0a-da2e5c03763e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213099568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.1
213099568
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.549649240
Short name T167
Test name
Test status
Simulation time 88551412392 ps
CPU time 23.47 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:30:16 PM PDT 24
Peak memory 201436 kb
Host smart-207c462f-84ea-4f08-b8c6-3670d733de51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549649240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_combo_detect.549649240
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2581714051
Short name T640
Test name
Test status
Simulation time 48917592833 ps
CPU time 132.11 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:32:03 PM PDT 24
Peak memory 201472 kb
Host smart-19fb57e8-3e04-498c-a1c2-c2767e07f951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581714051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2581714051
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4124145437
Short name T413
Test name
Test status
Simulation time 3105841954 ps
CPU time 2.68 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:42 PM PDT 24
Peak memory 201184 kb
Host smart-0c064759-d601-4ba7-b5e9-85e4bb358480
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124145437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.4124145437
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2862934583
Short name T443
Test name
Test status
Simulation time 2668598767 ps
CPU time 1.55 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:40 PM PDT 24
Peak memory 201216 kb
Host smart-e391c632-3b2a-4190-bfde-f4458a54b2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862934583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.2862934583
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.3065662191
Short name T329
Test name
Test status
Simulation time 2457473229 ps
CPU time 2.35 seconds
Started Mar 14 01:29:38 PM PDT 24
Finished Mar 14 01:29:40 PM PDT 24
Peak memory 201200 kb
Host smart-7929bc5e-9ebf-47e3-82ee-e94710930042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065662191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.3065662191
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4223489533
Short name T470
Test name
Test status
Simulation time 2193465306 ps
CPU time 1.46 seconds
Started Mar 14 01:29:37 PM PDT 24
Finished Mar 14 01:29:39 PM PDT 24
Peak memory 201120 kb
Host smart-b24ec845-0b1e-4eda-92c4-45446aa88708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223489533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.4223489533
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3224900031
Short name T606
Test name
Test status
Simulation time 2511721222 ps
CPU time 6.82 seconds
Started Mar 14 01:29:39 PM PDT 24
Finished Mar 14 01:29:46 PM PDT 24
Peak memory 201272 kb
Host smart-586330ac-e6bc-48ec-8597-9faba8070449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224900031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.3224900031
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.2400600788
Short name T428
Test name
Test status
Simulation time 2109238261 ps
CPU time 6.25 seconds
Started Mar 14 01:29:40 PM PDT 24
Finished Mar 14 01:29:47 PM PDT 24
Peak memory 201164 kb
Host smart-60ef576a-e500-45ca-85b5-d9dec44d3a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400600788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2400600788
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.895255755
Short name T186
Test name
Test status
Simulation time 49988890470 ps
CPU time 65.36 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:30:56 PM PDT 24
Peak memory 214036 kb
Host smart-9dc3ff06-8f1e-47b8-8a27-bf48cb56b911
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895255755 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.895255755
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1439108674
Short name T25
Test name
Test status
Simulation time 9243976530 ps
CPU time 3.97 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:29:56 PM PDT 24
Peak memory 201240 kb
Host smart-48f952c6-ba5f-4408-86c3-5bc6ec8aed96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439108674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.1439108674
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.1724603912
Short name T318
Test name
Test status
Simulation time 2013830443 ps
CPU time 6.05 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 201300 kb
Host smart-96fcb3fd-691c-49fc-acf9-7ab26703038b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724603912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.1724603912
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.4216071033
Short name T543
Test name
Test status
Simulation time 3668694733 ps
CPU time 10.8 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:30:03 PM PDT 24
Peak memory 201308 kb
Host smart-5d78fe53-67ff-43a5-94e1-beb6ba8e0415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216071033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.4
216071033
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.3248202418
Short name T529
Test name
Test status
Simulation time 166333624049 ps
CPU time 55.36 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:30:49 PM PDT 24
Peak memory 201384 kb
Host smart-0498ad2e-1d95-40ad-84b8-57d0623b0ff3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248202418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.3248202418
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1892975031
Short name T568
Test name
Test status
Simulation time 5153666337 ps
CPU time 7.26 seconds
Started Mar 14 01:29:54 PM PDT 24
Finished Mar 14 01:30:02 PM PDT 24
Peak memory 201192 kb
Host smart-cf091b22-a1f0-418e-8554-58cafe965631
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892975031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.1892975031
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.615149368
Short name T157
Test name
Test status
Simulation time 4233510100 ps
CPU time 2.34 seconds
Started Mar 14 01:29:49 PM PDT 24
Finished Mar 14 01:29:51 PM PDT 24
Peak memory 201264 kb
Host smart-32938c37-512d-4d76-b5ab-05039b54011e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615149368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctr
l_edge_detect.615149368
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3429381933
Short name T595
Test name
Test status
Simulation time 2617559420 ps
CPU time 4.18 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:29:58 PM PDT 24
Peak memory 201148 kb
Host smart-c4cf0314-53f7-41b8-b0f4-b2e627b18b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429381933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.3429381933
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2900255563
Short name T647
Test name
Test status
Simulation time 2490841384 ps
CPU time 2.46 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:29:54 PM PDT 24
Peak memory 201188 kb
Host smart-57c48d4a-6569-4502-991f-b6887c1892c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900255563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.2900255563
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3147250514
Short name T521
Test name
Test status
Simulation time 2220281616 ps
CPU time 2.07 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:29:54 PM PDT 24
Peak memory 201196 kb
Host smart-4cfef74c-7230-4057-bb1f-143c27f171a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147250514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.3147250514
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1929064335
Short name T676
Test name
Test status
Simulation time 2559487398 ps
CPU time 1.6 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:29:52 PM PDT 24
Peak memory 201268 kb
Host smart-a122aefa-25d3-420e-a97a-ea96a4ff7b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929064335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.1929064335
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.3263276255
Short name T535
Test name
Test status
Simulation time 2112834615 ps
CPU time 6.25 seconds
Started Mar 14 01:29:55 PM PDT 24
Finished Mar 14 01:30:01 PM PDT 24
Peak memory 201084 kb
Host smart-510d251f-537f-4643-ba59-58a78436eb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263276255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.3263276255
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.810780857
Short name T432
Test name
Test status
Simulation time 6694008523 ps
CPU time 5.01 seconds
Started Mar 14 01:29:57 PM PDT 24
Finished Mar 14 01:30:02 PM PDT 24
Peak memory 201128 kb
Host smart-3206d11f-f043-4302-99ff-b36a925f8fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810780857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_st
ress_all.810780857
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.93716047
Short name T99
Test name
Test status
Simulation time 46697430126 ps
CPU time 119.56 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:31:50 PM PDT 24
Peak memory 217924 kb
Host smart-7f135dc5-5c04-4f54-84fd-808edfab6cee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93716047 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.93716047
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2022044758
Short name T395
Test name
Test status
Simulation time 342546265805 ps
CPU time 44.66 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:30:37 PM PDT 24
Peak memory 201208 kb
Host smart-dd29a9e4-d96a-49bf-9e84-70365c904fdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022044758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.2022044758
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.3373612949
Short name T213
Test name
Test status
Simulation time 2015858012 ps
CPU time 3.31 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:29:54 PM PDT 24
Peak memory 201272 kb
Host smart-a032e88d-c8e4-423d-a071-e8dd64862ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373612949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.3373612949
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.171028767
Short name T656
Test name
Test status
Simulation time 148962267908 ps
CPU time 191.6 seconds
Started Mar 14 01:29:49 PM PDT 24
Finished Mar 14 01:33:00 PM PDT 24
Peak memory 201268 kb
Host smart-40755523-c5f8-4373-b764-cfc04e34a157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171028767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.171028767
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.2288008350
Short name T361
Test name
Test status
Simulation time 61064467477 ps
CPU time 38.75 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:30:31 PM PDT 24
Peak memory 201376 kb
Host smart-b5f94046-3c05-4d1f-bbe1-f09bec9ff3bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288008350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.2288008350
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2192877182
Short name T360
Test name
Test status
Simulation time 55813157837 ps
CPU time 149.35 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:32:21 PM PDT 24
Peak memory 201468 kb
Host smart-7851a8e6-f6cf-4df5-abc0-b351932b0d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192877182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.2192877182
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1119437251
Short name T602
Test name
Test status
Simulation time 5558543054 ps
CPU time 3.99 seconds
Started Mar 14 01:29:55 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 201088 kb
Host smart-8dd35566-64d4-4350-9a28-e3ec08226bb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119437251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.1119437251
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.4154874209
Short name T137
Test name
Test status
Simulation time 3545236228 ps
CPU time 6.78 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:29:57 PM PDT 24
Peak memory 201156 kb
Host smart-6e4f3a82-bba1-4e16-afde-9ababcb5f2c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154874209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.4154874209
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.291440485
Short name T616
Test name
Test status
Simulation time 2610802900 ps
CPU time 7.54 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 201160 kb
Host smart-7f39a0d2-03e8-4cca-82d1-a28ef9adf98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291440485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.291440485
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2712675081
Short name T758
Test name
Test status
Simulation time 2443616250 ps
CPU time 3.84 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:29:54 PM PDT 24
Peak memory 201172 kb
Host smart-4ecd2ae5-d82f-42cc-a2dd-4b5e4c73c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712675081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.2712675081
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1089813594
Short name T588
Test name
Test status
Simulation time 2084677641 ps
CPU time 1.84 seconds
Started Mar 14 01:29:49 PM PDT 24
Finished Mar 14 01:29:51 PM PDT 24
Peak memory 201096 kb
Host smart-54863abd-4f24-434f-9299-ee4518fa0aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089813594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.1089813594
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2000324259
Short name T471
Test name
Test status
Simulation time 2537422650 ps
CPU time 2.27 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:29:55 PM PDT 24
Peak memory 201272 kb
Host smart-38ada2ee-b93a-4145-bf11-9f0c6c2f8a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000324259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2000324259
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.3135443000
Short name T467
Test name
Test status
Simulation time 2129650163 ps
CPU time 2.2 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:29:53 PM PDT 24
Peak memory 201068 kb
Host smart-01060049-9ffd-4c1e-9909-1e4bdc7132a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135443000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3135443000
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.3079571175
Short name T131
Test name
Test status
Simulation time 60080995915 ps
CPU time 42.88 seconds
Started Mar 14 01:29:55 PM PDT 24
Finished Mar 14 01:30:38 PM PDT 24
Peak memory 201356 kb
Host smart-df62d053-373b-404a-8a1e-179c6fa94045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079571175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.3079571175
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.19829168
Short name T754
Test name
Test status
Simulation time 2783117207 ps
CPU time 1.99 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:29:53 PM PDT 24
Peak memory 201204 kb
Host smart-6db16cb4-dba7-4376-a881-a4038af2397c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19829168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_ultra_low_pwr.19829168
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.3995254764
Short name T757
Test name
Test status
Simulation time 2036479519 ps
CPU time 1.65 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:29:53 PM PDT 24
Peak memory 201276 kb
Host smart-29c2fcf1-3c1a-4e34-af2a-ee524c281ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995254764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.3995254764
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1254464885
Short name T17
Test name
Test status
Simulation time 3469538967 ps
CPU time 4.99 seconds
Started Mar 14 01:29:57 PM PDT 24
Finished Mar 14 01:30:02 PM PDT 24
Peak memory 201128 kb
Host smart-cbc48269-b512-4b39-bf90-c9d8ea663a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254464885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1
254464885
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3835023060
Short name T4
Test name
Test status
Simulation time 73602327835 ps
CPU time 177.39 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:32:48 PM PDT 24
Peak memory 201336 kb
Host smart-f3222c20-a4d9-45a6-94a9-71bcf7f0843c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835023060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.3835023060
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2333539180
Short name T182
Test name
Test status
Simulation time 2552529043 ps
CPU time 7.06 seconds
Started Mar 14 01:29:54 PM PDT 24
Finished Mar 14 01:30:02 PM PDT 24
Peak memory 201192 kb
Host smart-98f2c77d-7a09-40b6-ba19-6af9a8ff8493
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333539180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.2333539180
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.487458560
Short name T703
Test name
Test status
Simulation time 3187509914 ps
CPU time 8.69 seconds
Started Mar 14 01:29:48 PM PDT 24
Finished Mar 14 01:29:56 PM PDT 24
Peak memory 201180 kb
Host smart-d9e5f5b6-7ea9-4260-b07f-3bbb75cc142b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487458560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctr
l_edge_detect.487458560
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.371249714
Short name T664
Test name
Test status
Simulation time 2634030555 ps
CPU time 2.41 seconds
Started Mar 14 01:29:54 PM PDT 24
Finished Mar 14 01:29:56 PM PDT 24
Peak memory 201176 kb
Host smart-f6fa957f-bdce-41c2-a49d-e3109586f6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371249714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.371249714
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3039750346
Short name T502
Test name
Test status
Simulation time 2469305498 ps
CPU time 2.22 seconds
Started Mar 14 01:29:54 PM PDT 24
Finished Mar 14 01:29:56 PM PDT 24
Peak memory 201148 kb
Host smart-3ec065f2-5a81-468e-82aa-dcdc0190549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039750346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3039750346
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2915634749
Short name T222
Test name
Test status
Simulation time 2215407194 ps
CPU time 3.37 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:29:55 PM PDT 24
Peak memory 201196 kb
Host smart-da458054-bf39-4ad6-935a-7f65c695259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915634749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2915634749
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.81327916
Short name T753
Test name
Test status
Simulation time 2541653215 ps
CPU time 2.05 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:29:55 PM PDT 24
Peak memory 201260 kb
Host smart-3541a357-b7a2-4d9b-a42d-4e11480d3d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81327916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.81327916
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.4060623688
Short name T445
Test name
Test status
Simulation time 2111365753 ps
CPU time 4.27 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:29:54 PM PDT 24
Peak memory 201172 kb
Host smart-b471512c-4e28-495b-80c0-e777ad10a5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060623688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.4060623688
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.2102569794
Short name T9
Test name
Test status
Simulation time 7846684233 ps
CPU time 3.79 seconds
Started Mar 14 01:29:56 PM PDT 24
Finished Mar 14 01:30:00 PM PDT 24
Peak memory 201064 kb
Host smart-78c4ffc6-60f4-4c65-b774-99358012fcce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102569794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.2102569794
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2561341788
Short name T136
Test name
Test status
Simulation time 189124853956 ps
CPU time 510.94 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:38:21 PM PDT 24
Peak memory 209920 kb
Host smart-3356a0ec-2228-45a6-9bc3-fbf7ab3bb973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561341788 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2561341788
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2888387743
Short name T325
Test name
Test status
Simulation time 6897040776 ps
CPU time 1.2 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:29:52 PM PDT 24
Peak memory 201176 kb
Host smart-d3cd5f9e-a9db-4e16-813a-ee8576971d97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888387743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.2888387743
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.3599123473
Short name T532
Test name
Test status
Simulation time 2011098764 ps
CPU time 5.75 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 201304 kb
Host smart-971eb5d1-e53b-462d-869c-98b724b9c83f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599123473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.3599123473
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3872753185
Short name T299
Test name
Test status
Simulation time 3048508058 ps
CPU time 4.24 seconds
Started Mar 14 01:29:55 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 201100 kb
Host smart-b65c0245-89e1-4591-b26e-920576ac8e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872753185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.3
872753185
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.3041850746
Short name T313
Test name
Test status
Simulation time 74501552919 ps
CPU time 194.56 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:33:06 PM PDT 24
Peak memory 201420 kb
Host smart-c0bf47e2-3ce2-402d-abce-4d589f17eba7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041850746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.3041850746
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3531648239
Short name T55
Test name
Test status
Simulation time 49884849716 ps
CPU time 71.48 seconds
Started Mar 14 01:29:49 PM PDT 24
Finished Mar 14 01:31:01 PM PDT 24
Peak memory 201420 kb
Host smart-08db851f-7a59-4ad4-9673-9063ced1edab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531648239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.3531648239
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2950600763
Short name T714
Test name
Test status
Simulation time 4869314405 ps
CPU time 9.77 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:30:03 PM PDT 24
Peak memory 201192 kb
Host smart-4e667b1f-118e-4789-80fc-0416a71ec19f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950600763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.2950600763
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2397329570
Short name T218
Test name
Test status
Simulation time 3643458767 ps
CPU time 5.48 seconds
Started Mar 14 01:29:54 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 201208 kb
Host smart-6a8bc86f-bf96-4fb5-81e2-c4897fe8ff6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397329570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.2397329570
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.863932238
Short name T404
Test name
Test status
Simulation time 2611650962 ps
CPU time 6.99 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 201188 kb
Host smart-1d631a50-71b6-4912-a15a-64fd4c86f512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863932238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.863932238
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.79612541
Short name T672
Test name
Test status
Simulation time 2460596909 ps
CPU time 2.26 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:29:52 PM PDT 24
Peak memory 201232 kb
Host smart-5d7cf0ba-a9ff-4284-a5e0-1cf6e54a7228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79612541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.79612541
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.665259032
Short name T609
Test name
Test status
Simulation time 2130010157 ps
CPU time 2 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:29:53 PM PDT 24
Peak memory 201148 kb
Host smart-15fbc301-2acb-43c7-bd73-90eaa8eeca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665259032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.665259032
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.888935055
Short name T707
Test name
Test status
Simulation time 2558899818 ps
CPU time 1.59 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:29:53 PM PDT 24
Peak memory 201272 kb
Host smart-2cf753ff-72e0-485e-b216-836cb58af562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888935055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.888935055
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.2430444657
Short name T163
Test name
Test status
Simulation time 2112436886 ps
CPU time 5.41 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:29:57 PM PDT 24
Peak memory 201100 kb
Host smart-c41788cc-1461-486b-9c2d-0ee114ef6c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430444657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2430444657
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.44512045
Short name T466
Test name
Test status
Simulation time 7248742755 ps
CPU time 8.98 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:30:02 PM PDT 24
Peak memory 201196 kb
Host smart-a1976681-e70c-4744-9ed3-0eee13b4d044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44512045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_str
ess_all.44512045
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2813058880
Short name T709
Test name
Test status
Simulation time 4860005454 ps
CPU time 3.8 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:29:56 PM PDT 24
Peak memory 201196 kb
Host smart-d3dab4eb-319a-4c5a-a85f-132ccb970fd9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813058880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.2813058880
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.2230361383
Short name T710
Test name
Test status
Simulation time 2024207255 ps
CPU time 2.92 seconds
Started Mar 14 01:29:52 PM PDT 24
Finished Mar 14 01:29:55 PM PDT 24
Peak memory 201296 kb
Host smart-818b132d-a2b1-4394-bf77-c1f4071d3ee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230361383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.2230361383
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.348419688
Short name T50
Test name
Test status
Simulation time 3298069458 ps
CPU time 2.53 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:01 PM PDT 24
Peak memory 201244 kb
Host smart-5c201634-d0b3-46da-a5aa-bef278e3bd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348419688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.348419688
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.1468503085
Short name T128
Test name
Test status
Simulation time 58496163246 ps
CPU time 23.63 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:22 PM PDT 24
Peak memory 201408 kb
Host smart-71df67ac-ee60-4a49-927a-cc9710522bad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468503085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.1468503085
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3641333816
Short name T600
Test name
Test status
Simulation time 19080831912 ps
CPU time 49.06 seconds
Started Mar 14 01:29:54 PM PDT 24
Finished Mar 14 01:30:44 PM PDT 24
Peak memory 201496 kb
Host smart-24896df5-ccf2-49d8-a922-506972049049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641333816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.3641333816
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1833529831
Short name T755
Test name
Test status
Simulation time 4187872992 ps
CPU time 3.25 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:01 PM PDT 24
Peak memory 201164 kb
Host smart-fc7efcad-301b-4d12-b8d0-aadc51c9a425
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833529831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.1833529831
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1365673843
Short name T228
Test name
Test status
Simulation time 4312857808 ps
CPU time 1.93 seconds
Started Mar 14 01:29:57 PM PDT 24
Finished Mar 14 01:29:59 PM PDT 24
Peak memory 201072 kb
Host smart-6653f141-6b43-4da8-a833-43d41dac6917
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365673843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.1365673843
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3195215594
Short name T732
Test name
Test status
Simulation time 2612580830 ps
CPU time 7.44 seconds
Started Mar 14 01:29:53 PM PDT 24
Finished Mar 14 01:30:00 PM PDT 24
Peak memory 201148 kb
Host smart-111e31a4-6f08-49da-8b29-927f3cd14444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195215594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.3195215594
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2048102750
Short name T779
Test name
Test status
Simulation time 2483657941 ps
CPU time 1.86 seconds
Started Mar 14 01:29:56 PM PDT 24
Finished Mar 14 01:29:58 PM PDT 24
Peak memory 201076 kb
Host smart-f2306619-aa4a-46ef-9e92-3691150823cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048102750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2048102750
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.4089403929
Short name T524
Test name
Test status
Simulation time 2111337651 ps
CPU time 3.52 seconds
Started Mar 14 01:29:48 PM PDT 24
Finished Mar 14 01:29:52 PM PDT 24
Peak memory 201108 kb
Host smart-49f357ae-8000-49b0-9e4d-f9649ff64b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089403929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.4089403929
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1618996360
Short name T453
Test name
Test status
Simulation time 2521714616 ps
CPU time 2.26 seconds
Started Mar 14 01:29:55 PM PDT 24
Finished Mar 14 01:29:57 PM PDT 24
Peak memory 201276 kb
Host smart-af0ec3fd-5d1f-4fe5-b9b7-7f60971d2162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618996360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1618996360
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.298354198
Short name T539
Test name
Test status
Simulation time 2114923896 ps
CPU time 3.2 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:01 PM PDT 24
Peak memory 201100 kb
Host smart-786b580f-e449-40c5-9d6f-558ba8901950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298354198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.298354198
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.3299502735
Short name T729
Test name
Test status
Simulation time 84371317516 ps
CPU time 211.43 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:33:29 PM PDT 24
Peak memory 201300 kb
Host smart-ae3c995c-dc30-4605-a469-421fb808cd20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299502735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.3299502735
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1889102972
Short name T123
Test name
Test status
Simulation time 420383874055 ps
CPU time 154.63 seconds
Started Mar 14 01:29:55 PM PDT 24
Finished Mar 14 01:32:30 PM PDT 24
Peak memory 209816 kb
Host smart-e25e7bfa-7ead-4463-87fe-d27cf0163c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889102972 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1889102972
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2305138665
Short name T786
Test name
Test status
Simulation time 782494152664 ps
CPU time 29.86 seconds
Started Mar 14 01:29:57 PM PDT 24
Finished Mar 14 01:30:27 PM PDT 24
Peak memory 201072 kb
Host smart-14ae484f-66b9-4219-a9cf-d15051143856
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305138665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.2305138665
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.2637131306
Short name T434
Test name
Test status
Simulation time 2019098329 ps
CPU time 3.54 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:01 PM PDT 24
Peak memory 201308 kb
Host smart-4252b5dc-0fce-4d1c-aaa0-5df30d673064
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637131306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.2637131306
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1953683065
Short name T749
Test name
Test status
Simulation time 173847387732 ps
CPU time 131.33 seconds
Started Mar 14 01:29:51 PM PDT 24
Finished Mar 14 01:32:03 PM PDT 24
Peak memory 201244 kb
Host smart-b832a677-4ba5-4196-9c8e-cd46a8ca8ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953683065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1
953683065
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3864871270
Short name T742
Test name
Test status
Simulation time 57335433330 ps
CPU time 148.42 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:32:19 PM PDT 24
Peak memory 201372 kb
Host smart-fe920347-4128-4843-9d9c-22043c7ac575
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864871270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.3864871270
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2881195962
Short name T93
Test name
Test status
Simulation time 22579346178 ps
CPU time 60.89 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:59 PM PDT 24
Peak memory 201532 kb
Host smart-2d7dea35-f430-4b70-8f63-a929eb8c78e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881195962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.2881195962
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2393203875
Short name T520
Test name
Test status
Simulation time 3033629382 ps
CPU time 8.08 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:29:58 PM PDT 24
Peak memory 201164 kb
Host smart-3e8435c0-1a24-4617-ba1d-25572cd32f93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393203875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.2393203875
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1527703095
Short name T627
Test name
Test status
Simulation time 4180585140 ps
CPU time 2.74 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:01 PM PDT 24
Peak memory 201220 kb
Host smart-06bb330a-ba8e-47d8-82c8-a171291eebc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527703095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.1527703095
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3597664091
Short name T720
Test name
Test status
Simulation time 2608508960 ps
CPU time 7.52 seconds
Started Mar 14 01:29:55 PM PDT 24
Finished Mar 14 01:30:03 PM PDT 24
Peak memory 200796 kb
Host smart-2b6d2474-64eb-4b25-9d24-a9f4651266e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597664091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3597664091
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2895954514
Short name T230
Test name
Test status
Simulation time 2468601481 ps
CPU time 3.1 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:01 PM PDT 24
Peak memory 201224 kb
Host smart-13637858-f178-40c3-bf38-fa8896e053d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895954514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.2895954514
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.309057068
Short name T692
Test name
Test status
Simulation time 2150681424 ps
CPU time 5.76 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:04 PM PDT 24
Peak memory 201168 kb
Host smart-ba414dc8-9b69-4bcb-b4b4-068ed37f479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309057068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.309057068
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4142749602
Short name T447
Test name
Test status
Simulation time 2553984062 ps
CPU time 1.81 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:00 PM PDT 24
Peak memory 201304 kb
Host smart-3f7358fe-4d22-4da3-a9f7-48a76f49e520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142749602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.4142749602
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.2987473584
Short name T527
Test name
Test status
Simulation time 2113091418 ps
CPU time 5.77 seconds
Started Mar 14 01:29:49 PM PDT 24
Finished Mar 14 01:29:55 PM PDT 24
Peak memory 201328 kb
Host smart-19524175-9f3e-47c8-a85e-d4a013dfebcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987473584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2987473584
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.717869682
Short name T751
Test name
Test status
Simulation time 167572078999 ps
CPU time 212.73 seconds
Started Mar 14 01:29:55 PM PDT 24
Finished Mar 14 01:33:28 PM PDT 24
Peak memory 201192 kb
Host smart-a1b5238f-fbc9-4808-94ef-e568d201df5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717869682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_st
ress_all.717869682
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3114884152
Short name T174
Test name
Test status
Simulation time 80398092116 ps
CPU time 53.23 seconds
Started Mar 14 01:29:55 PM PDT 24
Finished Mar 14 01:30:48 PM PDT 24
Peak memory 217776 kb
Host smart-d8d49c09-4f17-4b4a-89ec-685541ead829
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114884152 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3114884152
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2696832433
Short name T646
Test name
Test status
Simulation time 2613277341 ps
CPU time 1.94 seconds
Started Mar 14 01:29:58 PM PDT 24
Finished Mar 14 01:30:00 PM PDT 24
Peak memory 201216 kb
Host smart-7cba8ba3-c38a-4dc3-a41c-0536c044f303
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696832433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.2696832433
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.3380839570
Short name T401
Test name
Test status
Simulation time 2012949214 ps
CPU time 5.5 seconds
Started Mar 14 01:30:06 PM PDT 24
Finished Mar 14 01:30:12 PM PDT 24
Peak memory 201252 kb
Host smart-e1429020-32f5-4ac1-8836-5cc5ab9f1292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380839570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.3380839570
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.915155143
Short name T719
Test name
Test status
Simulation time 3566035667 ps
CPU time 9.57 seconds
Started Mar 14 01:30:03 PM PDT 24
Finished Mar 14 01:30:13 PM PDT 24
Peak memory 201244 kb
Host smart-74042b98-49e4-4f9e-b5a6-2b07a0c04803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915155143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.915155143
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.3368888404
Short name T223
Test name
Test status
Simulation time 48193404191 ps
CPU time 63.93 seconds
Started Mar 14 01:30:04 PM PDT 24
Finished Mar 14 01:31:08 PM PDT 24
Peak memory 201344 kb
Host smart-1b7b740d-2a5f-419e-9fb9-f4fc96898d64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368888404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.3368888404
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1800325095
Short name T380
Test name
Test status
Simulation time 69843322119 ps
CPU time 91.69 seconds
Started Mar 14 01:30:04 PM PDT 24
Finished Mar 14 01:31:37 PM PDT 24
Peak memory 201404 kb
Host smart-121a60c5-edf2-4221-ad51-3896ada227d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800325095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.1800325095
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.362569307
Short name T400
Test name
Test status
Simulation time 4311533154 ps
CPU time 3.63 seconds
Started Mar 14 01:30:04 PM PDT 24
Finished Mar 14 01:30:08 PM PDT 24
Peak memory 201184 kb
Host smart-13dc5add-c015-4e46-8a96-2ed431e5bd43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362569307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ec_pwr_on_rst.362569307
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2580042608
Short name T192
Test name
Test status
Simulation time 2689538816 ps
CPU time 6.68 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:30:09 PM PDT 24
Peak memory 201204 kb
Host smart-b096ac99-9baa-47ae-b7f2-b5a1a89ce87e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580042608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.2580042608
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1171810449
Short name T739
Test name
Test status
Simulation time 2612436980 ps
CPU time 7.4 seconds
Started Mar 14 01:30:01 PM PDT 24
Finished Mar 14 01:30:08 PM PDT 24
Peak memory 201264 kb
Host smart-3c9adc67-887c-4279-8934-da84699b97cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171810449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.1171810449
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1708337505
Short name T781
Test name
Test status
Simulation time 2484395051 ps
CPU time 2.32 seconds
Started Mar 14 01:30:03 PM PDT 24
Finished Mar 14 01:30:05 PM PDT 24
Peak memory 201212 kb
Host smart-ccc62852-c9f2-49c4-b827-414fe576db59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708337505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.1708337505
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.273340840
Short name T494
Test name
Test status
Simulation time 2225889455 ps
CPU time 6.23 seconds
Started Mar 14 01:30:08 PM PDT 24
Finished Mar 14 01:30:14 PM PDT 24
Peak memory 201192 kb
Host smart-7f4f48b9-5e2f-4707-8284-d6b96d575ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273340840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.273340840
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1464782508
Short name T772
Test name
Test status
Simulation time 2510550855 ps
CPU time 7.99 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:30:10 PM PDT 24
Peak memory 201260 kb
Host smart-15e26dd7-737b-4a59-b378-81e9fabe1cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464782508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1464782508
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.127362470
Short name T397
Test name
Test status
Simulation time 2138638765 ps
CPU time 1.39 seconds
Started Mar 14 01:29:50 PM PDT 24
Finished Mar 14 01:29:52 PM PDT 24
Peak memory 201124 kb
Host smart-5300fd24-e3b1-40fe-bab3-675876cb9478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127362470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.127362470
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.1275751708
Short name T765
Test name
Test status
Simulation time 11440753894 ps
CPU time 31.84 seconds
Started Mar 14 01:30:00 PM PDT 24
Finished Mar 14 01:30:31 PM PDT 24
Peak memory 201144 kb
Host smart-b9fd11f6-449c-4a1e-8ff8-36dde7bf6841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275751708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.1275751708
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3552767755
Short name T118
Test name
Test status
Simulation time 4765081668 ps
CPU time 7.57 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:30:10 PM PDT 24
Peak memory 201200 kb
Host smart-1c7595ba-178c-4a09-85db-5dbaabe45083
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552767755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3552767755
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.3166248423
Short name T621
Test name
Test status
Simulation time 2073402400 ps
CPU time 1.12 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:08 PM PDT 24
Peak memory 201260 kb
Host smart-a1933a15-31e8-4aa8-9e05-8e8e3de41c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166248423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.3166248423
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1833946758
Short name T31
Test name
Test status
Simulation time 3955461738 ps
CPU time 5.21 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 201268 kb
Host smart-38224535-1175-472c-9e12-8470cd32483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833946758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1833946758
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3384299072
Short name T791
Test name
Test status
Simulation time 87399406962 ps
CPU time 112.52 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:29:58 PM PDT 24
Peak memory 201380 kb
Host smart-76bd3dba-4c46-4a90-b413-ffa2d5e4b12a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384299072 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3384299072
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.4290993003
Short name T80
Test name
Test status
Simulation time 78351598023 ps
CPU time 217 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 201452 kb
Host smart-40383c62-ad48-46ba-8898-d573e4d88a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290993003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.4290993003
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2220190804
Short name T671
Test name
Test status
Simulation time 3670739598 ps
CPU time 2.93 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:28:10 PM PDT 24
Peak memory 201160 kb
Host smart-5ed4e62a-eb6c-4d17-8448-567733fe33f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220190804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.2220190804
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.1462881619
Short name T37
Test name
Test status
Simulation time 2475687071 ps
CPU time 2.26 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:28:06 PM PDT 24
Peak memory 201212 kb
Host smart-30fb63b6-1f7e-496b-a2f1-e5eb6b91eda8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462881619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.1462881619
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.4278299826
Short name T317
Test name
Test status
Simulation time 2626866757 ps
CPU time 2.68 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 201180 kb
Host smart-fbf02c87-56aa-4ef7-a9cc-cd8451f24a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278299826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.4278299826
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1404560433
Short name T773
Test name
Test status
Simulation time 2481218632 ps
CPU time 1.93 seconds
Started Mar 14 01:27:58 PM PDT 24
Finished Mar 14 01:28:00 PM PDT 24
Peak memory 201152 kb
Host smart-caf0fba0-003a-46b9-82dd-92f8a17b8d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404560433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1404560433
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.4046806454
Short name T503
Test name
Test status
Simulation time 2060072775 ps
CPU time 1.9 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:08 PM PDT 24
Peak memory 201112 kb
Host smart-e944f56a-fcc1-4da4-8c96-61f503ac0b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046806454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.4046806454
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.2423913127
Short name T334
Test name
Test status
Simulation time 2561681917 ps
CPU time 1.5 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 201160 kb
Host smart-eac37a50-03a5-491c-8b08-0b4e0b916457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423913127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.2423913127
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.3564562844
Short name T496
Test name
Test status
Simulation time 2113589551 ps
CPU time 6.34 seconds
Started Mar 14 01:28:08 PM PDT 24
Finished Mar 14 01:28:14 PM PDT 24
Peak memory 201112 kb
Host smart-f369c9ec-c506-490a-ba8f-d420daa0800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564562844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.3564562844
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.949592529
Short name T45
Test name
Test status
Simulation time 79582456930 ps
CPU time 204.5 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:31:29 PM PDT 24
Peak memory 201464 kb
Host smart-6326e63a-5062-403a-b512-ecce7668346b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949592529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_str
ess_all.949592529
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.628081241
Short name T258
Test name
Test status
Simulation time 35063715657 ps
CPU time 49.87 seconds
Started Mar 14 01:30:04 PM PDT 24
Finished Mar 14 01:30:55 PM PDT 24
Peak memory 201436 kb
Host smart-7e0f1817-c88d-4841-87d9-5e3da698128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628081241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_wi
th_pre_cond.628081241
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2042768695
Short name T94
Test name
Test status
Simulation time 85224609953 ps
CPU time 173.46 seconds
Started Mar 14 01:30:03 PM PDT 24
Finished Mar 14 01:32:56 PM PDT 24
Peak memory 201412 kb
Host smart-0aef1e82-6653-452f-a4ac-e9ecacff0a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042768695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.2042768695
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2832124147
Short name T766
Test name
Test status
Simulation time 38369416569 ps
CPU time 49.44 seconds
Started Mar 14 01:30:08 PM PDT 24
Finished Mar 14 01:30:58 PM PDT 24
Peak memory 201476 kb
Host smart-16dc9b65-7db0-441c-8f40-022fd7e310c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832124147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.2832124147
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1574349944
Short name T232
Test name
Test status
Simulation time 29603461163 ps
CPU time 41.24 seconds
Started Mar 14 01:30:00 PM PDT 24
Finished Mar 14 01:30:41 PM PDT 24
Peak memory 201436 kb
Host smart-857c2607-1270-4618-a0b9-e9ca19cf3387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574349944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.1574349944
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3436461361
Short name T377
Test name
Test status
Simulation time 72938868644 ps
CPU time 204.54 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:33:26 PM PDT 24
Peak memory 201440 kb
Host smart-b26a5e2c-32d2-4f94-8cbc-f68b159fd76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436461361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.3436461361
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.3640271990
Short name T762
Test name
Test status
Simulation time 2042198290 ps
CPU time 1.81 seconds
Started Mar 14 01:28:05 PM PDT 24
Finished Mar 14 01:28:07 PM PDT 24
Peak memory 201280 kb
Host smart-44d2e10b-ab24-4dfc-81a1-62e0972c9784
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640271990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.3640271990
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2601615656
Short name T312
Test name
Test status
Simulation time 3471505823 ps
CPU time 2.26 seconds
Started Mar 14 01:28:03 PM PDT 24
Finished Mar 14 01:28:05 PM PDT 24
Peak memory 201236 kb
Host smart-9eb39db2-328a-480d-9ec5-69a1ba814c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601615656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.2601615656
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.2965194962
Short name T359
Test name
Test status
Simulation time 64968315774 ps
CPU time 88.64 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:29:35 PM PDT 24
Peak memory 201428 kb
Host smart-14a0d234-86bf-4235-b868-629a5f3b3ad7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965194962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.2965194962
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2945762607
Short name T314
Test name
Test status
Simulation time 3772293750 ps
CPU time 5.11 seconds
Started Mar 14 01:28:05 PM PDT 24
Finished Mar 14 01:28:10 PM PDT 24
Peak memory 201172 kb
Host smart-6aec310b-3a21-4cbd-b5bc-51b719202340
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945762607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2945762607
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1743841189
Short name T764
Test name
Test status
Simulation time 3182306568 ps
CPU time 2 seconds
Started Mar 14 01:28:05 PM PDT 24
Finished Mar 14 01:28:07 PM PDT 24
Peak memory 201232 kb
Host smart-3998536f-3f51-4cb3-8efe-7245586c2146
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743841189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1743841189
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3263795580
Short name T485
Test name
Test status
Simulation time 2607136867 ps
CPU time 7.73 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:28:15 PM PDT 24
Peak memory 201224 kb
Host smart-f63b7ad0-b9d2-4fb0-9f1a-551f778eae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263795580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3263795580
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1352251838
Short name T691
Test name
Test status
Simulation time 2443915710 ps
CPU time 7.05 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:28:11 PM PDT 24
Peak memory 201160 kb
Host smart-df8ab195-9deb-4787-86e0-82bcf99fd922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352251838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1352251838
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4218191224
Short name T518
Test name
Test status
Simulation time 2106466914 ps
CPU time 1.41 seconds
Started Mar 14 01:28:03 PM PDT 24
Finished Mar 14 01:28:04 PM PDT 24
Peak memory 201152 kb
Host smart-3df8e1c8-c394-45ce-8e07-a216f8b9832a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218191224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.4218191224
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2979782511
Short name T208
Test name
Test status
Simulation time 2508856817 ps
CPU time 7.39 seconds
Started Mar 14 01:28:08 PM PDT 24
Finished Mar 14 01:28:16 PM PDT 24
Peak memory 201244 kb
Host smart-244aea0a-e73b-40ab-b171-c3a317668646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979782511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.2979782511
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.179092314
Short name T178
Test name
Test status
Simulation time 2114823344 ps
CPU time 4.73 seconds
Started Mar 14 01:28:09 PM PDT 24
Finished Mar 14 01:28:14 PM PDT 24
Peak memory 201116 kb
Host smart-66024b19-d4d1-4e5d-8db0-46ffccd82151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179092314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.179092314
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3781880497
Short name T96
Test name
Test status
Simulation time 130221616911 ps
CPU time 93.8 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:29:40 PM PDT 24
Peak memory 218048 kb
Host smart-85b97f1f-8683-4ef6-8a19-76b1284adb52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781880497 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.3781880497
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1848259997
Short name T120
Test name
Test status
Simulation time 7222745761 ps
CPU time 8.22 seconds
Started Mar 14 01:28:08 PM PDT 24
Finished Mar 14 01:28:16 PM PDT 24
Peak memory 201196 kb
Host smart-2ec2d39b-b9e7-47a4-9294-623420614222
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848259997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.1848259997
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3241636404
Short name T592
Test name
Test status
Simulation time 68368971795 ps
CPU time 175.56 seconds
Started Mar 14 01:30:07 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 201508 kb
Host smart-7ddc9a6d-1aba-433f-af93-9904120ac32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241636404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.3241636404
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1763853338
Short name T677
Test name
Test status
Simulation time 55683030228 ps
CPU time 42.48 seconds
Started Mar 14 01:30:01 PM PDT 24
Finished Mar 14 01:30:44 PM PDT 24
Peak memory 201424 kb
Host smart-bad875e2-8b97-4c97-b2d6-636f40572d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763853338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.1763853338
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3433502045
Short name T371
Test name
Test status
Simulation time 90834096947 ps
CPU time 114.31 seconds
Started Mar 14 01:30:03 PM PDT 24
Finished Mar 14 01:31:57 PM PDT 24
Peak memory 201392 kb
Host smart-8ed25ce3-181a-4fe7-9ad4-21c063255299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433502045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3433502045
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1066763136
Short name T177
Test name
Test status
Simulation time 107991454548 ps
CPU time 93.49 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:31:36 PM PDT 24
Peak memory 201376 kb
Host smart-08699605-655b-4d83-a038-4b6764c5ead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066763136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.1066763136
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.2719413622
Short name T32
Test name
Test status
Simulation time 64160618923 ps
CPU time 42.73 seconds
Started Mar 14 01:30:04 PM PDT 24
Finished Mar 14 01:30:47 PM PDT 24
Peak memory 201532 kb
Host smart-a41b929c-804a-440a-bacf-d0dab0a83b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719413622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.2719413622
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.4011226764
Short name T585
Test name
Test status
Simulation time 2014761947 ps
CPU time 6.25 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:28:13 PM PDT 24
Peak memory 201228 kb
Host smart-4088d2ca-38be-43d8-93aa-66fc2b29e48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011226764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.4011226764
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3004704275
Short name T47
Test name
Test status
Simulation time 3527570177 ps
CPU time 1.84 seconds
Started Mar 14 01:28:09 PM PDT 24
Finished Mar 14 01:28:10 PM PDT 24
Peak memory 201264 kb
Host smart-d7974c83-2198-4ece-9528-016ba42baa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004704275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.3004704275
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.1500545904
Short name T261
Test name
Test status
Simulation time 141951847617 ps
CPU time 179.1 seconds
Started Mar 14 01:28:03 PM PDT 24
Finished Mar 14 01:31:02 PM PDT 24
Peak memory 201460 kb
Host smart-871123f7-3d1d-4109-8624-f57cc63c9355
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500545904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.1500545904
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.4147415398
Short name T793
Test name
Test status
Simulation time 59994273195 ps
CPU time 87.84 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:29:35 PM PDT 24
Peak memory 201360 kb
Host smart-a27fee85-6431-4559-acfb-35b40f0a40f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147415398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.4147415398
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.37161756
Short name T586
Test name
Test status
Simulation time 4208343361 ps
CPU time 11.54 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:28:19 PM PDT 24
Peak memory 201212 kb
Host smart-8d9d5bf7-41dd-4d84-b0e2-dee7875add26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37161756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_ec_pwr_on_rst.37161756
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.4136349206
Short name T611
Test name
Test status
Simulation time 3465926517 ps
CPU time 4.07 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 201148 kb
Host smart-44104e4c-a4be-40a7-94e3-6005f53cb6dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136349206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.4136349206
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1532156465
Short name T789
Test name
Test status
Simulation time 2615316306 ps
CPU time 4.16 seconds
Started Mar 14 01:28:05 PM PDT 24
Finished Mar 14 01:28:10 PM PDT 24
Peak memory 201236 kb
Host smart-1898d7ca-4a73-4b2d-b01c-8871540cc888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532156465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.1532156465
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1340248577
Short name T64
Test name
Test status
Simulation time 2450705730 ps
CPU time 8.27 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:28:13 PM PDT 24
Peak memory 201200 kb
Host smart-d96cd780-104c-4257-841f-cfaca15b3529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340248577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.1340248577
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.4176712766
Short name T183
Test name
Test status
Simulation time 2208775542 ps
CPU time 2 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 201160 kb
Host smart-a63aef88-9c97-4ac8-b39e-22213e6546bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176712766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.4176712766
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2180342024
Short name T711
Test name
Test status
Simulation time 2594790201 ps
CPU time 1.37 seconds
Started Mar 14 01:28:09 PM PDT 24
Finished Mar 14 01:28:10 PM PDT 24
Peak memory 201268 kb
Host smart-e0093bfc-a8ba-43a4-b9fd-8c25e8562578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180342024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.2180342024
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.384145197
Short name T148
Test name
Test status
Simulation time 2114292076 ps
CPU time 6.31 seconds
Started Mar 14 01:28:09 PM PDT 24
Finished Mar 14 01:28:15 PM PDT 24
Peak memory 201132 kb
Host smart-7bfef788-a425-4522-9493-8b3430e6093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384145197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.384145197
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.2098846721
Short name T790
Test name
Test status
Simulation time 8556100130 ps
CPU time 6.26 seconds
Started Mar 14 01:28:10 PM PDT 24
Finished Mar 14 01:28:16 PM PDT 24
Peak memory 201208 kb
Host smart-98ce8052-0ed2-4e6c-8325-8bf2a14d12a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098846721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.2098846721
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.989107177
Short name T60
Test name
Test status
Simulation time 206668846660 ps
CPU time 98.39 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:29:43 PM PDT 24
Peak memory 209804 kb
Host smart-9ed27c42-9144-4a47-81a5-76b6c27bc39f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989107177 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.989107177
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2163376269
Short name T750
Test name
Test status
Simulation time 3678344768 ps
CPU time 7.02 seconds
Started Mar 14 01:28:04 PM PDT 24
Finished Mar 14 01:28:11 PM PDT 24
Peak memory 201212 kb
Host smart-1b91f2b8-f8d5-4090-9f92-5144213b4186
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163376269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.2163376269
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1625226024
Short name T95
Test name
Test status
Simulation time 25358472014 ps
CPU time 15.84 seconds
Started Mar 14 01:30:00 PM PDT 24
Finished Mar 14 01:30:16 PM PDT 24
Peak memory 201504 kb
Host smart-bc2a2d73-02db-4b5c-8d08-7a5c998f3207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625226024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.1625226024
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1749985599
Short name T374
Test name
Test status
Simulation time 114241912913 ps
CPU time 17.09 seconds
Started Mar 14 01:30:07 PM PDT 24
Finished Mar 14 01:30:25 PM PDT 24
Peak memory 201436 kb
Host smart-7e649549-00a5-43b5-8444-b797309a08fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749985599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.1749985599
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.627426077
Short name T89
Test name
Test status
Simulation time 26828088710 ps
CPU time 67.49 seconds
Started Mar 14 01:30:03 PM PDT 24
Finished Mar 14 01:31:10 PM PDT 24
Peak memory 201460 kb
Host smart-93e092dd-1565-49b1-b138-25b5fbaff852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627426077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_wi
th_pre_cond.627426077
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.3104284197
Short name T544
Test name
Test status
Simulation time 64495724297 ps
CPU time 88.67 seconds
Started Mar 14 01:30:03 PM PDT 24
Finished Mar 14 01:31:32 PM PDT 24
Peak memory 201468 kb
Host smart-27bcb10a-280f-4d9c-8c1a-d9811e071d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104284197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.3104284197
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3745273228
Short name T166
Test name
Test status
Simulation time 48104137062 ps
CPU time 13.68 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:30:15 PM PDT 24
Peak memory 201456 kb
Host smart-628ba405-2444-4fef-b138-9f9cb61b0a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745273228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.3745273228
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1614403004
Short name T713
Test name
Test status
Simulation time 68202943729 ps
CPU time 34.24 seconds
Started Mar 14 01:30:09 PM PDT 24
Finished Mar 14 01:30:44 PM PDT 24
Peak memory 201500 kb
Host smart-e928e56b-002f-4710-b709-37c0b01b482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614403004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.1614403004
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3413658837
Short name T81
Test name
Test status
Simulation time 71438237675 ps
CPU time 179.66 seconds
Started Mar 14 01:30:03 PM PDT 24
Finished Mar 14 01:33:03 PM PDT 24
Peak memory 201440 kb
Host smart-03b7e4ab-2029-4b65-bb6a-3ee97e322c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413658837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.3413658837
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.4177490582
Short name T774
Test name
Test status
Simulation time 2012909568 ps
CPU time 5.78 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:25 PM PDT 24
Peak memory 201240 kb
Host smart-fb768589-b2f4-44a4-8fad-04b3a6cd2623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177490582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.4177490582
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.4207439871
Short name T456
Test name
Test status
Simulation time 110590923077 ps
CPU time 49.07 seconds
Started Mar 14 01:28:05 PM PDT 24
Finished Mar 14 01:28:54 PM PDT 24
Peak memory 201272 kb
Host smart-0c5fe486-7ec2-4a71-a071-fdb37b40f8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207439871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.4207439871
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.1299543902
Short name T247
Test name
Test status
Simulation time 127364109795 ps
CPU time 348.03 seconds
Started Mar 14 01:28:16 PM PDT 24
Finished Mar 14 01:34:04 PM PDT 24
Peak memory 201328 kb
Host smart-5558beb3-2e8d-40e6-abbb-303c90c2b9ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299543902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.1299543902
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.756883551
Short name T382
Test name
Test status
Simulation time 95996254515 ps
CPU time 115.16 seconds
Started Mar 14 01:28:10 PM PDT 24
Finished Mar 14 01:30:05 PM PDT 24
Peak memory 201520 kb
Host smart-a83fb47c-6aab-49b2-81d6-854597992312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756883551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wit
h_pre_cond.756883551
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1268704266
Short name T475
Test name
Test status
Simulation time 4785237112 ps
CPU time 8.86 seconds
Started Mar 14 01:28:10 PM PDT 24
Finished Mar 14 01:28:19 PM PDT 24
Peak memory 201192 kb
Host smart-9d3f9455-453d-4066-886c-093ce7f5ded5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268704266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.1268704266
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3750374192
Short name T39
Test name
Test status
Simulation time 4189017473 ps
CPU time 8.5 seconds
Started Mar 14 01:28:09 PM PDT 24
Finished Mar 14 01:28:17 PM PDT 24
Peak memory 201224 kb
Host smart-24375910-9756-46f4-8f9a-e5f9a556cfd0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750374192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.3750374192
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2967399629
Short name T459
Test name
Test status
Simulation time 2627294308 ps
CPU time 2.74 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:09 PM PDT 24
Peak memory 201184 kb
Host smart-6438120a-eb36-4db8-8152-26fdfef900ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967399629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.2967399629
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.4157182088
Short name T29
Test name
Test status
Simulation time 2465654552 ps
CPU time 7.06 seconds
Started Mar 14 01:28:09 PM PDT 24
Finished Mar 14 01:28:16 PM PDT 24
Peak memory 201204 kb
Host smart-b142f982-7a7c-4a68-a83d-1eb6142b2d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157182088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.4157182088
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.321738391
Short name T172
Test name
Test status
Simulation time 2129743600 ps
CPU time 3.54 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:28:11 PM PDT 24
Peak memory 201092 kb
Host smart-ee3d7e6b-9b4e-4d4d-b167-4cdb8c365602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321738391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.321738391
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1383997038
Short name T708
Test name
Test status
Simulation time 2516448404 ps
CPU time 4.12 seconds
Started Mar 14 01:28:03 PM PDT 24
Finished Mar 14 01:28:07 PM PDT 24
Peak memory 201256 kb
Host smart-64bf617d-2461-4bd6-ace3-8110cbb98a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383997038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1383997038
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.3695494159
Short name T743
Test name
Test status
Simulation time 2111300458 ps
CPU time 6.2 seconds
Started Mar 14 01:28:05 PM PDT 24
Finished Mar 14 01:28:12 PM PDT 24
Peak memory 201108 kb
Host smart-073b8b8c-630d-4355-bcd3-58e855029b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695494159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.3695494159
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.1538265427
Short name T106
Test name
Test status
Simulation time 14102370254 ps
CPU time 11.85 seconds
Started Mar 14 01:28:07 PM PDT 24
Finished Mar 14 01:28:19 PM PDT 24
Peak memory 201452 kb
Host smart-75466f04-4708-4e36-8f34-d7541c2a3e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538265427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.1538265427
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.2062700688
Short name T639
Test name
Test status
Simulation time 3391023080 ps
CPU time 3.43 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:10 PM PDT 24
Peak memory 201204 kb
Host smart-f28f1372-969a-4ba0-a6f0-57c9fe2c4ecf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062700688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.2062700688
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2115329303
Short name T468
Test name
Test status
Simulation time 52118388482 ps
CPU time 139.76 seconds
Started Mar 14 01:30:05 PM PDT 24
Finished Mar 14 01:32:25 PM PDT 24
Peak memory 201504 kb
Host smart-973d41a4-3074-45ee-891b-a4619efd7d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115329303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.2115329303
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1309034752
Short name T220
Test name
Test status
Simulation time 27581002485 ps
CPU time 38.09 seconds
Started Mar 14 01:30:02 PM PDT 24
Finished Mar 14 01:30:40 PM PDT 24
Peak memory 201504 kb
Host smart-7745dd67-42f8-46ea-8f44-401ba484fc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309034752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.1309034752
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.554555664
Short name T487
Test name
Test status
Simulation time 32051476639 ps
CPU time 79.24 seconds
Started Mar 14 01:30:09 PM PDT 24
Finished Mar 14 01:31:29 PM PDT 24
Peak memory 201392 kb
Host smart-c6dcaa9a-69cf-4f90-a390-ebffb6d34b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554555664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_wi
th_pre_cond.554555664
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3600842544
Short name T780
Test name
Test status
Simulation time 23834985127 ps
CPU time 47.18 seconds
Started Mar 14 01:30:03 PM PDT 24
Finished Mar 14 01:30:50 PM PDT 24
Peak memory 201520 kb
Host smart-a5f57a51-ed67-4523-b692-523944bdf6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600842544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.3600842544
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.826310788
Short name T498
Test name
Test status
Simulation time 47397317242 ps
CPU time 103.69 seconds
Started Mar 14 01:30:09 PM PDT 24
Finished Mar 14 01:31:54 PM PDT 24
Peak memory 201472 kb
Host smart-b44f0770-d857-4650-bbfd-c27ff2946314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826310788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_wi
th_pre_cond.826310788
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.261192664
Short name T240
Test name
Test status
Simulation time 22092307566 ps
CPU time 29.08 seconds
Started Mar 14 01:30:00 PM PDT 24
Finished Mar 14 01:30:29 PM PDT 24
Peak memory 201512 kb
Host smart-97e7134f-826d-41f9-8101-aeb964abae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261192664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_wi
th_pre_cond.261192664
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.535769349
Short name T180
Test name
Test status
Simulation time 104483296410 ps
CPU time 74.49 seconds
Started Mar 14 01:30:05 PM PDT 24
Finished Mar 14 01:31:19 PM PDT 24
Peak memory 201472 kb
Host smart-a6495ef9-8aec-4603-9669-8b749641f14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535769349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_wi
th_pre_cond.535769349
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.978687996
Short name T510
Test name
Test status
Simulation time 24612317324 ps
CPU time 16.34 seconds
Started Mar 14 01:30:08 PM PDT 24
Finished Mar 14 01:30:25 PM PDT 24
Peak memory 201516 kb
Host smart-dc485e85-b078-4cfb-abce-3e3ec51497c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978687996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_wi
th_pre_cond.978687996
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3190534411
Short name T554
Test name
Test status
Simulation time 56385820484 ps
CPU time 149.79 seconds
Started Mar 14 01:30:08 PM PDT 24
Finished Mar 14 01:32:38 PM PDT 24
Peak memory 201476 kb
Host smart-567e1a25-8ce5-45a6-839b-ab320de3d116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190534411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3190534411
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.1360870417
Short name T631
Test name
Test status
Simulation time 2058898278 ps
CPU time 1.24 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:21 PM PDT 24
Peak memory 201264 kb
Host smart-3c38cd96-1ebf-4485-b58c-30b4f46ef57a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360870417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.1360870417
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2123392815
Short name T402
Test name
Test status
Simulation time 37865788125 ps
CPU time 26.08 seconds
Started Mar 14 01:28:15 PM PDT 24
Finished Mar 14 01:28:41 PM PDT 24
Peak memory 201232 kb
Host smart-fa16da60-fbb8-4a8c-ab4b-19c6a377edbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123392815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.2123392815
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3960750329
Short name T362
Test name
Test status
Simulation time 153427311891 ps
CPU time 411.59 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:35:10 PM PDT 24
Peak memory 201384 kb
Host smart-434ed088-158d-4352-a1ef-483e141fdb2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960750329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3960750329
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1288579221
Short name T85
Test name
Test status
Simulation time 85932588951 ps
CPU time 63.63 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:29:23 PM PDT 24
Peak memory 201512 kb
Host smart-c1a93135-4fbc-4487-8933-8c6b8007c646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288579221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.1288579221
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3476428224
Short name T660
Test name
Test status
Simulation time 2909410332 ps
CPU time 2.59 seconds
Started Mar 14 01:28:09 PM PDT 24
Finished Mar 14 01:28:11 PM PDT 24
Peak memory 201212 kb
Host smart-7fc7cb94-b89f-4aa7-abe0-42eaf751d43a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476428224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.3476428224
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.1518778704
Short name T187
Test name
Test status
Simulation time 3210162905 ps
CPU time 6.76 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:26 PM PDT 24
Peak memory 201212 kb
Host smart-009430e1-9e63-4418-a919-1b08896e7ddd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518778704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.1518778704
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.850942387
Short name T54
Test name
Test status
Simulation time 2621098123 ps
CPU time 3.08 seconds
Started Mar 14 01:28:16 PM PDT 24
Finished Mar 14 01:28:19 PM PDT 24
Peak memory 201176 kb
Host smart-53feb616-1c43-4f57-839e-2190075c8d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850942387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.850942387
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3740953293
Short name T721
Test name
Test status
Simulation time 2495243846 ps
CPU time 1.78 seconds
Started Mar 14 01:28:06 PM PDT 24
Finished Mar 14 01:28:08 PM PDT 24
Peak memory 201244 kb
Host smart-f8826015-4ace-4f1b-9f84-cbf206808859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740953293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3740953293
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.968493819
Short name T410
Test name
Test status
Simulation time 2228921848 ps
CPU time 6.72 seconds
Started Mar 14 01:28:16 PM PDT 24
Finished Mar 14 01:28:22 PM PDT 24
Peak memory 201140 kb
Host smart-53f117b4-0494-497c-9f1f-021f4b2cb771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968493819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.968493819
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2120099756
Short name T446
Test name
Test status
Simulation time 2530315364 ps
CPU time 2.28 seconds
Started Mar 14 01:28:16 PM PDT 24
Finished Mar 14 01:28:19 PM PDT 24
Peak memory 201244 kb
Host smart-df82bbdb-ded2-4ff5-a8ff-a048a995bd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120099756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2120099756
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.902907034
Short name T235
Test name
Test status
Simulation time 2135878700 ps
CPU time 1.91 seconds
Started Mar 14 01:28:11 PM PDT 24
Finished Mar 14 01:28:13 PM PDT 24
Peak memory 201136 kb
Host smart-b46ab816-81bd-4396-bb42-48c0ab8785a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902907034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.902907034
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.2489859501
Short name T723
Test name
Test status
Simulation time 8420628188 ps
CPU time 19.51 seconds
Started Mar 14 01:28:15 PM PDT 24
Finished Mar 14 01:28:35 PM PDT 24
Peak memory 201160 kb
Host smart-c644023a-ae20-4445-b785-32c811009cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489859501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.2489859501
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1289986826
Short name T746
Test name
Test status
Simulation time 50276567030 ps
CPU time 17.17 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:36 PM PDT 24
Peak memory 217900 kb
Host smart-0518dbee-380e-4958-b01e-5a48ff3ad568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289986826 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1289986826
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2162080555
Short name T122
Test name
Test status
Simulation time 9900272009 ps
CPU time 9.78 seconds
Started Mar 14 01:28:19 PM PDT 24
Finished Mar 14 01:28:29 PM PDT 24
Peak memory 201216 kb
Host smart-11413301-1aa0-4b8d-9a1e-3286362fc597
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162080555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.2162080555
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.515838431
Short name T12
Test name
Test status
Simulation time 118443151156 ps
CPU time 79.53 seconds
Started Mar 14 01:30:08 PM PDT 24
Finished Mar 14 01:31:28 PM PDT 24
Peak memory 201528 kb
Host smart-247efc77-f73a-41f4-9bd6-ca9c12c6dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515838431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_wi
th_pre_cond.515838431
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1618458959
Short name T286
Test name
Test status
Simulation time 101180737789 ps
CPU time 65 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:31:19 PM PDT 24
Peak memory 201520 kb
Host smart-313a0c59-fe69-4bf4-bd5c-de48d88a7b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618458959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.1618458959
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1658608808
Short name T381
Test name
Test status
Simulation time 61432838764 ps
CPU time 39.36 seconds
Started Mar 14 01:30:13 PM PDT 24
Finished Mar 14 01:30:52 PM PDT 24
Peak memory 201472 kb
Host smart-228359fa-48d8-498f-b5a0-437d6863c904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658608808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.1658608808
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.4030488739
Short name T257
Test name
Test status
Simulation time 85195249999 ps
CPU time 238.34 seconds
Started Mar 14 01:30:13 PM PDT 24
Finished Mar 14 01:34:11 PM PDT 24
Peak memory 201432 kb
Host smart-b93fb883-9865-4857-a321-75b84c77575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030488739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.4030488739
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3472950171
Short name T309
Test name
Test status
Simulation time 63536510167 ps
CPU time 88.47 seconds
Started Mar 14 01:30:13 PM PDT 24
Finished Mar 14 01:31:41 PM PDT 24
Peak memory 201436 kb
Host smart-61ffee4d-5888-44f2-991f-365147f3d780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472950171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.3472950171
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1968463096
Short name T694
Test name
Test status
Simulation time 36854190055 ps
CPU time 26.22 seconds
Started Mar 14 01:30:14 PM PDT 24
Finished Mar 14 01:30:41 PM PDT 24
Peak memory 201512 kb
Host smart-bac66423-bbbc-47af-85a5-89874d1b7d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968463096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.1968463096
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1726230885
Short name T478
Test name
Test status
Simulation time 39500306934 ps
CPU time 6.87 seconds
Started Mar 14 01:30:13 PM PDT 24
Finished Mar 14 01:30:20 PM PDT 24
Peak memory 201412 kb
Host smart-8ebe4ed6-9c96-4459-ab65-3e89851a8cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726230885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.1726230885
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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