| T123 |
/workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2330652068 |
|
|
Mar 28 12:55:32 PM PDT 24 |
Mar 28 12:55:39 PM PDT 24 |
9100223527 ps |
| T467 |
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2868006755 |
|
|
Mar 28 12:56:20 PM PDT 24 |
Mar 28 12:56:29 PM PDT 24 |
3048312101 ps |
| T394 |
/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.596348190 |
|
|
Mar 28 12:55:12 PM PDT 24 |
Mar 28 12:58:21 PM PDT 24 |
66721011747 ps |
| T83 |
/workspace/coverage/default/11.sysrst_ctrl_stress_all.2765252670 |
|
|
Mar 28 12:55:09 PM PDT 24 |
Mar 28 12:57:15 PM PDT 24 |
51752938961 ps |
| T208 |
/workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1870563511 |
|
|
Mar 28 12:56:08 PM PDT 24 |
Mar 28 12:56:12 PM PDT 24 |
2615249388 ps |
| T209 |
/workspace/coverage/default/28.sysrst_ctrl_stress_all.3215831199 |
|
|
Mar 28 12:55:51 PM PDT 24 |
Mar 28 12:56:21 PM PDT 24 |
11913611607 ps |
| T210 |
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3579918896 |
|
|
Mar 28 12:56:39 PM PDT 24 |
Mar 28 12:56:42 PM PDT 24 |
2931168196 ps |
| T211 |
/workspace/coverage/default/43.sysrst_ctrl_smoke.4139626027 |
|
|
Mar 28 12:56:23 PM PDT 24 |
Mar 28 12:56:25 PM PDT 24 |
2128803397 ps |
| T212 |
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3875144298 |
|
|
Mar 28 12:55:03 PM PDT 24 |
Mar 28 12:55:06 PM PDT 24 |
2483098405 ps |
| T213 |
/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1731196297 |
|
|
Mar 28 12:56:06 PM PDT 24 |
Mar 28 12:56:14 PM PDT 24 |
2510939982 ps |
| T214 |
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.386852439 |
|
|
Mar 28 12:56:15 PM PDT 24 |
Mar 28 12:56:20 PM PDT 24 |
2449216083 ps |
| T215 |
/workspace/coverage/default/39.sysrst_ctrl_combo_detect.1087994024 |
|
|
Mar 28 12:56:13 PM PDT 24 |
Mar 28 01:00:29 PM PDT 24 |
98619190898 ps |
| T216 |
/workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3710708563 |
|
|
Mar 28 12:56:04 PM PDT 24 |
Mar 28 12:56:11 PM PDT 24 |
2512467969 ps |
| T468 |
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.259547353 |
|
|
Mar 28 12:54:57 PM PDT 24 |
Mar 28 12:55:07 PM PDT 24 |
3330182472 ps |
| T124 |
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.959140796 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:11 PM PDT 24 |
5332903138 ps |
| T469 |
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1551856734 |
|
|
Mar 28 12:55:09 PM PDT 24 |
Mar 28 12:56:15 PM PDT 24 |
24831293034 ps |
| T470 |
/workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.399889138 |
|
|
Mar 28 12:55:49 PM PDT 24 |
Mar 28 12:55:56 PM PDT 24 |
2463303450 ps |
| T360 |
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3134819334 |
|
|
Mar 28 12:57:06 PM PDT 24 |
Mar 28 01:00:06 PM PDT 24 |
67489610242 ps |
| T471 |
/workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4048788379 |
|
|
Mar 28 12:55:49 PM PDT 24 |
Mar 28 12:55:56 PM PDT 24 |
3299452541 ps |
| T296 |
/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3234653459 |
|
|
Mar 28 12:56:09 PM PDT 24 |
Mar 28 12:56:13 PM PDT 24 |
3267991811 ps |
| T100 |
/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1396379863 |
|
|
Mar 28 12:54:50 PM PDT 24 |
Mar 28 12:55:52 PM PDT 24 |
431862425890 ps |
| T472 |
/workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1055097067 |
|
|
Mar 28 12:55:23 PM PDT 24 |
Mar 28 12:55:31 PM PDT 24 |
2612881296 ps |
| T202 |
/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2157976153 |
|
|
Mar 28 12:56:04 PM PDT 24 |
Mar 28 12:57:55 PM PDT 24 |
41586874774 ps |
| T473 |
/workspace/coverage/default/38.sysrst_ctrl_alert_test.3740293044 |
|
|
Mar 28 12:56:13 PM PDT 24 |
Mar 28 12:56:16 PM PDT 24 |
2035951500 ps |
| T257 |
/workspace/coverage/default/12.sysrst_ctrl_combo_detect.3214006643 |
|
|
Mar 28 12:55:17 PM PDT 24 |
Mar 28 12:56:22 PM PDT 24 |
46252830189 ps |
| T398 |
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3052662685 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 01:04:34 PM PDT 24 |
178928364701 ps |
| T405 |
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.4136697635 |
|
|
Mar 28 12:57:02 PM PDT 24 |
Mar 28 12:59:31 PM PDT 24 |
52801031009 ps |
| T203 |
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2655965992 |
|
|
Mar 28 12:55:10 PM PDT 24 |
Mar 28 12:55:13 PM PDT 24 |
4133482585 ps |
| T369 |
/workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.477672343 |
|
|
Mar 28 12:55:20 PM PDT 24 |
Mar 28 12:55:38 PM PDT 24 |
110473206631 ps |
| T474 |
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1004952196 |
|
|
Mar 28 12:55:07 PM PDT 24 |
Mar 28 12:55:17 PM PDT 24 |
3595268359 ps |
| T475 |
/workspace/coverage/default/41.sysrst_ctrl_alert_test.3783661195 |
|
|
Mar 28 12:56:25 PM PDT 24 |
Mar 28 12:56:27 PM PDT 24 |
2030254415 ps |
| T476 |
/workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3834293650 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:55:52 PM PDT 24 |
2621049133 ps |
| T477 |
/workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.85063239 |
|
|
Mar 28 12:55:49 PM PDT 24 |
Mar 28 12:55:54 PM PDT 24 |
4999937587 ps |
| T266 |
/workspace/coverage/default/38.sysrst_ctrl_stress_all.809712728 |
|
|
Mar 28 12:56:12 PM PDT 24 |
Mar 28 12:58:10 PM PDT 24 |
88750576908 ps |
| T478 |
/workspace/coverage/default/9.sysrst_ctrl_smoke.2164322758 |
|
|
Mar 28 12:55:06 PM PDT 24 |
Mar 28 12:55:25 PM PDT 24 |
2115149531 ps |
| T178 |
/workspace/coverage/default/30.sysrst_ctrl_stress_all.3387104948 |
|
|
Mar 28 12:55:59 PM PDT 24 |
Mar 28 12:57:15 PM PDT 24 |
323429475936 ps |
| T179 |
/workspace/coverage/default/4.sysrst_ctrl_stress_all.2019047777 |
|
|
Mar 28 12:55:08 PM PDT 24 |
Mar 28 01:12:36 PM PDT 24 |
505861279712 ps |
| T479 |
/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2071024718 |
|
|
Mar 28 12:56:04 PM PDT 24 |
Mar 28 12:56:06 PM PDT 24 |
2530307289 ps |
| T159 |
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2507577384 |
|
|
Mar 28 12:57:05 PM PDT 24 |
Mar 28 12:57:18 PM PDT 24 |
5493543764 ps |
| T180 |
/workspace/coverage/default/39.sysrst_ctrl_edge_detect.3809268337 |
|
|
Mar 28 12:56:25 PM PDT 24 |
Mar 28 12:56:33 PM PDT 24 |
2866982698 ps |
| T480 |
/workspace/coverage/default/27.sysrst_ctrl_pin_override_test.962651247 |
|
|
Mar 28 12:55:54 PM PDT 24 |
Mar 28 12:55:56 PM PDT 24 |
2528005580 ps |
| T481 |
/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1926663878 |
|
|
Mar 28 12:55:18 PM PDT 24 |
Mar 28 12:55:25 PM PDT 24 |
2610735706 ps |
| T482 |
/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3782504408 |
|
|
Mar 28 12:55:51 PM PDT 24 |
Mar 28 12:55:58 PM PDT 24 |
9471248744 ps |
| T205 |
/workspace/coverage/default/10.sysrst_ctrl_edge_detect.2719339873 |
|
|
Mar 28 12:55:04 PM PDT 24 |
Mar 28 12:55:07 PM PDT 24 |
5812835003 ps |
| T483 |
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1819378454 |
|
|
Mar 28 12:56:24 PM PDT 24 |
Mar 28 12:56:26 PM PDT 24 |
2176507577 ps |
| T484 |
/workspace/coverage/default/19.sysrst_ctrl_alert_test.1060789909 |
|
|
Mar 28 12:55:37 PM PDT 24 |
Mar 28 12:55:41 PM PDT 24 |
2015296434 ps |
| T485 |
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1837051026 |
|
|
Mar 28 12:55:02 PM PDT 24 |
Mar 28 12:57:23 PM PDT 24 |
59736096743 ps |
| T217 |
/workspace/coverage/default/37.sysrst_ctrl_stress_all.1181835895 |
|
|
Mar 28 12:56:07 PM PDT 24 |
Mar 28 02:37:05 PM PDT 24 |
2519056667722 ps |
| T126 |
/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2940688039 |
|
|
Mar 28 12:56:05 PM PDT 24 |
Mar 28 12:57:13 PM PDT 24 |
111297517867 ps |
| T486 |
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.219771126 |
|
|
Mar 28 12:55:09 PM PDT 24 |
Mar 28 12:55:16 PM PDT 24 |
2220691388 ps |
| T487 |
/workspace/coverage/default/22.sysrst_ctrl_edge_detect.1915185667 |
|
|
Mar 28 12:55:49 PM PDT 24 |
Mar 28 12:55:51 PM PDT 24 |
3527909089 ps |
| T383 |
/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2669042300 |
|
|
Mar 28 12:54:45 PM PDT 24 |
Mar 28 12:56:25 PM PDT 24 |
154780133410 ps |
| T488 |
/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.163940081 |
|
|
Mar 28 12:55:15 PM PDT 24 |
Mar 28 12:55:23 PM PDT 24 |
2475304877 ps |
| T489 |
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1800677636 |
|
|
Mar 28 12:56:25 PM PDT 24 |
Mar 28 12:56:32 PM PDT 24 |
2206902207 ps |
| T490 |
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3374036485 |
|
|
Mar 28 12:57:09 PM PDT 24 |
Mar 28 12:57:47 PM PDT 24 |
55929424482 ps |
| T491 |
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1476001625 |
|
|
Mar 28 12:55:05 PM PDT 24 |
Mar 28 12:55:06 PM PDT 24 |
2179290104 ps |
| T492 |
/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1415104015 |
|
|
Mar 28 12:55:51 PM PDT 24 |
Mar 28 12:55:57 PM PDT 24 |
2086512031 ps |
| T493 |
/workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3529340044 |
|
|
Mar 28 12:55:48 PM PDT 24 |
Mar 28 12:55:55 PM PDT 24 |
2419957905 ps |
| T365 |
/workspace/coverage/default/14.sysrst_ctrl_combo_detect.1685996392 |
|
|
Mar 28 12:55:12 PM PDT 24 |
Mar 28 12:55:36 PM PDT 24 |
33697394369 ps |
| T189 |
/workspace/coverage/default/27.sysrst_ctrl_edge_detect.1103631750 |
|
|
Mar 28 12:55:55 PM PDT 24 |
Mar 28 12:55:57 PM PDT 24 |
3307159388 ps |
| T494 |
/workspace/coverage/default/3.sysrst_ctrl_smoke.864974952 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
2135228940 ps |
| T495 |
/workspace/coverage/default/20.sysrst_ctrl_smoke.2057561756 |
|
|
Mar 28 12:55:37 PM PDT 24 |
Mar 28 12:55:44 PM PDT 24 |
2113814609 ps |
| T496 |
/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3699832981 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:56 PM PDT 24 |
2607363474 ps |
| T497 |
/workspace/coverage/default/28.sysrst_ctrl_alert_test.601155267 |
|
|
Mar 28 12:55:49 PM PDT 24 |
Mar 28 12:55:55 PM PDT 24 |
2008883688 ps |
| T498 |
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3677112514 |
|
|
Mar 28 12:55:03 PM PDT 24 |
Mar 28 12:55:06 PM PDT 24 |
2151034017 ps |
| T499 |
/workspace/coverage/default/25.sysrst_ctrl_alert_test.2265997714 |
|
|
Mar 28 12:55:51 PM PDT 24 |
Mar 28 12:55:53 PM PDT 24 |
2124798048 ps |
| T137 |
/workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.424922996 |
|
|
Mar 28 12:56:08 PM PDT 24 |
Mar 28 12:56:13 PM PDT 24 |
9056079089 ps |
| T325 |
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1838599483 |
|
|
Mar 28 12:55:09 PM PDT 24 |
Mar 28 12:55:12 PM PDT 24 |
6619472899 ps |
| T500 |
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3796366541 |
|
|
Mar 28 12:55:03 PM PDT 24 |
Mar 28 12:55:06 PM PDT 24 |
2394590701 ps |
| T501 |
/workspace/coverage/default/25.sysrst_ctrl_stress_all.3810615589 |
|
|
Mar 28 12:55:51 PM PDT 24 |
Mar 28 12:56:06 PM PDT 24 |
10470548756 ps |
| T164 |
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.525005425 |
|
|
Mar 28 12:57:02 PM PDT 24 |
Mar 28 12:57:37 PM PDT 24 |
283599738290 ps |
| T502 |
/workspace/coverage/default/2.sysrst_ctrl_alert_test.1639058698 |
|
|
Mar 28 12:54:54 PM PDT 24 |
Mar 28 12:55:00 PM PDT 24 |
2015454210 ps |
| T399 |
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2465529975 |
|
|
Mar 28 12:55:06 PM PDT 24 |
Mar 28 01:01:02 PM PDT 24 |
142076399667 ps |
| T503 |
/workspace/coverage/default/22.sysrst_ctrl_alert_test.2393596212 |
|
|
Mar 28 12:55:49 PM PDT 24 |
Mar 28 12:55:52 PM PDT 24 |
2022818243 ps |
| T504 |
/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3977494735 |
|
|
Mar 28 12:55:35 PM PDT 24 |
Mar 28 12:55:38 PM PDT 24 |
2532277840 ps |
| T505 |
/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4226223905 |
|
|
Mar 28 12:56:08 PM PDT 24 |
Mar 28 12:57:18 PM PDT 24 |
24829151303 ps |
| T506 |
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3936237038 |
|
|
Mar 28 12:55:07 PM PDT 24 |
Mar 28 12:55:09 PM PDT 24 |
2181667756 ps |
| T507 |
/workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1327139713 |
|
|
Mar 28 12:55:17 PM PDT 24 |
Mar 28 12:55:19 PM PDT 24 |
2625501614 ps |
| T508 |
/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.3467031660 |
|
|
Mar 28 12:56:01 PM PDT 24 |
Mar 28 12:56:08 PM PDT 24 |
2460407456 ps |
| T509 |
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2020140525 |
|
|
Mar 28 12:56:25 PM PDT 24 |
Mar 28 12:56:33 PM PDT 24 |
2510310551 ps |
| T510 |
/workspace/coverage/default/42.sysrst_ctrl_alert_test.2393037018 |
|
|
Mar 28 12:56:24 PM PDT 24 |
Mar 28 12:56:30 PM PDT 24 |
2013741453 ps |
| T377 |
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.382598572 |
|
|
Mar 28 12:56:40 PM PDT 24 |
Mar 28 12:57:52 PM PDT 24 |
71785886963 ps |
| T165 |
/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.313140537 |
|
|
Mar 28 12:55:12 PM PDT 24 |
Mar 28 12:56:21 PM PDT 24 |
127775214379 ps |
| T392 |
/workspace/coverage/default/13.sysrst_ctrl_stress_all.2943736088 |
|
|
Mar 28 12:55:13 PM PDT 24 |
Mar 28 01:04:44 PM PDT 24 |
208016530861 ps |
| T364 |
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3685296657 |
|
|
Mar 28 12:55:04 PM PDT 24 |
Mar 28 12:58:19 PM PDT 24 |
640493475775 ps |
| T511 |
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3493709334 |
|
|
Mar 28 12:56:17 PM PDT 24 |
Mar 28 12:56:24 PM PDT 24 |
2154555782 ps |
| T267 |
/workspace/coverage/default/27.sysrst_ctrl_combo_detect.191044268 |
|
|
Mar 28 12:55:54 PM PDT 24 |
Mar 28 12:57:58 PM PDT 24 |
108968790740 ps |
| T512 |
/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3158195364 |
|
|
Mar 28 12:54:43 PM PDT 24 |
Mar 28 12:54:50 PM PDT 24 |
4390450378 ps |
| T513 |
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2876591195 |
|
|
Mar 28 12:56:19 PM PDT 24 |
Mar 28 12:56:21 PM PDT 24 |
2029237972 ps |
| T514 |
/workspace/coverage/default/29.sysrst_ctrl_edge_detect.337003360 |
|
|
Mar 28 12:55:48 PM PDT 24 |
Mar 28 12:55:51 PM PDT 24 |
3034134852 ps |
| T515 |
/workspace/coverage/default/16.sysrst_ctrl_edge_detect.3156047427 |
|
|
Mar 28 12:55:24 PM PDT 24 |
Mar 28 12:55:27 PM PDT 24 |
3414841477 ps |
| T516 |
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3645489930 |
|
|
Mar 28 12:56:31 PM PDT 24 |
Mar 28 12:56:34 PM PDT 24 |
3044007058 ps |
| T517 |
/workspace/coverage/default/40.sysrst_ctrl_alert_test.2194113098 |
|
|
Mar 28 12:56:17 PM PDT 24 |
Mar 28 12:56:23 PM PDT 24 |
2011584171 ps |
| T518 |
/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1572420836 |
|
|
Mar 28 12:56:08 PM PDT 24 |
Mar 28 12:56:14 PM PDT 24 |
2153647777 ps |
| T519 |
/workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.576887844 |
|
|
Mar 28 12:55:24 PM PDT 24 |
Mar 28 12:55:32 PM PDT 24 |
30924354412 ps |
| T520 |
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1805658971 |
|
|
Mar 28 12:57:04 PM PDT 24 |
Mar 28 12:57:06 PM PDT 24 |
2549896948 ps |
| T521 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1491760709 |
|
|
Mar 28 12:54:52 PM PDT 24 |
Mar 28 12:54:59 PM PDT 24 |
2430433110 ps |
| T274 |
/workspace/coverage/default/0.sysrst_ctrl_sec_cm.1114273454 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:55:50 PM PDT 24 |
22011803799 ps |
| T522 |
/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3466180719 |
|
|
Mar 28 12:55:12 PM PDT 24 |
Mar 28 12:55:20 PM PDT 24 |
2463671381 ps |
| T523 |
/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.485753008 |
|
|
Mar 28 12:55:36 PM PDT 24 |
Mar 28 12:56:55 PM PDT 24 |
28581864007 ps |
| T388 |
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.813670269 |
|
|
Mar 28 12:57:06 PM PDT 24 |
Mar 28 01:02:20 PM PDT 24 |
122525965305 ps |
| T524 |
/workspace/coverage/default/25.sysrst_ctrl_pin_access_test.4171450576 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:55:54 PM PDT 24 |
2063123030 ps |
| T525 |
/workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3485672648 |
|
|
Mar 28 12:56:01 PM PDT 24 |
Mar 28 12:56:05 PM PDT 24 |
4488577434 ps |
| T526 |
/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2049598767 |
|
|
Mar 28 12:55:54 PM PDT 24 |
Mar 28 12:56:02 PM PDT 24 |
2509160962 ps |
| T527 |
/workspace/coverage/default/17.sysrst_ctrl_smoke.128549463 |
|
|
Mar 28 12:55:31 PM PDT 24 |
Mar 28 12:55:35 PM PDT 24 |
2119236593 ps |
| T380 |
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2826359065 |
|
|
Mar 28 12:57:06 PM PDT 24 |
Mar 28 12:59:00 PM PDT 24 |
86505760579 ps |
| T77 |
/workspace/coverage/default/0.sysrst_ctrl_feature_disable.2149303667 |
|
|
Mar 28 12:55:00 PM PDT 24 |
Mar 28 12:56:34 PM PDT 24 |
34302318225 ps |
| T528 |
/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2926151671 |
|
|
Mar 28 12:55:20 PM PDT 24 |
Mar 28 12:55:22 PM PDT 24 |
3092423837 ps |
| T529 |
/workspace/coverage/default/49.sysrst_ctrl_smoke.3190329995 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:12 PM PDT 24 |
2122060948 ps |
| T530 |
/workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1584427668 |
|
|
Mar 28 12:55:14 PM PDT 24 |
Mar 28 12:55:15 PM PDT 24 |
7614751184 ps |
| T531 |
/workspace/coverage/default/34.sysrst_ctrl_pin_access_test.2953975023 |
|
|
Mar 28 12:56:07 PM PDT 24 |
Mar 28 12:56:10 PM PDT 24 |
2130496502 ps |
| T390 |
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.331185960 |
|
|
Mar 28 12:57:07 PM PDT 24 |
Mar 28 01:00:28 PM PDT 24 |
79346428378 ps |
| T532 |
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3815761170 |
|
|
Mar 28 12:57:06 PM PDT 24 |
Mar 28 12:57:08 PM PDT 24 |
2044868085 ps |
| T78 |
/workspace/coverage/default/34.sysrst_ctrl_edge_detect.1561258582 |
|
|
Mar 28 12:56:03 PM PDT 24 |
Mar 28 12:56:05 PM PDT 24 |
3230996081 ps |
| T168 |
/workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2613225205 |
|
|
Mar 28 12:55:46 PM PDT 24 |
Mar 28 12:56:00 PM PDT 24 |
4754585475 ps |
| T169 |
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.943740472 |
|
|
Mar 28 12:56:23 PM PDT 24 |
Mar 28 12:56:25 PM PDT 24 |
3412034832 ps |
| T170 |
/workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2151893785 |
|
|
Mar 28 12:55:03 PM PDT 24 |
Mar 28 12:55:05 PM PDT 24 |
2664633612 ps |
| T171 |
/workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2966249152 |
|
|
Mar 28 12:56:05 PM PDT 24 |
Mar 28 12:56:12 PM PDT 24 |
2613839552 ps |
| T172 |
/workspace/coverage/default/13.sysrst_ctrl_alert_test.47750769 |
|
|
Mar 28 12:55:19 PM PDT 24 |
Mar 28 12:55:22 PM PDT 24 |
2022552877 ps |
| T173 |
/workspace/coverage/default/16.sysrst_ctrl_pin_override_test.1684198480 |
|
|
Mar 28 12:55:13 PM PDT 24 |
Mar 28 12:55:21 PM PDT 24 |
2507408547 ps |
| T174 |
/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1956144468 |
|
|
Mar 28 12:55:54 PM PDT 24 |
Mar 28 12:56:08 PM PDT 24 |
20015342069 ps |
| T175 |
/workspace/coverage/default/22.sysrst_ctrl_smoke.2394604070 |
|
|
Mar 28 12:55:49 PM PDT 24 |
Mar 28 12:55:55 PM PDT 24 |
2108050081 ps |
| T176 |
/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3390625166 |
|
|
Mar 28 12:55:18 PM PDT 24 |
Mar 28 12:55:25 PM PDT 24 |
2509038812 ps |
| T533 |
/workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1716354336 |
|
|
Mar 28 12:55:54 PM PDT 24 |
Mar 28 12:55:59 PM PDT 24 |
3232044695 ps |
| T534 |
/workspace/coverage/default/11.sysrst_ctrl_pin_access_test.3466975425 |
|
|
Mar 28 12:55:05 PM PDT 24 |
Mar 28 12:55:11 PM PDT 24 |
2049691192 ps |
| T535 |
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3559098435 |
|
|
Mar 28 12:55:06 PM PDT 24 |
Mar 28 12:55:47 PM PDT 24 |
15680514371 ps |
| T536 |
/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.2110901381 |
|
|
Mar 28 12:56:03 PM PDT 24 |
Mar 28 12:56:10 PM PDT 24 |
2157712488 ps |
| T537 |
/workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2499314042 |
|
|
Mar 28 12:55:57 PM PDT 24 |
Mar 28 12:56:06 PM PDT 24 |
3324687232 ps |
| T538 |
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.565132551 |
|
|
Mar 28 12:56:18 PM PDT 24 |
Mar 28 12:56:47 PM PDT 24 |
17644796361 ps |
| T539 |
/workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1574947624 |
|
|
Mar 28 12:55:25 PM PDT 24 |
Mar 28 12:57:13 PM PDT 24 |
310351200612 ps |
| T397 |
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.925500799 |
|
|
Mar 28 12:56:23 PM PDT 24 |
Mar 28 12:56:57 PM PDT 24 |
83560368691 ps |
| T540 |
/workspace/coverage/default/23.sysrst_ctrl_alert_test.1478607209 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:55:54 PM PDT 24 |
2024244313 ps |
| T541 |
/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.277554012 |
|
|
Mar 28 12:55:46 PM PDT 24 |
Mar 28 12:55:48 PM PDT 24 |
2542791098 ps |
| T542 |
/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2163824308 |
|
|
Mar 28 12:56:11 PM PDT 24 |
Mar 28 12:56:13 PM PDT 24 |
2533448006 ps |
| T543 |
/workspace/coverage/default/12.sysrst_ctrl_stress_all.1303359707 |
|
|
Mar 28 12:55:16 PM PDT 24 |
Mar 28 12:55:29 PM PDT 24 |
9574956916 ps |
| T544 |
/workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.82034257 |
|
|
Mar 28 12:55:52 PM PDT 24 |
Mar 28 12:55:58 PM PDT 24 |
3933030266 ps |
| T138 |
/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4164393507 |
|
|
Mar 28 12:55:18 PM PDT 24 |
Mar 28 12:55:22 PM PDT 24 |
12773717849 ps |
| T404 |
/workspace/coverage/default/45.sysrst_ctrl_stress_all.424123814 |
|
|
Mar 28 12:56:41 PM PDT 24 |
Mar 28 12:56:49 PM PDT 24 |
17297385964 ps |
| T545 |
/workspace/coverage/default/2.sysrst_ctrl_smoke.3182778019 |
|
|
Mar 28 12:55:01 PM PDT 24 |
Mar 28 12:55:04 PM PDT 24 |
2129489000 ps |
| T546 |
/workspace/coverage/default/30.sysrst_ctrl_pin_access_test.4134735953 |
|
|
Mar 28 12:56:03 PM PDT 24 |
Mar 28 12:56:10 PM PDT 24 |
2204037300 ps |
| T547 |
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.202914059 |
|
|
Mar 28 12:56:21 PM PDT 24 |
Mar 28 12:56:28 PM PDT 24 |
2466544876 ps |
| T368 |
/workspace/coverage/default/24.sysrst_ctrl_combo_detect.2378709706 |
|
|
Mar 28 12:55:48 PM PDT 24 |
Mar 28 12:57:42 PM PDT 24 |
176418031549 ps |
| T548 |
/workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1581085328 |
|
|
Mar 28 12:56:08 PM PDT 24 |
Mar 28 12:56:17 PM PDT 24 |
4968443104 ps |
| T549 |
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.454689269 |
|
|
Mar 28 12:55:06 PM PDT 24 |
Mar 28 12:55:09 PM PDT 24 |
2537128953 ps |
| T326 |
/workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1892103984 |
|
|
Mar 28 12:55:40 PM PDT 24 |
Mar 28 12:55:43 PM PDT 24 |
2797241007 ps |
| T379 |
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3555091005 |
|
|
Mar 28 12:57:04 PM PDT 24 |
Mar 28 12:58:07 PM PDT 24 |
51077215555 ps |
| T550 |
/workspace/coverage/default/12.sysrst_ctrl_pin_access_test.1264915929 |
|
|
Mar 28 12:55:19 PM PDT 24 |
Mar 28 12:55:25 PM PDT 24 |
2085335848 ps |
| T551 |
/workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2851217403 |
|
|
Mar 28 12:56:10 PM PDT 24 |
Mar 28 12:56:15 PM PDT 24 |
2613526111 ps |
| T363 |
/workspace/coverage/default/36.sysrst_ctrl_stress_all.1276268406 |
|
|
Mar 28 12:56:10 PM PDT 24 |
Mar 28 12:59:45 PM PDT 24 |
161499062332 ps |
| T101 |
/workspace/coverage/default/21.sysrst_ctrl_combo_detect.867453775 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:56:38 PM PDT 24 |
72273588753 ps |
| T552 |
/workspace/coverage/default/38.sysrst_ctrl_combo_detect.1691330665 |
|
|
Mar 28 12:56:05 PM PDT 24 |
Mar 28 12:58:36 PM PDT 24 |
92989647593 ps |
| T553 |
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1443940204 |
|
|
Mar 28 12:57:06 PM PDT 24 |
Mar 28 12:57:17 PM PDT 24 |
3518160209 ps |
| T554 |
/workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3284384467 |
|
|
Mar 28 12:55:18 PM PDT 24 |
Mar 28 12:55:20 PM PDT 24 |
2164629738 ps |
| T555 |
/workspace/coverage/default/0.sysrst_ctrl_smoke.3843835181 |
|
|
Mar 28 12:54:46 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
2115993587 ps |
| T556 |
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3196263216 |
|
|
Mar 28 12:56:43 PM PDT 24 |
Mar 28 12:56:47 PM PDT 24 |
2457902283 ps |
| T557 |
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.92328450 |
|
|
Mar 28 12:57:06 PM PDT 24 |
Mar 28 12:58:57 PM PDT 24 |
73928560909 ps |
| T81 |
/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3720258731 |
|
|
Mar 28 12:55:53 PM PDT 24 |
Mar 28 12:57:03 PM PDT 24 |
54694645289 ps |
| T233 |
/workspace/coverage/default/15.sysrst_ctrl_stress_all.2042589212 |
|
|
Mar 28 12:55:12 PM PDT 24 |
Mar 28 12:58:07 PM PDT 24 |
133050557163 ps |
| T558 |
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.952157462 |
|
|
Mar 28 12:55:06 PM PDT 24 |
Mar 28 12:55:15 PM PDT 24 |
2995334660 ps |
| T559 |
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.914737528 |
|
|
Mar 28 12:56:24 PM PDT 24 |
Mar 28 12:56:30 PM PDT 24 |
2510808601 ps |
| T560 |
/workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1235919709 |
|
|
Mar 28 12:54:54 PM PDT 24 |
Mar 28 12:54:56 PM PDT 24 |
2527392835 ps |
| T190 |
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3995164440 |
|
|
Mar 28 12:56:40 PM PDT 24 |
Mar 28 12:56:45 PM PDT 24 |
2798289086 ps |
| T561 |
/workspace/coverage/default/19.sysrst_ctrl_smoke.1710684668 |
|
|
Mar 28 12:55:40 PM PDT 24 |
Mar 28 12:55:42 PM PDT 24 |
2121847980 ps |
| T562 |
/workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1032165151 |
|
|
Mar 28 12:55:29 PM PDT 24 |
Mar 28 12:55:32 PM PDT 24 |
3228029660 ps |
| T563 |
/workspace/coverage/default/21.sysrst_ctrl_alert_test.2897249692 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:55:53 PM PDT 24 |
2019996016 ps |
| T564 |
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3128056007 |
|
|
Mar 28 12:56:39 PM PDT 24 |
Mar 28 12:56:45 PM PDT 24 |
7264582611 ps |
| T565 |
/workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2727329674 |
|
|
Mar 28 12:55:06 PM PDT 24 |
Mar 28 12:55:07 PM PDT 24 |
2559565024 ps |
| T566 |
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.272448279 |
|
|
Mar 28 12:56:40 PM PDT 24 |
Mar 28 12:57:46 PM PDT 24 |
97907445434 ps |
| T567 |
/workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3932902631 |
|
|
Mar 28 12:55:13 PM PDT 24 |
Mar 28 12:55:20 PM PDT 24 |
7011269021 ps |
| T568 |
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.889203211 |
|
|
Mar 28 12:56:40 PM PDT 24 |
Mar 28 12:56:45 PM PDT 24 |
2674879631 ps |
| T569 |
/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.4072329364 |
|
|
Mar 28 12:55:06 PM PDT 24 |
Mar 28 12:58:08 PM PDT 24 |
73042980523 ps |
| T570 |
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2058523443 |
|
|
Mar 28 12:56:15 PM PDT 24 |
Mar 28 12:56:20 PM PDT 24 |
3512349310 ps |
| T571 |
/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2256725447 |
|
|
Mar 28 12:55:23 PM PDT 24 |
Mar 28 12:55:29 PM PDT 24 |
3637398248 ps |
| T79 |
/workspace/coverage/default/32.sysrst_ctrl_stress_all.265829094 |
|
|
Mar 28 12:56:06 PM PDT 24 |
Mar 28 12:56:30 PM PDT 24 |
59528481914 ps |
| T194 |
/workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2090466942 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:55:58 PM PDT 24 |
2463278466 ps |
| T191 |
/workspace/coverage/default/3.sysrst_ctrl_stress_all.1650902276 |
|
|
Mar 28 12:54:58 PM PDT 24 |
Mar 28 12:56:00 PM PDT 24 |
85606031174 ps |
| T195 |
/workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3835340318 |
|
|
Mar 28 12:54:49 PM PDT 24 |
Mar 28 12:54:52 PM PDT 24 |
2545491652 ps |
| T196 |
/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2441322825 |
|
|
Mar 28 12:55:24 PM PDT 24 |
Mar 28 12:55:27 PM PDT 24 |
2233345944 ps |
| T197 |
/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2829406471 |
|
|
Mar 28 12:55:35 PM PDT 24 |
Mar 28 12:55:40 PM PDT 24 |
7288670160 ps |
| T198 |
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3122900799 |
|
|
Mar 28 12:56:38 PM PDT 24 |
Mar 28 12:56:42 PM PDT 24 |
2519811183 ps |
| T199 |
/workspace/coverage/default/15.sysrst_ctrl_edge_detect.4151526250 |
|
|
Mar 28 12:55:18 PM PDT 24 |
Mar 28 12:55:25 PM PDT 24 |
5487341606 ps |
| T200 |
/workspace/coverage/default/21.sysrst_ctrl_pin_access_test.4130386063 |
|
|
Mar 28 12:55:46 PM PDT 24 |
Mar 28 12:55:52 PM PDT 24 |
2093853717 ps |
| T201 |
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.2933384331 |
|
|
Mar 28 12:55:01 PM PDT 24 |
Mar 28 12:55:12 PM PDT 24 |
22076290648 ps |
| T572 |
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.915946313 |
|
|
Mar 28 12:55:09 PM PDT 24 |
Mar 28 12:55:13 PM PDT 24 |
2618670018 ps |
| T573 |
/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2809743098 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:55:56 PM PDT 24 |
2160968047 ps |
| T378 |
/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2403132461 |
|
|
Mar 28 12:55:13 PM PDT 24 |
Mar 28 12:59:39 PM PDT 24 |
147053335708 ps |
| T574 |
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.71688326 |
|
|
Mar 28 12:56:39 PM PDT 24 |
Mar 28 12:56:42 PM PDT 24 |
2526269187 ps |
| T575 |
/workspace/coverage/default/15.sysrst_ctrl_pin_access_test.992717318 |
|
|
Mar 28 12:55:28 PM PDT 24 |
Mar 28 12:55:34 PM PDT 24 |
2077825321 ps |
| T576 |
/workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2053097953 |
|
|
Mar 28 12:55:49 PM PDT 24 |
Mar 28 12:55:55 PM PDT 24 |
5927290814 ps |
| T144 |
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2495561685 |
|
|
Mar 28 12:55:08 PM PDT 24 |
Mar 28 12:55:11 PM PDT 24 |
5027550160 ps |
| T145 |
/workspace/coverage/default/26.sysrst_ctrl_stress_all.2747165339 |
|
|
Mar 28 12:55:52 PM PDT 24 |
Mar 28 12:56:50 PM PDT 24 |
81315498463 ps |
| T577 |
/workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3845846263 |
|
|
Mar 28 12:55:35 PM PDT 24 |
Mar 28 12:55:40 PM PDT 24 |
2514793908 ps |
| T102 |
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.404468656 |
|
|
Mar 28 12:55:05 PM PDT 24 |
Mar 28 12:57:44 PM PDT 24 |
245347044858 ps |
| T578 |
/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3762713307 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:55:53 PM PDT 24 |
3397564594 ps |
| T579 |
/workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.806365489 |
|
|
Mar 28 12:54:54 PM PDT 24 |
Mar 28 12:55:03 PM PDT 24 |
3143332801 ps |
| T580 |
/workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2323135937 |
|
|
Mar 28 12:55:55 PM PDT 24 |
Mar 28 12:55:57 PM PDT 24 |
3739639857 ps |
| T581 |
/workspace/coverage/default/22.sysrst_ctrl_pin_override_test.253018712 |
|
|
Mar 28 12:55:51 PM PDT 24 |
Mar 28 12:55:59 PM PDT 24 |
2510263914 ps |
| T582 |
/workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3648648233 |
|
|
Mar 28 12:56:12 PM PDT 24 |
Mar 28 12:57:41 PM PDT 24 |
31698213038 ps |
| T583 |
/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1197550933 |
|
|
Mar 28 12:55:51 PM PDT 24 |
Mar 28 12:55:52 PM PDT 24 |
2546865586 ps |
| T584 |
/workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3156968396 |
|
|
Mar 28 12:56:04 PM PDT 24 |
Mar 28 12:56:17 PM PDT 24 |
4612601106 ps |
| T258 |
/workspace/coverage/default/28.sysrst_ctrl_combo_detect.134426830 |
|
|
Mar 28 12:55:55 PM PDT 24 |
Mar 28 01:01:22 PM PDT 24 |
129522151691 ps |
| T585 |
/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3277648681 |
|
|
Mar 28 12:54:54 PM PDT 24 |
Mar 28 12:55:01 PM PDT 24 |
2530675648 ps |
| T586 |
/workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2278364478 |
|
|
Mar 28 12:55:29 PM PDT 24 |
Mar 28 12:55:39 PM PDT 24 |
3481024199 ps |
| T587 |
/workspace/coverage/default/47.sysrst_ctrl_stress_all.4057421449 |
|
|
Mar 28 12:56:40 PM PDT 24 |
Mar 28 12:57:15 PM PDT 24 |
14073717165 ps |
| T588 |
/workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.3549039701 |
|
|
Mar 28 12:55:29 PM PDT 24 |
Mar 28 12:55:31 PM PDT 24 |
2467811689 ps |
| T589 |
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.885544829 |
|
|
Mar 28 12:57:10 PM PDT 24 |
Mar 28 12:57:15 PM PDT 24 |
6240828168 ps |
| T590 |
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3836683102 |
|
|
Mar 28 12:55:17 PM PDT 24 |
Mar 28 12:55:19 PM PDT 24 |
2531775344 ps |
| T591 |
/workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2300534134 |
|
|
Mar 28 12:55:52 PM PDT 24 |
Mar 28 12:55:54 PM PDT 24 |
3855134675 ps |
| T592 |
/workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1074316274 |
|
|
Mar 28 12:55:23 PM PDT 24 |
Mar 28 12:56:03 PM PDT 24 |
14555211947 ps |
| T593 |
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3929682235 |
|
|
Mar 28 12:56:21 PM PDT 24 |
Mar 28 12:56:23 PM PDT 24 |
3183561397 ps |
| T594 |
/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2995231045 |
|
|
Mar 28 12:55:27 PM PDT 24 |
Mar 28 12:55:33 PM PDT 24 |
3430917260 ps |
| T193 |
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.278364248 |
|
|
Mar 28 12:56:20 PM PDT 24 |
Mar 28 12:58:47 PM PDT 24 |
423559375464 ps |
| T595 |
/workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3146979858 |
|
|
Mar 28 12:55:53 PM PDT 24 |
Mar 28 12:55:55 PM PDT 24 |
4496306875 ps |
| T396 |
/workspace/coverage/default/48.sysrst_ctrl_stress_all.861927816 |
|
|
Mar 28 12:57:07 PM PDT 24 |
Mar 28 12:58:20 PM PDT 24 |
157128052355 ps |
| T596 |
/workspace/coverage/default/4.sysrst_ctrl_alert_test.3880461030 |
|
|
Mar 28 12:55:03 PM PDT 24 |
Mar 28 12:55:10 PM PDT 24 |
2009444682 ps |
| T597 |
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3044044558 |
|
|
Mar 28 12:57:07 PM PDT 24 |
Mar 28 12:57:15 PM PDT 24 |
8609133229 ps |
| T384 |
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3912648010 |
|
|
Mar 28 12:57:08 PM PDT 24 |
Mar 28 12:57:51 PM PDT 24 |
93225594310 ps |
| T598 |
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.156785436 |
|
|
Mar 28 12:56:24 PM PDT 24 |
Mar 28 12:56:32 PM PDT 24 |
2483253721 ps |
| T599 |
/workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3500005904 |
|
|
Mar 28 12:56:07 PM PDT 24 |
Mar 28 12:56:15 PM PDT 24 |
2464368838 ps |
| T600 |
/workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1552235768 |
|
|
Mar 28 12:55:03 PM PDT 24 |
Mar 28 12:55:05 PM PDT 24 |
2190893582 ps |
| T601 |
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1215845667 |
|
|
Mar 28 12:56:13 PM PDT 24 |
Mar 28 12:56:16 PM PDT 24 |
3634115454 ps |
| T268 |
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2005396817 |
|
|
Mar 28 12:55:08 PM PDT 24 |
Mar 28 12:55:41 PM PDT 24 |
22945123649 ps |
| T602 |
/workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.444049493 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:55:53 PM PDT 24 |
4669674027 ps |
| T603 |
/workspace/coverage/default/40.sysrst_ctrl_smoke.2123318492 |
|
|
Mar 28 12:56:13 PM PDT 24 |
Mar 28 12:56:16 PM PDT 24 |
2121733442 ps |
| T604 |
/workspace/coverage/default/26.sysrst_ctrl_edge_detect.352760585 |
|
|
Mar 28 12:55:50 PM PDT 24 |
Mar 28 12:55:54 PM PDT 24 |
4250884750 ps |
| T103 |
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.3778317634 |
|
|
Mar 28 12:56:18 PM PDT 24 |
Mar 28 12:57:07 PM PDT 24 |
76106164053 ps |
| T605 |
/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.781430407 |
|
|
Mar 28 12:56:02 PM PDT 24 |
Mar 28 12:56:04 PM PDT 24 |
2627710502 ps |
| T400 |
/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1328720244 |
|
|
Mar 28 12:55:51 PM PDT 24 |
Mar 28 12:57:07 PM PDT 24 |
28831895615 ps |
| T606 |
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.900288922 |
|
|
Mar 28 12:56:21 PM PDT 24 |
Mar 28 12:56:23 PM PDT 24 |
2464236504 ps |
| T607 |
/workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.679776598 |
|
|
Mar 28 12:54:46 PM PDT 24 |
Mar 28 12:54:48 PM PDT 24 |
2637346089 ps |
| T608 |
/workspace/coverage/default/37.sysrst_ctrl_alert_test.563588940 |
|
|
Mar 28 12:56:10 PM PDT 24 |
Mar 28 12:56:16 PM PDT 24 |
2013532529 ps |
| T315 |
/workspace/coverage/default/31.sysrst_ctrl_stress_all.1700902143 |
|
|
Mar 28 12:56:05 PM PDT 24 |
Mar 28 12:56:24 PM PDT 24 |
13794870655 ps |
| T609 |
/workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.280306234 |
|
|
Mar 28 12:55:55 PM PDT 24 |
Mar 28 12:58:26 PM PDT 24 |
63527557060 ps |
| T610 |
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1672710937 |
|
|
Mar 28 12:57:05 PM PDT 24 |
Mar 28 12:57:52 PM PDT 24 |
73025668773 ps |
| T611 |
/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1464330567 |
|
|
Mar 28 12:55:55 PM PDT 24 |
Mar 28 12:56:01 PM PDT 24 |
3609895952 ps |
| T612 |
/workspace/coverage/default/31.sysrst_ctrl_combo_detect.3798469155 |
|
|
Mar 28 12:55:54 PM PDT 24 |
Mar 28 12:57:45 PM PDT 24 |
155958144020 ps |
| T613 |
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1168507741 |
|
|
Mar 28 12:55:09 PM PDT 24 |
Mar 28 12:55:12 PM PDT 24 |
5544264937 ps |
| T614 |
/workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.1630052622 |
|
|
Mar 28 12:55:13 PM PDT 24 |
Mar 28 12:55:20 PM PDT 24 |
2468928137 ps |
| T80 |
/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2809033984 |
|
|
Mar 28 12:55:40 PM PDT 24 |
Mar 28 12:56:40 PM PDT 24 |
237255168090 ps |
| T109 |
/workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.9395166 |
|
|
Mar 28 12:55:54 PM PDT 24 |
Mar 28 12:56:04 PM PDT 24 |
3297723002 ps |
| T110 |
/workspace/coverage/default/32.sysrst_ctrl_combo_detect.1314883184 |
|
|
Mar 28 12:56:06 PM PDT 24 |
Mar 28 12:56:28 PM PDT 24 |
33279077299 ps |
| T111 |
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1014073617 |
|
|
Mar 28 12:57:06 PM PDT 24 |
Mar 28 12:57:50 PM PDT 24 |
68699038801 ps |
| T112 |
/workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.547986780 |
|
|
Mar 28 12:54:53 PM PDT 24 |
Mar 28 12:54:55 PM PDT 24 |
3207815545 ps |
| T113 |
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.2712312552 |
|
|
Mar 28 12:56:21 PM PDT 24 |
Mar 28 12:56:25 PM PDT 24 |
4367080382 ps |
| T114 |
/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3637449802 |
|
|
Mar 28 12:55:04 PM PDT 24 |
Mar 28 12:55:14 PM PDT 24 |
3683668170 ps |
| T115 |
/workspace/coverage/default/34.sysrst_ctrl_smoke.818124487 |
|
|
Mar 28 12:56:05 PM PDT 24 |
Mar 28 12:56:12 PM PDT 24 |
2111192355 ps |
| T116 |
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2490339748 |
|
|
Mar 28 12:56:31 PM PDT 24 |
Mar 28 12:56:36 PM PDT 24 |
2615933297 ps |
| T117 |
/workspace/coverage/default/16.sysrst_ctrl_combo_detect.722455735 |
|
|
Mar 28 12:55:31 PM PDT 24 |
Mar 28 12:57:25 PM PDT 24 |
58019523724 ps |
| T615 |
/workspace/coverage/default/31.sysrst_ctrl_edge_detect.3037027088 |
|
|
Mar 28 12:56:01 PM PDT 24 |
Mar 28 12:56:08 PM PDT 24 |
3314609951 ps |
| T616 |
/workspace/coverage/default/42.sysrst_ctrl_smoke.138727406 |
|
|
Mar 28 12:56:16 PM PDT 24 |
Mar 28 12:56:18 PM PDT 24 |
2136543851 ps |