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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.09 99.29 96.71 100.00 96.15 98.74 99.42 89.30


Total test records in report: 916
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T222 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3274422570 Mar 28 12:55:46 PM PDT 24 Mar 28 12:55:49 PM PDT 24 2840400436 ps
T795 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2690194289 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:34 PM PDT 24 2012117342 ps
T24 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.379626889 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2225372528 ps
T25 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.669129058 Mar 28 12:32:20 PM PDT 24 Mar 28 12:32:25 PM PDT 24 2073185769 ps
T271 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3318682074 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:24 PM PDT 24 2186818649 ps
T26 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1561459310 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:26 PM PDT 24 4367765860 ps
T17 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2898071860 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:49 PM PDT 24 8814546124 ps
T280 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3496652082 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:27 PM PDT 24 2158771845 ps
T272 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.169280750 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:32 PM PDT 24 2059973362 ps
T796 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.4221041445 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:30 PM PDT 24 2018126354 ps
T797 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1107250644 Mar 28 12:32:27 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2045217936 ps
T273 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3287207928 Mar 28 12:32:17 PM PDT 24 Mar 28 12:32:55 PM PDT 24 42504567732 ps
T798 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1670904367 Mar 28 12:32:27 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2042172887 ps
T275 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3640496713 Mar 28 12:32:12 PM PDT 24 Mar 28 12:33:11 PM PDT 24 22232165019 ps
T279 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3084571666 Mar 28 12:32:17 PM PDT 24 Mar 28 12:32:24 PM PDT 24 2053179211 ps
T276 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3853209809 Mar 28 12:32:20 PM PDT 24 Mar 28 12:34:22 PM PDT 24 42392355735 ps
T799 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4274606365 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2020583138 ps
T287 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3126188789 Mar 28 12:32:14 PM PDT 24 Mar 28 12:34:00 PM PDT 24 42477293974 ps
T285 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3808834905 Mar 28 12:32:21 PM PDT 24 Mar 28 12:34:19 PM PDT 24 42499434828 ps
T18 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.957441410 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:29 PM PDT 24 5095986701 ps
T340 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1718423227 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:58 PM PDT 24 40840556112 ps
T800 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2438056557 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:32 PM PDT 24 2010907958 ps
T19 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.557704771 Mar 28 12:32:30 PM PDT 24 Mar 28 12:32:38 PM PDT 24 10638947399 ps
T801 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.479147396 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:32 PM PDT 24 2010669505 ps
T341 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2892382050 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:49 PM PDT 24 33783809734 ps
T802 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2821465546 Mar 28 12:31:57 PM PDT 24 Mar 28 12:32:04 PM PDT 24 2066277309 ps
T355 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1425984966 Mar 28 12:32:15 PM PDT 24 Mar 28 12:32:27 PM PDT 24 10074142800 ps
T803 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1425637087 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:32 PM PDT 24 2013249271 ps
T356 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3019485823 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:25 PM PDT 24 8551400149 ps
T804 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.526254732 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:24 PM PDT 24 2011193197 ps
T805 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.116575882 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:34 PM PDT 24 2010645230 ps
T278 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.537655637 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:21 PM PDT 24 2211352261 ps
T342 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2062544555 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2052448585 ps
T806 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.965845432 Mar 28 12:32:29 PM PDT 24 Mar 28 12:32:35 PM PDT 24 23151820088 ps
T807 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3225774042 Mar 28 12:32:29 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2036638276 ps
T808 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1266027321 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2049101353 ps
T281 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2607990382 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2264651525 ps
T343 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.190766554 Mar 28 12:32:04 PM PDT 24 Mar 28 12:32:06 PM PDT 24 2075831587 ps
T809 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2854058331 Mar 28 12:32:15 PM PDT 24 Mar 28 12:32:21 PM PDT 24 2032118361 ps
T810 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1660181920 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:28 PM PDT 24 2020066433 ps
T357 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3419212907 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:19 PM PDT 24 2026129488 ps
T811 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.4081245848 Mar 28 12:32:31 PM PDT 24 Mar 28 12:32:34 PM PDT 24 2021282359 ps
T284 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.713789652 Mar 28 12:32:19 PM PDT 24 Mar 28 12:33:22 PM PDT 24 42381818363 ps
T812 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2011279228 Mar 28 12:32:31 PM PDT 24 Mar 28 12:32:34 PM PDT 24 2019562798 ps
T813 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1578465554 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:11 PM PDT 24 2095250641 ps
T814 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2523413338 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:28 PM PDT 24 2150292362 ps
T358 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1769914511 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:34 PM PDT 24 2064770643 ps
T286 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.375327078 Mar 28 12:32:18 PM PDT 24 Mar 28 12:32:25 PM PDT 24 2100752352 ps
T815 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2544167517 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:24 PM PDT 24 2410174696 ps
T376 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2763962248 Mar 28 12:32:28 PM PDT 24 Mar 28 12:34:20 PM PDT 24 42435722568 ps
T816 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2913867213 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:31 PM PDT 24 4762222955 ps
T817 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4052155854 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2246124420 ps
T344 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3924855863 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2051857086 ps
T283 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3031812214 Mar 28 12:32:27 PM PDT 24 Mar 28 12:32:59 PM PDT 24 42757912870 ps
T818 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2788361051 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:41 PM PDT 24 22448649122 ps
T819 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3431667876 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:28 PM PDT 24 2017097500 ps
T820 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2271377906 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:34 PM PDT 24 2012285265 ps
T821 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2610335397 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:42 PM PDT 24 22516425151 ps
T822 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2182784588 Mar 28 12:32:44 PM PDT 24 Mar 28 12:32:50 PM PDT 24 2011636811 ps
T345 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1715740 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:30 PM PDT 24 2194477753 ps
T346 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3609213157 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2043276522 ps
T282 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2777656556 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:19 PM PDT 24 2034140224 ps
T823 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1151969552 Mar 28 12:32:17 PM PDT 24 Mar 28 12:32:23 PM PDT 24 2017274980 ps
T824 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1871358468 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2191320007 ps
T825 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.2039408943 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:30 PM PDT 24 2014928139 ps
T826 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3466937989 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2064956981 ps
T827 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2531020318 Mar 28 12:32:31 PM PDT 24 Mar 28 12:32:35 PM PDT 24 4450149533 ps
T828 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3915975831 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:26 PM PDT 24 2028851235 ps
T829 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.355839071 Mar 28 12:32:13 PM PDT 24 Mar 28 12:32:22 PM PDT 24 2090762036 ps
T830 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.4062587356 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2064341355 ps
T374 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.384187974 Mar 28 12:32:12 PM PDT 24 Mar 28 12:33:43 PM PDT 24 42496166507 ps
T831 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2806806299 Mar 28 12:32:32 PM PDT 24 Mar 28 12:32:34 PM PDT 24 2032146642 ps
T832 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.4101408700 Mar 28 12:32:13 PM PDT 24 Mar 28 12:32:33 PM PDT 24 6027790339 ps
T833 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.64095404 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:25 PM PDT 24 2438546028 ps
T834 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1003724082 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2074220949 ps
T835 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3146218774 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2014109160 ps
T836 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1403611537 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:28 PM PDT 24 4070361651 ps
T837 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.621267209 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2046466611 ps
T838 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2786398795 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:29 PM PDT 24 7276692191 ps
T347 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.269069632 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:29 PM PDT 24 6076230584 ps
T839 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3402448813 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2504438347 ps
T840 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3638885520 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:17 PM PDT 24 2013553428 ps
T841 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3244657823 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2295524170 ps
T842 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3779387539 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2036424640 ps
T843 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.597304715 Mar 28 12:32:29 PM PDT 24 Mar 28 12:32:35 PM PDT 24 2009698324 ps
T348 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2647558207 Mar 28 12:32:19 PM PDT 24 Mar 28 12:32:24 PM PDT 24 2100854993 ps
T844 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2760337843 Mar 28 12:32:27 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2012178704 ps
T845 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.435742261 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:28 PM PDT 24 2171911284 ps
T846 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2929598007 Mar 28 12:32:13 PM PDT 24 Mar 28 12:32:32 PM PDT 24 7281184515 ps
T847 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3050116158 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:32 PM PDT 24 2015819835 ps
T848 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2703893886 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:44 PM PDT 24 4526422499 ps
T849 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3584844775 Mar 28 12:32:39 PM PDT 24 Mar 28 12:32:44 PM PDT 24 2012579278 ps
T850 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1936275314 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:32 PM PDT 24 5060293113 ps
T851 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.449201255 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:27 PM PDT 24 2310178568 ps
T852 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2403586863 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:13 PM PDT 24 4631208687 ps
T853 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.77183380 Mar 28 12:32:11 PM PDT 24 Mar 28 12:34:02 PM PDT 24 42364719437 ps
T854 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.313387251 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2116812142 ps
T855 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2147565513 Mar 28 12:32:27 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2030278657 ps
T349 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1854771563 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:26 PM PDT 24 2442167813 ps
T856 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.270460599 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:34 PM PDT 24 9838007233 ps
T857 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.451093689 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:18 PM PDT 24 2047057501 ps
T350 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.572112546 Mar 28 12:32:16 PM PDT 24 Mar 28 12:34:41 PM PDT 24 30913676436 ps
T858 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.218933873 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:33 PM PDT 24 7735661066 ps
T351 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1541037469 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:30 PM PDT 24 3135642397 ps
T859 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4187896051 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:35 PM PDT 24 6061445187 ps
T860 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4195680223 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:30 PM PDT 24 2013722802 ps
T861 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.47350162 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:32 PM PDT 24 2026365321 ps
T862 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1284830406 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:28 PM PDT 24 2032831983 ps
T863 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.472935025 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:40 PM PDT 24 4725404781 ps
T864 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3419583899 Mar 28 12:32:18 PM PDT 24 Mar 28 12:32:23 PM PDT 24 3037141314 ps
T352 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2834814870 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:19 PM PDT 24 2051068158 ps
T865 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3640242024 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:32 PM PDT 24 2063345927 ps
T866 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3007436257 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:27 PM PDT 24 2045194878 ps
T867 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.878867840 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2097541545 ps
T375 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1589617201 Mar 28 12:32:09 PM PDT 24 Mar 28 12:33:17 PM PDT 24 42417817417 ps
T868 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1643186375 Mar 28 12:32:09 PM PDT 24 Mar 28 12:32:36 PM PDT 24 22324869488 ps
T869 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1357940909 Mar 28 12:32:21 PM PDT 24 Mar 28 12:32:27 PM PDT 24 2521098217 ps
T870 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.4147100134 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:26 PM PDT 24 2032772162 ps
T871 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4163840910 Mar 28 12:32:28 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2120607447 ps
T872 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.587719309 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:32 PM PDT 24 4574914085 ps
T873 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.793564665 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:27 PM PDT 24 2125847782 ps
T874 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.652068837 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:30 PM PDT 24 2019400465 ps
T875 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.672008985 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:20 PM PDT 24 2161961288 ps
T876 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.987108231 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:28 PM PDT 24 2278840675 ps
T877 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2425405648 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2037959883 ps
T878 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3823379272 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:30 PM PDT 24 2084257446 ps
T879 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.116461920 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:19 PM PDT 24 2018356661 ps
T880 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1053016489 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:30 PM PDT 24 22340918450 ps
T881 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3840827443 Mar 28 12:32:30 PM PDT 24 Mar 28 12:32:36 PM PDT 24 2078609774 ps
T882 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.4090726628 Mar 28 12:32:16 PM PDT 24 Mar 28 12:32:22 PM PDT 24 2148831085 ps
T883 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.227876289 Mar 28 12:32:11 PM PDT 24 Mar 28 12:32:14 PM PDT 24 2075946222 ps
T884 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2126686690 Mar 28 12:32:22 PM PDT 24 Mar 28 12:32:54 PM PDT 24 22251668961 ps
T885 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3333866868 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:19 PM PDT 24 2075124038 ps
T886 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.880141735 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:30 PM PDT 24 2030108091 ps
T887 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3541815021 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:39 PM PDT 24 45007767096 ps
T888 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3822676925 Mar 28 12:32:10 PM PDT 24 Mar 28 12:32:33 PM PDT 24 8443974023 ps
T889 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.57335861 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:21 PM PDT 24 2108174671 ps
T890 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.4119123117 Mar 28 12:32:34 PM PDT 24 Mar 28 12:32:40 PM PDT 24 2013230783 ps
T891 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1446971962 Mar 28 12:32:27 PM PDT 24 Mar 28 12:32:57 PM PDT 24 42519673980 ps
T892 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.688514053 Mar 28 12:32:17 PM PDT 24 Mar 28 12:32:45 PM PDT 24 40085099090 ps
T893 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3066329036 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:33 PM PDT 24 6789240728 ps
T353 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3198286244 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:22 PM PDT 24 2053803925 ps
T894 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.469379547 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:26 PM PDT 24 2129068825 ps
T895 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.624082771 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2171841493 ps
T896 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.479503759 Mar 28 12:32:06 PM PDT 24 Mar 28 12:32:13 PM PDT 24 2712594847 ps
T897 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.50893446 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2106205501 ps
T898 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3983426032 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2148512659 ps
T899 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.545440792 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:30 PM PDT 24 2014351699 ps
T900 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3368475277 Mar 28 12:32:12 PM PDT 24 Mar 28 12:32:22 PM PDT 24 2036169923 ps
T901 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2017641327 Mar 28 12:32:23 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2050305638 ps
T354 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3353552657 Mar 28 12:32:11 PM PDT 24 Mar 28 12:35:13 PM PDT 24 74113146156 ps
T902 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3987125075 Mar 28 12:32:18 PM PDT 24 Mar 28 12:32:27 PM PDT 24 2017513423 ps
T903 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.746419934 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:57 PM PDT 24 43896292214 ps
T904 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2508116985 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:26 PM PDT 24 2034783737 ps
T905 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2770730196 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:28 PM PDT 24 2047070734 ps
T906 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3551669311 Mar 28 12:32:20 PM PDT 24 Mar 28 12:32:29 PM PDT 24 7516205382 ps
T907 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1219512314 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:29 PM PDT 24 2032418236 ps
T908 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3677776180 Mar 28 12:32:18 PM PDT 24 Mar 28 12:32:38 PM PDT 24 6033028910 ps
T909 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2770890023 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2098403664 ps
T910 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.661254140 Mar 28 12:32:25 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2045415479 ps
T911 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3151774954 Mar 28 12:32:24 PM PDT 24 Mar 28 12:32:31 PM PDT 24 2014339861 ps
T912 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1513152652 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:23 PM PDT 24 2463774986 ps
T913 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.380813700 Mar 28 12:32:30 PM PDT 24 Mar 28 12:32:36 PM PDT 24 2065847028 ps
T914 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.848647943 Mar 28 12:33:05 PM PDT 24 Mar 28 12:33:07 PM PDT 24 2037260418 ps
T915 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2741275893 Mar 28 12:32:14 PM PDT 24 Mar 28 12:32:25 PM PDT 24 2035044923 ps
T916 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.762612466 Mar 28 12:32:26 PM PDT 24 Mar 28 12:32:33 PM PDT 24 2010282400 ps

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.4080375685
Short name T1
Test name
Test status
Simulation time 1767678367546 ps
CPU time 269.2 seconds
Started Mar 28 12:55:19 PM PDT 24
Finished Mar 28 12:59:48 PM PDT 24
Peak memory 210520 kb
Host smart-2bebc13e-5709-4d39-b73a-ea30765b2a82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080375685 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.4080375685
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2048105659
Short name T5
Test name
Test status
Simulation time 92236161618 ps
CPU time 65.6 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:58:17 PM PDT 24
Peak memory 202204 kb
Host smart-9261c3bf-8b6c-4a25-bce3-6ea512d705bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048105659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.2048105659
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2249995996
Short name T33
Test name
Test status
Simulation time 64265503989 ps
CPU time 59.92 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:56:55 PM PDT 24
Peak memory 210460 kb
Host smart-dd659b05-1cd0-43dc-92ee-3b3fc83d98ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249995996 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2249995996
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3663675241
Short name T55
Test name
Test status
Simulation time 70061491395 ps
CPU time 44.64 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:57:52 PM PDT 24
Peak memory 210500 kb
Host smart-7065613e-07b3-4e27-9422-d0b9ddc29ce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663675241 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3663675241
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2149303667
Short name T77
Test name
Test status
Simulation time 34302318225 ps
CPU time 93.27 seconds
Started Mar 28 12:55:00 PM PDT 24
Finished Mar 28 12:56:34 PM PDT 24
Peak memory 201872 kb
Host smart-087a21ba-45ac-4758-8b1b-eec7d2ef1b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149303667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.2149303667
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.868453119
Short name T71
Test name
Test status
Simulation time 6130786660 ps
CPU time 9.15 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:14 PM PDT 24
Peak memory 201956 kb
Host smart-f3606e18-fe92-418f-a4db-cf1f226e26fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868453119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ultra_low_pwr.868453119
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1396379863
Short name T100
Test name
Test status
Simulation time 431862425890 ps
CPU time 62.12 seconds
Started Mar 28 12:54:50 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 215760 kb
Host smart-b6d9fa3d-b089-4465-ad61-ba951dbf0118
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396379863 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.1396379863
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3853209809
Short name T276
Test name
Test status
Simulation time 42392355735 ps
CPU time 119.57 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:34:22 PM PDT 24
Peak memory 201468 kb
Host smart-6a4999e3-2a33-4712-a1f7-a2b7ce130295
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853209809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.3853209809
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2809033984
Short name T80
Test name
Test status
Simulation time 237255168090 ps
CPU time 60.26 seconds
Started Mar 28 12:55:40 PM PDT 24
Finished Mar 28 12:56:40 PM PDT 24
Peak memory 215492 kb
Host smart-799de0f7-356c-44a2-bd72-5a42f1f4fa7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809033984 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.2809033984
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3826930767
Short name T57
Test name
Test status
Simulation time 91998557192 ps
CPU time 32.98 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 210456 kb
Host smart-3b207042-021e-4e5f-94a5-bc64c5fc3482
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826930767 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.3826930767
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.500415350
Short name T30
Test name
Test status
Simulation time 80280122335 ps
CPU time 113 seconds
Started Mar 28 12:55:07 PM PDT 24
Finished Mar 28 12:57:00 PM PDT 24
Peak memory 202144 kb
Host smart-0e069836-cee5-44db-b0e3-cd747342c716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500415350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_wi
th_pre_cond.500415350
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1302975943
Short name T313
Test name
Test status
Simulation time 93976599070 ps
CPU time 114.5 seconds
Started Mar 28 12:56:31 PM PDT 24
Finished Mar 28 12:58:26 PM PDT 24
Peak memory 202108 kb
Host smart-e3b4bc83-a707-4c86-aa78-b9f1d52dd2a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302975943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.1302975943
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.879829491
Short name T42
Test name
Test status
Simulation time 22590696352 ps
CPU time 31.94 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:38 PM PDT 24
Peak memory 202224 kb
Host smart-c72a9eb9-4ae7-44ff-9a4e-5421dfad785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879829491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wit
h_pre_cond.879829491
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.1607587774
Short name T85
Test name
Test status
Simulation time 13371270751 ps
CPU time 13.99 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:56:10 PM PDT 24
Peak memory 201996 kb
Host smart-4f88b9bc-5367-44a7-bb28-756fe0bb5442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607587774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.1607587774
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.265829094
Short name T79
Test name
Test status
Simulation time 59528481914 ps
CPU time 23.87 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:30 PM PDT 24
Peak memory 201768 kb
Host smart-3887939b-ba75-4cf4-b711-6571da65fd0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265829094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_st
ress_all.265829094
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.82815397
Short name T90
Test name
Test status
Simulation time 42013310499 ps
CPU time 114.86 seconds
Started Mar 28 12:54:50 PM PDT 24
Finished Mar 28 12:56:45 PM PDT 24
Peak memory 221744 kb
Host smart-5c738ee1-0e47-4742-8790-9d8a60812f92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82815397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.82815397
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.263773528
Short name T206
Test name
Test status
Simulation time 1262551178073 ps
CPU time 67.46 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:57:01 PM PDT 24
Peak memory 210464 kb
Host smart-5ef6dbb5-97af-4b52-9861-f74204488ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263773528 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.263773528
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1287586138
Short name T94
Test name
Test status
Simulation time 261869845596 ps
CPU time 108.63 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:57:54 PM PDT 24
Peak memory 213056 kb
Host smart-04ed2303-368d-4360-8e1b-a9921bcd6980
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287586138 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1287586138
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3914926170
Short name T250
Test name
Test status
Simulation time 127629830978 ps
CPU time 345.91 seconds
Started Mar 28 12:55:34 PM PDT 24
Finished Mar 28 01:01:20 PM PDT 24
Peak memory 202128 kb
Host smart-862d5eb3-4d95-4626-91b6-609a78b1ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914926170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.3914926170
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.537655637
Short name T278
Test name
Test status
Simulation time 2211352261 ps
CPU time 4.17 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201340 kb
Host smart-ba6c657d-ceec-4818-809b-c6a7bf1c5b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537655637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_error
s.537655637
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.4188150211
Short name T82
Test name
Test status
Simulation time 6273643920 ps
CPU time 4.78 seconds
Started Mar 28 12:54:51 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 201888 kb
Host smart-432ca954-f440-47ff-8ff3-134194ecf31d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188150211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.4188150211
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.4269762361
Short name T127
Test name
Test status
Simulation time 260696354167 ps
CPU time 49.43 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:56:42 PM PDT 24
Peak memory 218600 kb
Host smart-1b6c7ecd-4ced-413f-a84d-7561c0f2046d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269762361 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.4269762361
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1117628903
Short name T161
Test name
Test status
Simulation time 57387287321 ps
CPU time 78.08 seconds
Started Mar 28 12:55:16 PM PDT 24
Finished Mar 28 12:56:34 PM PDT 24
Peak memory 210528 kb
Host smart-19eb9646-e2bc-4982-83ea-e445610f67bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117628903 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.1117628903
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2784689195
Short name T118
Test name
Test status
Simulation time 86850144448 ps
CPU time 210.4 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 01:00:38 PM PDT 24
Peak memory 202076 kb
Host smart-a028a8ce-98f0-4ff0-80b1-0dcaead9c092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784689195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.2784689195
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3199571374
Short name T148
Test name
Test status
Simulation time 3880764181 ps
CPU time 2.16 seconds
Started Mar 28 12:56:14 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201968 kb
Host smart-35f8baff-eade-4c36-8091-8218cbd38e59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199571374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.3199571374
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2062544555
Short name T342
Test name
Test status
Simulation time 2052448585 ps
CPU time 6 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201228 kb
Host smart-9c39fea6-9ad2-4986-9832-3615c89f5ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062544555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.2062544555
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1749179746
Short name T37
Test name
Test status
Simulation time 87532700822 ps
CPU time 118.34 seconds
Started Mar 28 12:55:00 PM PDT 24
Finished Mar 28 12:56:59 PM PDT 24
Peak memory 202144 kb
Host smart-9c7bb77b-477f-4b3e-a4b3-11b318871f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749179746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.1749179746
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.87336135
Short name T27
Test name
Test status
Simulation time 82291744561 ps
CPU time 55.94 seconds
Started Mar 28 12:55:07 PM PDT 24
Finished Mar 28 12:56:04 PM PDT 24
Peak memory 202128 kb
Host smart-6f346f5c-705d-4014-b31d-738f456af2b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87336135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl
_combo_detect.87336135
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.404468656
Short name T102
Test name
Test status
Simulation time 245347044858 ps
CPU time 159.06 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:57:44 PM PDT 24
Peak memory 210656 kb
Host smart-26a8487c-56d9-44f6-b0c0-5f2b2d726bbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404468656 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.404468656
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.33422560
Short name T50
Test name
Test status
Simulation time 32305445234 ps
CPU time 84.31 seconds
Started Mar 28 12:54:52 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201896 kb
Host smart-213171a5-a68a-49e8-b557-607ab763143c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33422560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.33422560
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1966605438
Short name T43
Test name
Test status
Simulation time 197261714827 ps
CPU time 513.68 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 01:03:40 PM PDT 24
Peak memory 202032 kb
Host smart-2d74f558-f674-42d0-9f16-6c8724527e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966605438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.1
966605438
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.1080130548
Short name T14
Test name
Test status
Simulation time 2018124604 ps
CPU time 5.08 seconds
Started Mar 28 12:55:03 PM PDT 24
Finished Mar 28 12:55:09 PM PDT 24
Peak memory 201936 kb
Host smart-6b00a667-5fa7-485e-a874-824a0cbb43b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080130548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.1080130548
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3924855863
Short name T344
Test name
Test status
Simulation time 2051857086 ps
CPU time 3.72 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201200 kb
Host smart-ccf9c56c-f56a-469c-867f-55d7fcc2925d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924855863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3924855863
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.596348190
Short name T394
Test name
Test status
Simulation time 66721011747 ps
CPU time 189.08 seconds
Started Mar 28 12:55:12 PM PDT 24
Finished Mar 28 12:58:21 PM PDT 24
Peak memory 201996 kb
Host smart-41a50052-9205-4ec6-8af8-622ed83722bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596348190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_wi
th_pre_cond.596348190
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.2019047777
Short name T179
Test name
Test status
Simulation time 505861279712 ps
CPU time 1048.26 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 01:12:36 PM PDT 24
Peak memory 202152 kb
Host smart-c3ad17de-9568-4ec2-9bfe-2a69f7a5e509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019047777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.2019047777
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2008163019
Short name T403
Test name
Test status
Simulation time 132278889200 ps
CPU time 90.71 seconds
Started Mar 28 12:55:07 PM PDT 24
Finished Mar 28 12:56:37 PM PDT 24
Peak memory 210452 kb
Host smart-7561ff5a-cd94-469e-901a-1ea5c4925aa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008163019 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.2008163019
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2273214744
Short name T385
Test name
Test status
Simulation time 129313362376 ps
CPU time 79.69 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:58:26 PM PDT 24
Peak memory 202056 kb
Host smart-06abf9f0-cc64-4a36-be4f-2c1d77174bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273214744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2273214744
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3610030979
Short name T373
Test name
Test status
Simulation time 111088624245 ps
CPU time 310.44 seconds
Started Mar 28 12:57:03 PM PDT 24
Finished Mar 28 01:02:13 PM PDT 24
Peak memory 202140 kb
Host smart-1537e21c-0b1b-4995-88ab-239082b67030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610030979 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.3610030979
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.525005425
Short name T164
Test name
Test status
Simulation time 283599738290 ps
CPU time 35.85 seconds
Started Mar 28 12:57:02 PM PDT 24
Finished Mar 28 12:57:37 PM PDT 24
Peak memory 210564 kb
Host smart-fb3cc59d-04ba-4e28-984f-dc89a753c88e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525005425 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.525005425
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1954125708
Short name T370
Test name
Test status
Simulation time 136453959136 ps
CPU time 25.39 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:34 PM PDT 24
Peak memory 202132 kb
Host smart-8795757c-f554-4116-b93f-8177b3506fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954125708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.1954125708
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3296679304
Short name T401
Test name
Test status
Simulation time 85805843157 ps
CPU time 56.02 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:58:07 PM PDT 24
Peak memory 202188 kb
Host smart-6b78cbe1-04f7-40d6-a10b-60c8502af512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296679304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3296679304
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3244657823
Short name T841
Test name
Test status
Simulation time 2295524170 ps
CPU time 3.03 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 209472 kb
Host smart-726b6e29-f95c-451e-a6f0-b4249880227d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244657823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.3244657823
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2403132461
Short name T378
Test name
Test status
Simulation time 147053335708 ps
CPU time 265.6 seconds
Started Mar 28 12:55:13 PM PDT 24
Finished Mar 28 12:59:39 PM PDT 24
Peak memory 202132 kb
Host smart-02170a85-8281-4b0c-b1c0-ea433727b402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403132461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.2403132461
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3829934275
Short name T269
Test name
Test status
Simulation time 76186889944 ps
CPU time 50.29 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 202140 kb
Host smart-f75ddaca-b9bf-4038-addf-6bcbe10868dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829934275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.3829934275
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.477672343
Short name T369
Test name
Test status
Simulation time 110473206631 ps
CPU time 17.73 seconds
Started Mar 28 12:55:20 PM PDT 24
Finished Mar 28 12:55:38 PM PDT 24
Peak memory 202168 kb
Host smart-b42d6dd6-6577-4c54-a8f3-5c1253439718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477672343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_wi
th_pre_cond.477672343
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2479282615
Short name T386
Test name
Test status
Simulation time 82449211763 ps
CPU time 86.79 seconds
Started Mar 28 12:55:35 PM PDT 24
Finished Mar 28 12:57:02 PM PDT 24
Peak memory 202116 kb
Host smart-61cfbb04-b6b0-4822-9866-ad50c292398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479282615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.2479282615
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3315845881
Short name T62
Test name
Test status
Simulation time 2466372114 ps
CPU time 4.52 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201964 kb
Host smart-036945f0-e1fe-494d-bccc-241023e0f9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315845881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.3315845881
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.4164510396
Short name T666
Test name
Test status
Simulation time 48388071421 ps
CPU time 114.26 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:56:59 PM PDT 24
Peak memory 202248 kb
Host smart-fa8dbe92-e350-4580-b713-dbce38352801
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164510396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.4164510396
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1977210606
Short name T207
Test name
Test status
Simulation time 2963589036 ps
CPU time 7.13 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 201932 kb
Host smart-07957c8b-4e43-45fd-b4bb-e6a7e985f259
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977210606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.1977210606
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.1388484214
Short name T136
Test name
Test status
Simulation time 4231945401 ps
CPU time 8 seconds
Started Mar 28 12:55:01 PM PDT 24
Finished Mar 28 12:55:09 PM PDT 24
Peak memory 201884 kb
Host smart-55bcbd94-6771-4b53-82de-1d6c1bd84161
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388484214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.1388484214
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3041664312
Short name T162
Test name
Test status
Simulation time 32095058396 ps
CPU time 81.08 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:57:25 PM PDT 24
Peak memory 212044 kb
Host smart-5f27893a-219a-45b0-8310-011b53a9c8b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041664312 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.3041664312
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.3946149419
Short name T86
Test name
Test status
Simulation time 17394387173 ps
CPU time 6.58 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 12:56:15 PM PDT 24
Peak memory 201920 kb
Host smart-22286c8f-564b-4cfe-bd4f-def2e4c25ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946149419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.3946149419
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.384187974
Short name T374
Test name
Test status
Simulation time 42496166507 ps
CPU time 88.5 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:33:43 PM PDT 24
Peak memory 201416 kb
Host smart-13a9cfc8-f333-4c2d-b9e0-cb84109d4e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384187974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_tl_intg_err.384187974
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3352050076
Short name T372
Test name
Test status
Simulation time 76452120231 ps
CPU time 54.25 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:55:43 PM PDT 24
Peak memory 202124 kb
Host smart-c44921be-2618-42a0-b9c0-98e4a70d9bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352050076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.3352050076
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1328720244
Short name T400
Test name
Test status
Simulation time 28831895615 ps
CPU time 75.52 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:57:07 PM PDT 24
Peak memory 202200 kb
Host smart-9c3c6edb-b12e-46ac-8e49-63183534e194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328720244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.1328720244
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.925500799
Short name T397
Test name
Test status
Simulation time 83560368691 ps
CPU time 33.05 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:57 PM PDT 24
Peak memory 202136 kb
Host smart-41b8c403-2cd2-43eb-9e4c-6a3a89946df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925500799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_wi
th_pre_cond.925500799
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.137873100
Short name T381
Test name
Test status
Simulation time 32988449608 ps
CPU time 23.51 seconds
Started Mar 28 12:56:18 PM PDT 24
Finished Mar 28 12:56:42 PM PDT 24
Peak memory 202164 kb
Host smart-36f3797b-b06c-46c4-8c60-61223cf01043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137873100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_wi
th_pre_cond.137873100
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.108000444
Short name T88
Test name
Test status
Simulation time 95700539404 ps
CPU time 66.42 seconds
Started Mar 28 12:57:04 PM PDT 24
Finished Mar 28 12:58:11 PM PDT 24
Peak memory 202168 kb
Host smart-36bae808-84cf-4c55-8a16-0e2888e64863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108000444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_wi
th_pre_cond.108000444
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.4105749992
Short name T371
Test name
Test status
Simulation time 93869671996 ps
CPU time 244.45 seconds
Started Mar 28 12:57:12 PM PDT 24
Finished Mar 28 01:01:18 PM PDT 24
Peak memory 202056 kb
Host smart-b13b5b88-34a2-4554-8149-f9cf654a9bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105749992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.4105749992
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3720258731
Short name T81
Test name
Test status
Simulation time 54694645289 ps
CPU time 70.81 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:57:03 PM PDT 24
Peak memory 202068 kb
Host smart-eeaf2deb-dca3-4e7e-a2e6-2bfb7d5d5fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720258731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.3720258731
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1794989845
Short name T69
Test name
Test status
Simulation time 56435502532 ps
CPU time 71.72 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:57:03 PM PDT 24
Peak memory 202104 kb
Host smart-fc520bad-fe84-4a57-84c0-1024631f89c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794989845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.1794989845
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1513152652
Short name T912
Test name
Test status
Simulation time 2463774986 ps
CPU time 4.91 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 201348 kb
Host smart-654563f1-4d0e-4da9-9ef3-d1e2b61511eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513152652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.1513152652
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.688514053
Short name T892
Test name
Test status
Simulation time 40085099090 ps
CPU time 24.06 seconds
Started Mar 28 12:32:17 PM PDT 24
Finished Mar 28 12:32:45 PM PDT 24
Peak memory 201364 kb
Host smart-977e0d84-d973-41e4-ab20-37c8d5f9e281
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688514053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_bit_bash.688514053
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.4101408700
Short name T832
Test name
Test status
Simulation time 6027790339 ps
CPU time 15.99 seconds
Started Mar 28 12:32:13 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201320 kb
Host smart-264c51ab-b6c6-450d-bb03-8738c11c57aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101408700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.4101408700
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.672008985
Short name T875
Test name
Test status
Simulation time 2161961288 ps
CPU time 1.68 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:20 PM PDT 24
Peak memory 201380 kb
Host smart-a834e7c8-a2af-430f-a0b8-962f2ee7f2a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672008985 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.672008985
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3198286244
Short name T353
Test name
Test status
Simulation time 2053803925 ps
CPU time 3.51 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:22 PM PDT 24
Peak memory 201232 kb
Host smart-de28c988-e778-459e-8815-b31d459b1d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198286244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.3198286244
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3638885520
Short name T840
Test name
Test status
Simulation time 2013553428 ps
CPU time 5.35 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:17 PM PDT 24
Peak memory 200716 kb
Host smart-a96ec863-2e90-4e6d-806d-9242e4067752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638885520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.3638885520
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.587719309
Short name T872
Test name
Test status
Simulation time 4574914085 ps
CPU time 7.01 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 201324 kb
Host smart-d2b3cbbe-3a51-4176-a64b-1f391cf22ad4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587719309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
sysrst_ctrl_same_csr_outstanding.587719309
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2610335397
Short name T821
Test name
Test status
Simulation time 22516425151 ps
CPU time 17.66 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:42 PM PDT 24
Peak memory 201404 kb
Host smart-9fc7fa1f-73f8-4129-9fa4-21344bf2849d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610335397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.2610335397
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1541037469
Short name T351
Test name
Test status
Simulation time 3135642397 ps
CPU time 6.05 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 201308 kb
Host smart-3aa50932-50ce-4acd-bdf1-2ef6e112651b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541037469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.1541037469
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.572112546
Short name T350
Test name
Test status
Simulation time 30913676436 ps
CPU time 141.84 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:34:41 PM PDT 24
Peak memory 201320 kb
Host smart-022afd8e-775c-46ee-bcad-4dde2856f83f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572112546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_bit_bash.572112546
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3677776180
Short name T908
Test name
Test status
Simulation time 6033028910 ps
CPU time 16.9 seconds
Started Mar 28 12:32:18 PM PDT 24
Finished Mar 28 12:32:38 PM PDT 24
Peak memory 201324 kb
Host smart-423efb8b-9709-43d5-a257-6c6b7871da1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677776180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.3677776180
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2523413338
Short name T814
Test name
Test status
Simulation time 2150292362 ps
CPU time 3.47 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 201372 kb
Host smart-f885787a-044a-4c21-8849-8133ca74541e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523413338 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2523413338
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3333866868
Short name T885
Test name
Test status
Simulation time 2075124038 ps
CPU time 2.15 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:19 PM PDT 24
Peak memory 201200 kb
Host smart-d86c1006-d5ba-4579-b81f-add3041244a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333866868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.3333866868
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.116461920
Short name T879
Test name
Test status
Simulation time 2018356661 ps
CPU time 3.46 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:19 PM PDT 24
Peak memory 200668 kb
Host smart-116e228d-5ae7-459c-b4a1-39d56093b58e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116461920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test
.116461920
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2913867213
Short name T816
Test name
Test status
Simulation time 4762222955 ps
CPU time 4.07 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201400 kb
Host smart-238e2c04-49a9-4bbf-9de1-2837dba1d6da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913867213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.2913867213
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3823379272
Short name T878
Test name
Test status
Simulation time 2084257446 ps
CPU time 2.65 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 201316 kb
Host smart-c8a4273f-6e82-4f52-a08b-a5c7db83bbda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823379272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.3823379272
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1446971962
Short name T891
Test name
Test status
Simulation time 42519673980 ps
CPU time 29.52 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:57 PM PDT 24
Peak memory 201448 kb
Host smart-7db7cdbe-d952-4e3a-8e56-3931759a560e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446971962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.1446971962
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1003724082
Short name T834
Test name
Test status
Simulation time 2074220949 ps
CPU time 5.69 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201240 kb
Host smart-4b7202e0-67cf-434f-a39a-2e94044701ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003724082 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1003724082
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3419212907
Short name T357
Test name
Test status
Simulation time 2026129488 ps
CPU time 6.47 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:19 PM PDT 24
Peak memory 201232 kb
Host smart-4aef82e2-da38-4ce9-ad22-acda3e7f60b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419212907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3419212907
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.4163840910
Short name T871
Test name
Test status
Simulation time 2120607447 ps
CPU time 1.04 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 200808 kb
Host smart-72197290-f63d-48f8-81fb-c96b8155918f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163840910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.4163840910
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1425984966
Short name T355
Test name
Test status
Simulation time 10074142800 ps
CPU time 8.23 seconds
Started Mar 28 12:32:15 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 201416 kb
Host smart-c22df21e-686f-463b-aa1d-5c188b845e51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425984966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.1425984966
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.435742261
Short name T845
Test name
Test status
Simulation time 2171911284 ps
CPU time 4.68 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 201428 kb
Host smart-6c4fd394-63cb-434d-8ae8-070dd11f8be3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435742261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_error
s.435742261
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.479503759
Short name T896
Test name
Test status
Simulation time 2712594847 ps
CPU time 1.47 seconds
Started Mar 28 12:32:06 PM PDT 24
Finished Mar 28 12:32:13 PM PDT 24
Peak memory 201400 kb
Host smart-e0b4cea8-7bdf-47d6-9a4b-bd3d23d9e5c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479503759 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.479503759
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3779387539
Short name T842
Test name
Test status
Simulation time 2036424640 ps
CPU time 6.25 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201164 kb
Host smart-88b80f8f-e36a-44f7-a9fc-bc6229512f0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779387539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.3779387539
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2854058331
Short name T809
Test name
Test status
Simulation time 2032118361 ps
CPU time 2.07 seconds
Started Mar 28 12:32:15 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 200604 kb
Host smart-a26d0f25-4d16-43e7-9c65-4bab5e08be5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854058331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.2854058331
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2929598007
Short name T846
Test name
Test status
Simulation time 7281184515 ps
CPU time 15.87 seconds
Started Mar 28 12:32:13 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 201408 kb
Host smart-a9dd809b-c294-49b3-8c6b-4798484210d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929598007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.2929598007
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2777656556
Short name T282
Test name
Test status
Simulation time 2034140224 ps
CPU time 6.29 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:19 PM PDT 24
Peak memory 209492 kb
Host smart-0a4c5be8-c325-40a7-bb78-d78ad6f4c902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777656556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2777656556
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1643186375
Short name T868
Test name
Test status
Simulation time 22324869488 ps
CPU time 26.76 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:36 PM PDT 24
Peak memory 201452 kb
Host smart-03c43db1-db0e-46b8-889b-0647ca40eef9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643186375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.1643186375
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.313387251
Short name T854
Test name
Test status
Simulation time 2116812142 ps
CPU time 6.32 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201272 kb
Host smart-fb487d32-5c29-4c63-97c0-21e0bf8a5869
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313387251 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.313387251
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.227876289
Short name T883
Test name
Test status
Simulation time 2075946222 ps
CPU time 2.29 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:14 PM PDT 24
Peak memory 201280 kb
Host smart-f8afb5ef-8cf5-4fff-8e36-65ee12db4928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227876289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_r
w.227876289
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.545440792
Short name T899
Test name
Test status
Simulation time 2014351699 ps
CPU time 5.4 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 200824 kb
Host smart-0d4af3da-8cd6-4314-bab0-263076f1a9f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545440792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_tes
t.545440792
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1561459310
Short name T26
Test name
Test status
Simulation time 4367765860 ps
CPU time 1.79 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201396 kb
Host smart-710fb3ba-068b-4fea-a1dc-101060f89ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561459310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.1561459310
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3419583899
Short name T864
Test name
Test status
Simulation time 3037141314 ps
CPU time 1.83 seconds
Started Mar 28 12:32:18 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 201420 kb
Host smart-87ea23bb-273f-429f-b500-ca17cffb7caa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419583899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.3419583899
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3287207928
Short name T273
Test name
Test status
Simulation time 42504567732 ps
CPU time 30.3 seconds
Started Mar 28 12:32:17 PM PDT 24
Finished Mar 28 12:32:55 PM PDT 24
Peak memory 201428 kb
Host smart-c533ae70-2a3b-43a3-b017-f36952684875
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287207928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.3287207928
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4052155854
Short name T817
Test name
Test status
Simulation time 2246124420 ps
CPU time 2.34 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201300 kb
Host smart-74fd34a3-2360-4477-b5bd-7aca07576d2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052155854 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.4052155854
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2647558207
Short name T348
Test name
Test status
Simulation time 2100854993 ps
CPU time 2.17 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 201224 kb
Host smart-1d5315d8-4de7-4795-8062-92f5e820a8d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647558207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.2647558207
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3915975831
Short name T828
Test name
Test status
Simulation time 2028851235 ps
CPU time 1.84 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 200724 kb
Host smart-c3342d14-13ad-476b-8b3f-4c3b105a3f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915975831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.3915975831
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3822676925
Short name T888
Test name
Test status
Simulation time 8443974023 ps
CPU time 21.57 seconds
Started Mar 28 12:32:10 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201460 kb
Host smart-79838a42-9951-47c7-bbf1-dfe37509a0fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822676925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.3822676925
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.355839071
Short name T829
Test name
Test status
Simulation time 2090762036 ps
CPU time 5.48 seconds
Started Mar 28 12:32:13 PM PDT 24
Finished Mar 28 12:32:22 PM PDT 24
Peak memory 201304 kb
Host smart-5799f6aa-ff5b-43c5-967f-1656a68f2440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355839071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.355839071
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3640496713
Short name T275
Test name
Test status
Simulation time 22232165019 ps
CPU time 54.14 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:33:11 PM PDT 24
Peak memory 201384 kb
Host smart-a089e13b-3350-43f8-bd82-0cf775af2859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640496713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.3640496713
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3466937989
Short name T826
Test name
Test status
Simulation time 2064956981 ps
CPU time 3.39 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201240 kb
Host smart-ef23940a-3ade-4eee-af7f-b06e369bc3d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466937989 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3466937989
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1284830406
Short name T862
Test name
Test status
Simulation time 2032831983 ps
CPU time 3.28 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 201236 kb
Host smart-6fcad400-e28c-43e2-9b69-b29f6947bd4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284830406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.1284830406
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.3431667876
Short name T819
Test name
Test status
Simulation time 2017097500 ps
CPU time 3.36 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 200708 kb
Host smart-0b70dc0a-59f7-4a85-9a03-625dbb76e9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431667876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.3431667876
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2703893886
Short name T848
Test name
Test status
Simulation time 4526422499 ps
CPU time 17.98 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:44 PM PDT 24
Peak memory 201324 kb
Host smart-568ee806-4cab-4f05-9909-438b8dd65c30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703893886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.2703893886
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.50893446
Short name T897
Test name
Test status
Simulation time 2106205501 ps
CPU time 3.54 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201224 kb
Host smart-11fc3050-46bd-4c78-9911-3434ae49bbc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50893446 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.50893446
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1871358468
Short name T824
Test name
Test status
Simulation time 2191320007 ps
CPU time 1.54 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201356 kb
Host smart-a1d4784d-b43d-4288-8c4c-87eccc04c749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871358468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.1871358468
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.597304715
Short name T843
Test name
Test status
Simulation time 2009698324 ps
CPU time 6.2 seconds
Started Mar 28 12:32:29 PM PDT 24
Finished Mar 28 12:32:35 PM PDT 24
Peak memory 200672 kb
Host smart-82069fe6-fc3d-4fce-aca1-c41ef2ffafc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597304715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_tes
t.597304715
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2531020318
Short name T827
Test name
Test status
Simulation time 4450149533 ps
CPU time 3.74 seconds
Started Mar 28 12:32:31 PM PDT 24
Finished Mar 28 12:32:35 PM PDT 24
Peak memory 201324 kb
Host smart-eb8eded7-f4ea-4652-94eb-90c4c47824f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531020318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.2531020318
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2770890023
Short name T909
Test name
Test status
Simulation time 2098403664 ps
CPU time 6.31 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201268 kb
Host smart-0a37eaed-b8da-484a-8df3-3967fc149402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770890023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.2770890023
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.746419934
Short name T903
Test name
Test status
Simulation time 43896292214 ps
CPU time 31.93 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:57 PM PDT 24
Peak memory 201412 kb
Host smart-2f82a64d-37e4-41f1-8410-6a7913ff3faa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746419934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_tl_intg_err.746419934
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.661254140
Short name T910
Test name
Test status
Simulation time 2045415479 ps
CPU time 6.04 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201336 kb
Host smart-b2b3753f-0d40-4c72-9baf-d526e2ac863c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661254140 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.661254140
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1425637087
Short name T803
Test name
Test status
Simulation time 2013249271 ps
CPU time 5.81 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 200824 kb
Host smart-96be3186-60d2-40e8-b9f2-c0fc4738e61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425637087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.1425637087
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.270460599
Short name T856
Test name
Test status
Simulation time 9838007233 ps
CPU time 7.33 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:34 PM PDT 24
Peak memory 201400 kb
Host smart-e274feac-4684-41d5-95ea-92580fbd7769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270460599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.sysrst_ctrl_same_csr_outstanding.270460599
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.449201255
Short name T851
Test name
Test status
Simulation time 2310178568 ps
CPU time 2.6 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 201192 kb
Host smart-a0fce214-30fb-40f7-b090-157e422a9822
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449201255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_error
s.449201255
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2763962248
Short name T376
Test name
Test status
Simulation time 42435722568 ps
CPU time 111.54 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:34:20 PM PDT 24
Peak memory 201396 kb
Host smart-49b471d3-fa48-4d50-8eb2-31cfa60c65ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763962248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.2763962248
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.379626889
Short name T24
Test name
Test status
Simulation time 2225372528 ps
CPU time 2.44 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201388 kb
Host smart-18d2e37a-bf3d-4a65-afce-4bea5fed2a19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379626889 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.379626889
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1769914511
Short name T358
Test name
Test status
Simulation time 2064770643 ps
CPU time 6.48 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:34 PM PDT 24
Peak memory 201228 kb
Host smart-32c0f987-ac2a-4cbf-a001-c169c077936e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769914511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.1769914511
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3050116158
Short name T847
Test name
Test status
Simulation time 2015819835 ps
CPU time 5.31 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 200812 kb
Host smart-a6939a05-d985-42f5-b15f-6b3ae9ad63d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050116158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3050116158
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.957441410
Short name T18
Test name
Test status
Simulation time 5095986701 ps
CPU time 6.05 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201392 kb
Host smart-ed58fcd9-a3b2-4b47-a7a4-a772fb9001aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957441410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.957441410
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.878867840
Short name T867
Test name
Test status
Simulation time 2097541545 ps
CPU time 5.5 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201328 kb
Host smart-d7c8bec1-2c0e-412b-88ee-8b621cbdcb2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878867840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_error
s.878867840
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3031812214
Short name T283
Test name
Test status
Simulation time 42757912870 ps
CPU time 31.89 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:59 PM PDT 24
Peak memory 201464 kb
Host smart-526d5b72-fd90-45ae-a3bc-1e0e8f972a30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031812214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3031812214
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3840827443
Short name T881
Test name
Test status
Simulation time 2078609774 ps
CPU time 6.07 seconds
Started Mar 28 12:32:30 PM PDT 24
Finished Mar 28 12:32:36 PM PDT 24
Peak memory 201244 kb
Host smart-762a103d-5aec-45b0-a1f8-d612697e85d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840827443 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3840827443
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2425405648
Short name T877
Test name
Test status
Simulation time 2037959883 ps
CPU time 3.32 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201344 kb
Host smart-caac33be-029a-48de-93b5-d7cb1bfc8ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425405648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.2425405648
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2182784588
Short name T822
Test name
Test status
Simulation time 2011636811 ps
CPU time 5.82 seconds
Started Mar 28 12:32:44 PM PDT 24
Finished Mar 28 12:32:50 PM PDT 24
Peak memory 200656 kb
Host smart-0b84f809-a88d-442d-863e-26e1b22a5568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182784588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.2182784588
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.557704771
Short name T19
Test name
Test status
Simulation time 10638947399 ps
CPU time 7.89 seconds
Started Mar 28 12:32:30 PM PDT 24
Finished Mar 28 12:32:38 PM PDT 24
Peak memory 201408 kb
Host smart-996f56e8-45ab-4e88-8750-479086b19dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557704771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.sysrst_ctrl_same_csr_outstanding.557704771
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.47350162
Short name T861
Test name
Test status
Simulation time 2026365321 ps
CPU time 7.31 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 209496 kb
Host smart-d16e846c-510d-476b-9236-4f01db2b9d79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47350162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors
.47350162
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3541815021
Short name T887
Test name
Test status
Simulation time 45007767096 ps
CPU time 11.72 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:39 PM PDT 24
Peak memory 201420 kb
Host smart-e11b2114-8e5f-4d5e-bdbb-8dcf0c94f9e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541815021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.3541815021
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.380813700
Short name T913
Test name
Test status
Simulation time 2065847028 ps
CPU time 5.94 seconds
Started Mar 28 12:32:30 PM PDT 24
Finished Mar 28 12:32:36 PM PDT 24
Peak memory 201324 kb
Host smart-6252abf7-d5b5-468a-b54d-7b80f4f2e317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380813700 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.380813700
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.848647943
Short name T914
Test name
Test status
Simulation time 2037260418 ps
CPU time 1.79 seconds
Started Mar 28 12:33:05 PM PDT 24
Finished Mar 28 12:33:07 PM PDT 24
Peak memory 200708 kb
Host smart-83b0306e-535d-4269-81b4-e7eb3180a8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848647943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_tes
t.848647943
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.218933873
Short name T858
Test name
Test status
Simulation time 7735661066 ps
CPU time 6.17 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201464 kb
Host smart-b23eb43a-e9e0-4cbb-b61b-76af01660886
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218933873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.sysrst_ctrl_same_csr_outstanding.218933873
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.169280750
Short name T272
Test name
Test status
Simulation time 2059973362 ps
CPU time 6.89 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 201380 kb
Host smart-73970f38-f2ca-4f23-9b4e-c826ba54e4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169280750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_error
s.169280750
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2788361051
Short name T818
Test name
Test status
Simulation time 22448649122 ps
CPU time 16.43 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:41 PM PDT 24
Peak memory 201436 kb
Host smart-21101e66-6e51-4f17-936d-a799dc6c1a52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788361051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2788361051
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3402448813
Short name T839
Test name
Test status
Simulation time 2504438347 ps
CPU time 8.07 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201376 kb
Host smart-c3ee6626-0d3a-449f-9356-1ec8326e8698
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402448813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.3402448813
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3353552657
Short name T354
Test name
Test status
Simulation time 74113146156 ps
CPU time 181.47 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:35:13 PM PDT 24
Peak memory 201364 kb
Host smart-312b4942-71bd-4050-93d3-e063fbaff991
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353552657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.3353552657
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.4187896051
Short name T859
Test name
Test status
Simulation time 6061445187 ps
CPU time 8.23 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:35 PM PDT 24
Peak memory 201224 kb
Host smart-94180728-ee52-4bac-b6bb-9d0e048bed12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187896051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.4187896051
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.57335861
Short name T889
Test name
Test status
Simulation time 2108174671 ps
CPU time 2.2 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:21 PM PDT 24
Peak memory 201240 kb
Host smart-2101ba5c-afdc-41bc-a4e8-c2f445dc6c2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57335861 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.57335861
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3609213157
Short name T346
Test name
Test status
Simulation time 2043276522 ps
CPU time 6.26 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201268 kb
Host smart-ce4021fe-9f0a-4986-bcd6-4a024bae50ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609213157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.3609213157
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2011279228
Short name T812
Test name
Test status
Simulation time 2019562798 ps
CPU time 3.24 seconds
Started Mar 28 12:32:31 PM PDT 24
Finished Mar 28 12:32:34 PM PDT 24
Peak memory 200652 kb
Host smart-7ff2dc01-d464-428a-91e3-7127ea49e8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011279228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.2011279228
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.472935025
Short name T863
Test name
Test status
Simulation time 4725404781 ps
CPU time 11.43 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:40 PM PDT 24
Peak memory 201340 kb
Host smart-920a545e-5f3a-4cab-939b-09d53ccfce1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472935025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
sysrst_ctrl_same_csr_outstanding.472935025
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.64095404
Short name T833
Test name
Test status
Simulation time 2438546028 ps
CPU time 1.91 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201336 kb
Host smart-bb13ea72-2c15-4d38-929c-a80826fc67d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64095404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.64095404
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3808834905
Short name T285
Test name
Test status
Simulation time 42499434828 ps
CPU time 115.81 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:34:19 PM PDT 24
Peak memory 201416 kb
Host smart-40fee9a2-c65f-449a-8bc0-1d11990756c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808834905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.3808834905
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1660181920
Short name T810
Test name
Test status
Simulation time 2020066433 ps
CPU time 3.08 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 200744 kb
Host smart-a89f8ea9-e8ca-4393-8dfe-a4751fb1ebec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660181920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.1660181920
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1670904367
Short name T798
Test name
Test status
Simulation time 2042172887 ps
CPU time 2 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 200820 kb
Host smart-95a74ff5-1a93-4c64-a876-bed93e421b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670904367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.1670904367
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2760337843
Short name T844
Test name
Test status
Simulation time 2012178704 ps
CPU time 5.66 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 200652 kb
Host smart-8d47e0d4-3615-4c27-a7cf-b4a20a05acea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760337843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.2760337843
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.4195680223
Short name T860
Test name
Test status
Simulation time 2013722802 ps
CPU time 3.19 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 200696 kb
Host smart-cd33a65a-84c1-4d41-ae44-11c5960a34b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195680223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.4195680223
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.1107250644
Short name T797
Test name
Test status
Simulation time 2045217936 ps
CPU time 2 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 200704 kb
Host smart-0306f98c-382b-434e-ab52-825767bcbcfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107250644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.1107250644
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2271377906
Short name T820
Test name
Test status
Simulation time 2012285265 ps
CPU time 5.83 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:34 PM PDT 24
Peak memory 200784 kb
Host smart-82c1c0d5-9b86-4aa7-a687-922f627f74db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271377906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.2271377906
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3225774042
Short name T807
Test name
Test status
Simulation time 2036638276 ps
CPU time 1.92 seconds
Started Mar 28 12:32:29 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 200708 kb
Host smart-63256607-b0c5-4d01-b9d4-c770e59eadbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225774042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.3225774042
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.4081245848
Short name T811
Test name
Test status
Simulation time 2021282359 ps
CPU time 3.2 seconds
Started Mar 28 12:32:31 PM PDT 24
Finished Mar 28 12:32:34 PM PDT 24
Peak memory 200728 kb
Host smart-cf673a47-f0a6-4dc9-a539-2b0f2274c121
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081245848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.4081245848
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.652068837
Short name T874
Test name
Test status
Simulation time 2019400465 ps
CPU time 3.24 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 200684 kb
Host smart-26235448-0d38-4297-b993-2cfa8881c989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652068837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_tes
t.652068837
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4274606365
Short name T799
Test name
Test status
Simulation time 2020583138 ps
CPU time 3.18 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 200820 kb
Host smart-fa9fe1ae-6ab6-448f-941c-b8589416465e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274606365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.4274606365
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.1854771563
Short name T349
Test name
Test status
Simulation time 2442167813 ps
CPU time 3.29 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201008 kb
Host smart-1c1eb6e4-fe38-492a-90d1-c8125667697d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854771563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_aliasing.1854771563
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2892382050
Short name T341
Test name
Test status
Simulation time 33783809734 ps
CPU time 25.07 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:49 PM PDT 24
Peak memory 201424 kb
Host smart-9ca61b81-1b52-46a6-b357-a4faf6494cdd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892382050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.2892382050
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.269069632
Short name T347
Test name
Test status
Simulation time 6076230584 ps
CPU time 4.48 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201268 kb
Host smart-c6818640-193b-4c3c-918d-4628f1f1f121
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269069632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_hw_reset.269069632
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3983426032
Short name T898
Test name
Test status
Simulation time 2148512659 ps
CPU time 4.31 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201400 kb
Host smart-f650f8b1-ed24-4f37-b0ff-794dda6068fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983426032 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3983426032
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2544167517
Short name T815
Test name
Test status
Simulation time 2410174696 ps
CPU time 1.26 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 201240 kb
Host smart-c26bc862-1dd3-4646-b0c1-59de7f423b9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544167517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.2544167517
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1578465554
Short name T813
Test name
Test status
Simulation time 2095250641 ps
CPU time 1.12 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:11 PM PDT 24
Peak memory 200660 kb
Host smart-fb3b5c19-cfc1-4887-a553-22b108ac77fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578465554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.1578465554
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2786398795
Short name T838
Test name
Test status
Simulation time 7276692191 ps
CPU time 6.02 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 200976 kb
Host smart-cbd22697-a305-420c-8678-2f3676516e9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786398795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.2786398795
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.375327078
Short name T286
Test name
Test status
Simulation time 2100752352 ps
CPU time 3.86 seconds
Started Mar 28 12:32:18 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201200 kb
Host smart-c173db5c-29e2-487f-ab51-91d94ac6fb70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375327078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors
.375327078
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1589617201
Short name T375
Test name
Test status
Simulation time 42417817417 ps
CPU time 67.48 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:33:17 PM PDT 24
Peak memory 201424 kb
Host smart-8fc9fc34-acc6-40c6-8caf-596d1f5bde20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589617201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.1589617201
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.4119123117
Short name T890
Test name
Test status
Simulation time 2013230783 ps
CPU time 6.05 seconds
Started Mar 28 12:32:34 PM PDT 24
Finished Mar 28 12:32:40 PM PDT 24
Peak memory 200696 kb
Host smart-8da6923b-10a2-420b-a1f3-59fea2b7fef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119123117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.4119123117
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2806806299
Short name T831
Test name
Test status
Simulation time 2032146642 ps
CPU time 1.91 seconds
Started Mar 28 12:32:32 PM PDT 24
Finished Mar 28 12:32:34 PM PDT 24
Peak memory 200680 kb
Host smart-6fe335a1-ca13-4ef7-825c-48a266a2afa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806806299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2806806299
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3584844775
Short name T849
Test name
Test status
Simulation time 2012579278 ps
CPU time 5.49 seconds
Started Mar 28 12:32:39 PM PDT 24
Finished Mar 28 12:32:44 PM PDT 24
Peak memory 200724 kb
Host smart-43545588-846e-44f8-9338-53f312068782
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584844775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.3584844775
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.479147396
Short name T801
Test name
Test status
Simulation time 2010669505 ps
CPU time 5.61 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 200728 kb
Host smart-d87cbfa4-8496-424d-bd68-857d67b473cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479147396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_tes
t.479147396
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2438056557
Short name T800
Test name
Test status
Simulation time 2010907958 ps
CPU time 5.2 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 200636 kb
Host smart-6079c484-e3eb-4326-ac06-bc41b19f46d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438056557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.2438056557
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3151774954
Short name T911
Test name
Test status
Simulation time 2014339861 ps
CPU time 5.82 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 200664 kb
Host smart-3ffe966e-73a3-4509-87fd-a4aeb5e641a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151774954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.3151774954
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.469379547
Short name T894
Test name
Test status
Simulation time 2129068825 ps
CPU time 1.16 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 200744 kb
Host smart-52bc05d9-7310-486e-b559-3eb386719833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469379547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_tes
t.469379547
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1219512314
Short name T907
Test name
Test status
Simulation time 2032418236 ps
CPU time 1.77 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 200572 kb
Host smart-3ac8b88a-54c3-41e0-b75c-ed5c67c95d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219512314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.1219512314
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.116575882
Short name T805
Test name
Test status
Simulation time 2010645230 ps
CPU time 6.03 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:34 PM PDT 24
Peak memory 200768 kb
Host smart-ee848fa5-bd73-4df3-a2bc-b8ee9e420b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116575882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_tes
t.116575882
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3007436257
Short name T866
Test name
Test status
Simulation time 2045194878 ps
CPU time 1.93 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 200696 kb
Host smart-94c6a2c6-6754-4919-8c13-a11702489aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007436257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.3007436257
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1715740
Short name T345
Test name
Test status
Simulation time 2194477753 ps
CPU time 5.65 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 201528 kb
Host smart-384f8242-70c7-477a-9811-426baeefc3bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_cs
r_aliasing.1715740
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1718423227
Short name T340
Test name
Test status
Simulation time 40840556112 ps
CPU time 46.35 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:32:58 PM PDT 24
Peak memory 201388 kb
Host smart-da36ae31-213d-4561-8085-89acc0a78026
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718423227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.1718423227
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1403611537
Short name T836
Test name
Test status
Simulation time 4070361651 ps
CPU time 3.2 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 201312 kb
Host smart-215a1099-6d80-4617-a3c5-cde134b69d90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403611537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.1403611537
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.669129058
Short name T25
Test name
Test status
Simulation time 2073185769 ps
CPU time 3.47 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201256 kb
Host smart-9c42818e-ca20-4cd1-8aeb-9da981610913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669129058 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.669129058
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3084571666
Short name T279
Test name
Test status
Simulation time 2053179211 ps
CPU time 3.49 seconds
Started Mar 28 12:32:17 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 201160 kb
Host smart-9e12af5d-8810-44d0-9b4a-7018c9beabed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084571666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3084571666
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.526254732
Short name T804
Test name
Test status
Simulation time 2011193197 ps
CPU time 5.82 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 200784 kb
Host smart-e0ed8229-43f6-484e-8673-ddda896b5397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526254732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test
.526254732
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3551669311
Short name T906
Test name
Test status
Simulation time 7516205382 ps
CPU time 6.55 seconds
Started Mar 28 12:32:20 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201512 kb
Host smart-8eec739e-aa42-40d3-8d36-1d8df8a5111e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551669311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_same_csr_outstanding.3551669311
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1357940909
Short name T869
Test name
Test status
Simulation time 2521098217 ps
CPU time 4.28 seconds
Started Mar 28 12:32:21 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 201380 kb
Host smart-1a164ce4-7509-456b-a5e2-bdf146287f13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357940909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.1357940909
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.713789652
Short name T284
Test name
Test status
Simulation time 42381818363 ps
CPU time 60.4 seconds
Started Mar 28 12:32:19 PM PDT 24
Finished Mar 28 12:33:22 PM PDT 24
Peak memory 201416 kb
Host smart-cfbbc259-2a85-43a8-8693-bd70c3f9309a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713789652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_tl_intg_err.713789652
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2770730196
Short name T905
Test name
Test status
Simulation time 2047070734 ps
CPU time 1.54 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 200676 kb
Host smart-2f5f9f22-e714-4c2c-b44b-62738c925c99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770730196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.2770730196
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.880141735
Short name T886
Test name
Test status
Simulation time 2030108091 ps
CPU time 3.05 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 200720 kb
Host smart-b19e4c35-504d-4473-ba36-a0737bab6ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880141735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_tes
t.880141735
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2147565513
Short name T855
Test name
Test status
Simulation time 2030278657 ps
CPU time 1.92 seconds
Started Mar 28 12:32:27 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 200580 kb
Host smart-0989b14b-16cc-4242-8667-fa96c9910b6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147565513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.2147565513
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3146218774
Short name T835
Test name
Test status
Simulation time 2014109160 ps
CPU time 5.76 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 200664 kb
Host smart-adf21172-d492-4ef3-914c-eb77c5d97422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146218774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.3146218774
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2690194289
Short name T795
Test name
Test status
Simulation time 2012117342 ps
CPU time 5.78 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:34 PM PDT 24
Peak memory 200640 kb
Host smart-eca8ac17-d2ea-41b0-a723-44bf827b08ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690194289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.2690194289
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.4221041445
Short name T796
Test name
Test status
Simulation time 2018126354 ps
CPU time 3.17 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 200600 kb
Host smart-d9ea6199-e5df-4e75-8efc-d46122927064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221041445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.4221041445
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.762612466
Short name T916
Test name
Test status
Simulation time 2010282400 ps
CPU time 5.97 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 200664 kb
Host smart-243af863-e0dc-4c01-8e9a-c03d8e75ae85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762612466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_tes
t.762612466
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1266027321
Short name T808
Test name
Test status
Simulation time 2049101353 ps
CPU time 1.62 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 200696 kb
Host smart-2e41594a-8467-4d9a-912c-40e04a6a7851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266027321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.1266027321
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3987125075
Short name T902
Test name
Test status
Simulation time 2017513423 ps
CPU time 6.06 seconds
Started Mar 28 12:32:18 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 200592 kb
Host smart-f6f9e220-934a-4cec-a697-fdfd207853fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987125075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.3987125075
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.4147100134
Short name T870
Test name
Test status
Simulation time 2032772162 ps
CPU time 1.63 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 200660 kb
Host smart-4fc4eaa8-9ca7-4f66-ad1b-d4350cc44bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147100134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.4147100134
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.793564665
Short name T873
Test name
Test status
Simulation time 2125847782 ps
CPU time 2.17 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 201320 kb
Host smart-8cbcd52f-0aae-4573-abe9-b65314d0f643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793564665 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.793564665
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2017641327
Short name T901
Test name
Test status
Simulation time 2050305638 ps
CPU time 5.8 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201160 kb
Host smart-d66b3170-bace-49d1-a8ed-6c23e6911d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017641327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.2017641327
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.451093689
Short name T857
Test name
Test status
Simulation time 2047057501 ps
CPU time 1.74 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:18 PM PDT 24
Peak memory 200768 kb
Host smart-fe078346-7d9e-4792-855a-35fcc145c105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451093689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test
.451093689
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2403586863
Short name T852
Test name
Test status
Simulation time 4631208687 ps
CPU time 3.79 seconds
Started Mar 28 12:32:09 PM PDT 24
Finished Mar 28 12:32:13 PM PDT 24
Peak memory 201444 kb
Host smart-016b959e-41c6-4b76-93e0-7625d061754d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403586863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.2403586863
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2741275893
Short name T915
Test name
Test status
Simulation time 2035044923 ps
CPU time 7.57 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 209480 kb
Host smart-71442fa8-723a-4ad3-83c6-1ac287374020
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741275893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.2741275893
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.3126188789
Short name T287
Test name
Test status
Simulation time 42477293974 ps
CPU time 102.32 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:34:00 PM PDT 24
Peak memory 201512 kb
Host smart-ae2e574f-1bb6-4da8-9c80-6a59ccaa935f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126188789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.3126188789
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.987108231
Short name T876
Test name
Test status
Simulation time 2278840675 ps
CPU time 1.88 seconds
Started Mar 28 12:32:24 PM PDT 24
Finished Mar 28 12:32:28 PM PDT 24
Peak memory 209580 kb
Host smart-dc50fda0-5d74-465c-bfaf-628c19813a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987108231 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.987108231
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.190766554
Short name T343
Test name
Test status
Simulation time 2075831587 ps
CPU time 2.08 seconds
Started Mar 28 12:32:04 PM PDT 24
Finished Mar 28 12:32:06 PM PDT 24
Peak memory 201168 kb
Host smart-e1b9b563-11b8-486e-ab38-1514dd8bc786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190766554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw
.190766554
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.4062587356
Short name T830
Test name
Test status
Simulation time 2064341355 ps
CPU time 1.26 seconds
Started Mar 28 12:32:28 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 200696 kb
Host smart-b178cbcd-d8bc-4898-94bf-ba262993be7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062587356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.4062587356
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3019485823
Short name T356
Test name
Test status
Simulation time 8551400149 ps
CPU time 6.36 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:25 PM PDT 24
Peak memory 201276 kb
Host smart-6b08a821-7d91-472d-9740-7d3bd2d2a579
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019485823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.3019485823
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.624082771
Short name T895
Test name
Test status
Simulation time 2171841493 ps
CPU time 3.83 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:31 PM PDT 24
Peak memory 201404 kb
Host smart-d0c2a297-1237-4c29-a0aa-8b3e14811cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624082771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors
.624082771
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.77183380
Short name T853
Test name
Test status
Simulation time 42364719437 ps
CPU time 110.2 seconds
Started Mar 28 12:32:11 PM PDT 24
Finished Mar 28 12:34:02 PM PDT 24
Peak memory 201388 kb
Host smart-50ad072e-1163-4eef-9d05-5808636c4e80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77183380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_tl_intg_err.77183380
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3496652082
Short name T280
Test name
Test status
Simulation time 2158771845 ps
CPU time 1.7 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:27 PM PDT 24
Peak memory 201384 kb
Host smart-31a10336-6898-4e3a-907d-3552b3cbaf26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496652082 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3496652082
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3640242024
Short name T865
Test name
Test status
Simulation time 2063345927 ps
CPU time 5.69 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 201256 kb
Host smart-77db2bc6-f568-4328-a315-12e2d73570ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640242024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.3640242024
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.621267209
Short name T837
Test name
Test status
Simulation time 2046466611 ps
CPU time 1.82 seconds
Started Mar 28 12:32:25 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 200684 kb
Host smart-55fd441d-efbd-4300-b97e-c150df5b2688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621267209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test
.621267209
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.3066329036
Short name T893
Test name
Test status
Simulation time 6789240728 ps
CPU time 5.78 seconds
Started Mar 28 12:32:26 PM PDT 24
Finished Mar 28 12:32:33 PM PDT 24
Peak memory 201444 kb
Host smart-3c524300-c214-417e-9ac1-162d717f3c14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066329036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.3066329036
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2508116985
Short name T904
Test name
Test status
Simulation time 2034783737 ps
CPU time 7.43 seconds
Started Mar 28 12:32:14 PM PDT 24
Finished Mar 28 12:32:26 PM PDT 24
Peak memory 201304 kb
Host smart-15f4faba-b240-42fb-80a8-5073e38dfb9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508116985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.2508116985
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.965845432
Short name T806
Test name
Test status
Simulation time 23151820088 ps
CPU time 6 seconds
Started Mar 28 12:32:29 PM PDT 24
Finished Mar 28 12:32:35 PM PDT 24
Peak memory 201404 kb
Host smart-5d261c9b-cccb-49cc-9241-7c8f19559db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965845432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_tl_intg_err.965845432
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.4090726628
Short name T882
Test name
Test status
Simulation time 2148831085 ps
CPU time 2.26 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:22 PM PDT 24
Peak memory 201276 kb
Host smart-c5dea7e5-9c5a-4d9f-99f6-c0cffbd16993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090726628 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.4090726628
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2834814870
Short name T352
Test name
Test status
Simulation time 2051068158 ps
CPU time 6.18 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:19 PM PDT 24
Peak memory 201240 kb
Host smart-c5ad12b2-fa75-4b2e-ae63-de7d0a9ce561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834814870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.2834814870
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.1151969552
Short name T823
Test name
Test status
Simulation time 2017274980 ps
CPU time 3.26 seconds
Started Mar 28 12:32:17 PM PDT 24
Finished Mar 28 12:32:23 PM PDT 24
Peak memory 200732 kb
Host smart-dcdc353c-76e6-46f5-b3f7-9459b8e80ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151969552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.1151969552
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2898071860
Short name T17
Test name
Test status
Simulation time 8814546124 ps
CPU time 24.66 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:49 PM PDT 24
Peak memory 201428 kb
Host smart-cc3bf99b-313e-4b64-9a76-f9145b7c4379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898071860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.2898071860
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2607990382
Short name T281
Test name
Test status
Simulation time 2264651525 ps
CPU time 5.13 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:29 PM PDT 24
Peak memory 201408 kb
Host smart-d2958f64-cf38-49de-af42-f6d818615bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607990382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.2607990382
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2126686690
Short name T884
Test name
Test status
Simulation time 22251668961 ps
CPU time 29.57 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:54 PM PDT 24
Peak memory 201412 kb
Host smart-bd19055f-fedf-47a2-8f4a-85c534404deb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126686690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.2126686690
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2821465546
Short name T802
Test name
Test status
Simulation time 2066277309 ps
CPU time 6.29 seconds
Started Mar 28 12:31:57 PM PDT 24
Finished Mar 28 12:32:04 PM PDT 24
Peak memory 201200 kb
Host smart-c2807f56-a96c-42b9-9bdb-bbdf73daa97d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821465546 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2821465546
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3368475277
Short name T900
Test name
Test status
Simulation time 2036169923 ps
CPU time 4.88 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:22 PM PDT 24
Peak memory 201200 kb
Host smart-4913a641-550e-4aca-9db3-49b83ec58bd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368475277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.3368475277
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.2039408943
Short name T825
Test name
Test status
Simulation time 2014928139 ps
CPU time 5.79 seconds
Started Mar 28 12:32:22 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 200604 kb
Host smart-729a34af-93be-475a-8731-01d9724b40d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039408943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.2039408943
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.1936275314
Short name T850
Test name
Test status
Simulation time 5060293113 ps
CPU time 6.79 seconds
Started Mar 28 12:32:23 PM PDT 24
Finished Mar 28 12:32:32 PM PDT 24
Peak memory 201412 kb
Host smart-31d8b4a3-f05c-4a15-891a-434b6cf59113
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936275314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.1936275314
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3318682074
Short name T271
Test name
Test status
Simulation time 2186818649 ps
CPU time 3.91 seconds
Started Mar 28 12:32:16 PM PDT 24
Finished Mar 28 12:32:24 PM PDT 24
Peak memory 209564 kb
Host smart-cf7a9828-41b7-4886-b95c-c10dd61e98ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318682074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.3318682074
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1053016489
Short name T880
Test name
Test status
Simulation time 22340918450 ps
CPU time 15.36 seconds
Started Mar 28 12:32:12 PM PDT 24
Finished Mar 28 12:32:30 PM PDT 24
Peak memory 201412 kb
Host smart-dadd60ce-4495-4bd2-9258-a8bacd441e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053016489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.1053016489
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.547986780
Short name T112
Test name
Test status
Simulation time 3207815545 ps
CPU time 1.85 seconds
Started Mar 28 12:54:53 PM PDT 24
Finished Mar 28 12:54:55 PM PDT 24
Peak memory 201920 kb
Host smart-f1c12ddb-66ce-44ea-805a-4cc5d84216f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547986780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.547986780
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.620407445
Short name T255
Test name
Test status
Simulation time 68745150906 ps
CPU time 186.3 seconds
Started Mar 28 12:54:44 PM PDT 24
Finished Mar 28 12:57:50 PM PDT 24
Peak memory 202036 kb
Host smart-36db562b-98c9-46a7-bb0b-8a4af4074622
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620407445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_combo_detect.620407445
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1491760709
Short name T521
Test name
Test status
Simulation time 2430433110 ps
CPU time 6.75 seconds
Started Mar 28 12:54:52 PM PDT 24
Finished Mar 28 12:54:59 PM PDT 24
Peak memory 201856 kb
Host smart-a6851752-3047-4bef-9001-5773e08f0900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491760709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.1491760709
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2906483559
Short name T236
Test name
Test status
Simulation time 2510683871 ps
CPU time 7.29 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 201920 kb
Host smart-e5bf2285-0e16-4487-bfdb-b0e5ff4e66b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906483559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2906483559
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.806365489
Short name T579
Test name
Test status
Simulation time 3143332801 ps
CPU time 8.9 seconds
Started Mar 28 12:54:54 PM PDT 24
Finished Mar 28 12:55:03 PM PDT 24
Peak memory 201924 kb
Host smart-6cf65e15-c8f0-4ea6-be51-6e9779c1e379
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806365489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ec_pwr_on_rst.806365489
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.527155719
Short name T655
Test name
Test status
Simulation time 3342240203 ps
CPU time 2.26 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:52 PM PDT 24
Peak memory 201940 kb
Host smart-2d690d2c-95d9-48a2-94b3-0d326c11594d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527155719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_edge_detect.527155719
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3699832981
Short name T496
Test name
Test status
Simulation time 2607363474 ps
CPU time 7.62 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 201916 kb
Host smart-8d4eda40-e2d2-4a23-8135-525849c86716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699832981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.3699832981
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1702211139
Short name T424
Test name
Test status
Simulation time 2448486727 ps
CPU time 3.82 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:53 PM PDT 24
Peak memory 201908 kb
Host smart-f5d503f0-1f81-4316-8c01-bc3716a1fa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702211139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1702211139
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.4022481203
Short name T300
Test name
Test status
Simulation time 2137281773 ps
CPU time 6 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:55 PM PDT 24
Peak memory 201856 kb
Host smart-47303a0a-af87-4261-80fc-05ae7ddccef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022481203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.4022481203
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1235919709
Short name T560
Test name
Test status
Simulation time 2527392835 ps
CPU time 2.29 seconds
Started Mar 28 12:54:54 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 201964 kb
Host smart-4a18e874-e892-49e0-90a9-49325b999a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235919709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.1235919709
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.1114273454
Short name T274
Test name
Test status
Simulation time 22011803799 ps
CPU time 60.62 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:55:50 PM PDT 24
Peak memory 221768 kb
Host smart-805749e3-0a0c-4c66-8f6a-c43c76ca9745
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114273454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.1114273454
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.3843835181
Short name T555
Test name
Test status
Simulation time 2115993587 ps
CPU time 4.99 seconds
Started Mar 28 12:54:46 PM PDT 24
Finished Mar 28 12:54:51 PM PDT 24
Peak memory 201876 kb
Host smart-ea9f8439-beeb-4f69-bb48-d6e4798d66d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843835181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.3843835181
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.269411554
Short name T140
Test name
Test status
Simulation time 14535197075 ps
CPU time 18.61 seconds
Started Mar 28 12:54:52 PM PDT 24
Finished Mar 28 12:55:11 PM PDT 24
Peak memory 201868 kb
Host smart-b11bbc09-0925-48c0-b4ba-c61ce2d66554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269411554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_str
ess_all.269411554
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.693717368
Short name T330
Test name
Test status
Simulation time 96163747177 ps
CPU time 65.77 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 210604 kb
Host smart-88b57fbd-fe3e-4a6a-abb7-066184e60fc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693717368 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.693717368
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1561420143
Short name T56
Test name
Test status
Simulation time 2518833108 ps
CPU time 1.94 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:51 PM PDT 24
Peak memory 201936 kb
Host smart-70bdf3ef-067f-4ccc-ac7e-eb2053e78607
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561420143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.1561420143
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.506052827
Short name T451
Test name
Test status
Simulation time 2019841884 ps
CPU time 3.2 seconds
Started Mar 28 12:54:53 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 202020 kb
Host smart-a9b088ea-157d-488c-b424-5f8d847c15a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506052827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test
.506052827
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.195972867
Short name T625
Test name
Test status
Simulation time 203463402293 ps
CPU time 125.18 seconds
Started Mar 28 12:54:47 PM PDT 24
Finished Mar 28 12:56:53 PM PDT 24
Peak memory 202000 kb
Host smart-ef2e1bab-0449-491d-a730-601495bb5fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195972867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.195972867
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2519544609
Short name T631
Test name
Test status
Simulation time 116277492919 ps
CPU time 140.21 seconds
Started Mar 28 12:54:50 PM PDT 24
Finished Mar 28 12:57:10 PM PDT 24
Peak memory 202116 kb
Host smart-49b11a26-d904-4ff4-9c37-c9c337e5b082
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519544609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.2519544609
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1735273527
Short name T734
Test name
Test status
Simulation time 2392394739 ps
CPU time 3.6 seconds
Started Mar 28 12:54:51 PM PDT 24
Finished Mar 28 12:54:55 PM PDT 24
Peak memory 201936 kb
Host smart-479cde32-3136-4eca-b7f3-0c4d9940bfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735273527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1735273527
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3039073430
Short name T436
Test name
Test status
Simulation time 2554968077 ps
CPU time 2.08 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 201836 kb
Host smart-31252374-6bbd-43d9-9a6e-b23932a2a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039073430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3039073430
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2669042300
Short name T383
Test name
Test status
Simulation time 154780133410 ps
CPU time 99.65 seconds
Started Mar 28 12:54:45 PM PDT 24
Finished Mar 28 12:56:25 PM PDT 24
Peak memory 202148 kb
Host smart-c6d0e1d0-34b4-4a9f-ba30-b7a2aecae364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669042300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.2669042300
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3158195364
Short name T512
Test name
Test status
Simulation time 4390450378 ps
CPU time 6.18 seconds
Started Mar 28 12:54:43 PM PDT 24
Finished Mar 28 12:54:50 PM PDT 24
Peak memory 201908 kb
Host smart-d4890d0d-3f30-4ee4-b484-f6829437d398
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158195364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.3158195364
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.679776598
Short name T607
Test name
Test status
Simulation time 2637346089 ps
CPU time 2.37 seconds
Started Mar 28 12:54:46 PM PDT 24
Finished Mar 28 12:54:48 PM PDT 24
Peak memory 201900 kb
Host smart-3245ae94-be8d-46a2-9099-08b91ac89534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679776598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.679776598
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2410428669
Short name T15
Test name
Test status
Simulation time 2470363089 ps
CPU time 8.05 seconds
Started Mar 28 12:54:48 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 201980 kb
Host smart-e1ba28dd-7ce8-4b4b-9aab-79cedf2873cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410428669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2410428669
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1552235768
Short name T600
Test name
Test status
Simulation time 2190893582 ps
CPU time 0.99 seconds
Started Mar 28 12:55:03 PM PDT 24
Finished Mar 28 12:55:05 PM PDT 24
Peak memory 201832 kb
Host smart-fb9610ed-81f5-451e-ac38-beb330e3f7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552235768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1552235768
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3196372368
Short name T693
Test name
Test status
Simulation time 2536456444 ps
CPU time 2.34 seconds
Started Mar 28 12:54:52 PM PDT 24
Finished Mar 28 12:54:54 PM PDT 24
Peak memory 201872 kb
Host smart-bdce2edd-8097-4c40-b867-6a14b96a2231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196372368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.3196372368
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.3500834138
Short name T108
Test name
Test status
Simulation time 2126884275 ps
CPU time 2.04 seconds
Started Mar 28 12:54:45 PM PDT 24
Finished Mar 28 12:54:47 PM PDT 24
Peak memory 201836 kb
Host smart-e84c33d9-3383-4740-bfae-c395f403fdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500834138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.3500834138
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.259113498
Short name T63
Test name
Test status
Simulation time 12170903589 ps
CPU time 5.31 seconds
Started Mar 28 12:54:57 PM PDT 24
Finished Mar 28 12:55:04 PM PDT 24
Peak memory 201848 kb
Host smart-f35a8857-772b-408b-ab09-f637c9324643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259113498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_str
ess_all.259113498
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3104167731
Short name T708
Test name
Test status
Simulation time 3234179865 ps
CPU time 7.07 seconds
Started Mar 28 12:54:47 PM PDT 24
Finished Mar 28 12:54:54 PM PDT 24
Peak memory 201952 kb
Host smart-770892c6-ba1f-426e-83fb-7540f8e2594c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104167731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.3104167731
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.3612344163
Short name T775
Test name
Test status
Simulation time 2030209561 ps
CPU time 1.9 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 202020 kb
Host smart-a7930146-ae0d-40ec-873f-83a5abde1035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612344163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.3612344163
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.4072329364
Short name T569
Test name
Test status
Simulation time 73042980523 ps
CPU time 181.57 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:58:08 PM PDT 24
Peak memory 202052 kb
Host smart-744c24dc-860c-4ced-8d66-10e1b8400b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072329364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.4
072329364
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.844453699
Short name T96
Test name
Test status
Simulation time 147635570185 ps
CPU time 396.42 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 01:01:43 PM PDT 24
Peak memory 202148 kb
Host smart-0ae848ab-7b26-4a73-89d5-4bd45c2da77d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844453699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_combo_detect.844453699
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1506051091
Short name T229
Test name
Test status
Simulation time 52094543668 ps
CPU time 33.05 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:38 PM PDT 24
Peak memory 202260 kb
Host smart-592f2f22-22c2-4223-9d4a-52681a9d7bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506051091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.1506051091
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1463467660
Short name T338
Test name
Test status
Simulation time 3327483727 ps
CPU time 2.85 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 201900 kb
Host smart-719d05ca-1c67-4670-beab-b7122e83ccb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463467660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.1463467660
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.2719339873
Short name T205
Test name
Test status
Simulation time 5812835003 ps
CPU time 3.03 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 201920 kb
Host smart-4e71b9f2-f326-47f6-bf4b-aa8389750896
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719339873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.2719339873
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2783112825
Short name T779
Test name
Test status
Simulation time 2651305275 ps
CPU time 1.46 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 201872 kb
Host smart-e38a05de-c222-47eb-abe9-ba9b85ad0333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783112825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.2783112825
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.2727329674
Short name T565
Test name
Test status
Simulation time 2559565024 ps
CPU time 1.27 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 201876 kb
Host smart-a75c0ee3-87e7-4728-a38c-a24a9e92630a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727329674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.2727329674
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3245597605
Short name T48
Test name
Test status
Simulation time 2256505086 ps
CPU time 6.61 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:55:22 PM PDT 24
Peak memory 201928 kb
Host smart-ee0c373d-7bb3-498e-a915-9e5e5f1a56e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245597605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3245597605
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2151893785
Short name T170
Test name
Test status
Simulation time 2664633612 ps
CPU time 1.17 seconds
Started Mar 28 12:55:03 PM PDT 24
Finished Mar 28 12:55:05 PM PDT 24
Peak memory 201972 kb
Host smart-0a4e8b60-b763-40ec-9281-38e3ad910346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151893785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.2151893785
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.1221073644
Short name T427
Test name
Test status
Simulation time 2114521391 ps
CPU time 6.01 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 201824 kb
Host smart-68b4e7eb-8db9-4acf-b0da-984a1a24a9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221073644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.1221073644
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.728824852
Short name T438
Test name
Test status
Simulation time 9640875544 ps
CPU time 24.43 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:30 PM PDT 24
Peak memory 201972 kb
Host smart-a1db12b8-7d0c-4a75-8725-c372dd68be1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728824852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_st
ress_all.728824852
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1859188708
Short name T663
Test name
Test status
Simulation time 5713958457 ps
CPU time 4.91 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:10 PM PDT 24
Peak memory 201996 kb
Host smart-c9012ce0-1d3e-477c-8a6f-fb4a9d63c0a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859188708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.1859188708
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1762618886
Short name T724
Test name
Test status
Simulation time 2029659097 ps
CPU time 1.85 seconds
Started Mar 28 12:55:25 PM PDT 24
Finished Mar 28 12:55:27 PM PDT 24
Peak memory 201904 kb
Host smart-fa47ffc7-b0fc-44b8-bc03-5dc196adaa7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762618886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1762618886
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.3428277902
Short name T265
Test name
Test status
Simulation time 74582331076 ps
CPU time 192.18 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 12:58:20 PM PDT 24
Peak memory 202040 kb
Host smart-2cec5f6d-cf17-4141-bce2-5477bc780ced
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428277902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.3428277902
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.515008087
Short name T448
Test name
Test status
Simulation time 3888579606 ps
CPU time 5.39 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 201952 kb
Host smart-f4f45525-e081-4eff-81c0-3851dfe8c70c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515008087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ec_pwr_on_rst.515008087
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1966386183
Short name T683
Test name
Test status
Simulation time 4472725813 ps
CPU time 6.67 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:13 PM PDT 24
Peak memory 201972 kb
Host smart-e73477de-9ffa-45c7-b284-67e16afd8021
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966386183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.1966386183
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1670807929
Short name T633
Test name
Test status
Simulation time 2625593844 ps
CPU time 2.28 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 201964 kb
Host smart-f5698285-37ea-44a1-b5c8-434a87901df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670807929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.1670807929
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.894021255
Short name T670
Test name
Test status
Simulation time 2469933561 ps
CPU time 7.18 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:14 PM PDT 24
Peak memory 201944 kb
Host smart-618341b7-eb9b-40ba-b0f8-70cb4c68b624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894021255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.894021255
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.3466975425
Short name T534
Test name
Test status
Simulation time 2049691192 ps
CPU time 6.01 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:11 PM PDT 24
Peak memory 201932 kb
Host smart-dc389028-f069-4af2-96b9-69d2f3a103d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466975425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.3466975425
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3249329469
Short name T323
Test name
Test status
Simulation time 2528820700 ps
CPU time 2.02 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 201980 kb
Host smart-3f65f67b-aa7f-405f-95ae-503d7b72a1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249329469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3249329469
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.2005063503
Short name T771
Test name
Test status
Simulation time 2116280989 ps
CPU time 3.42 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:09 PM PDT 24
Peak memory 201872 kb
Host smart-ced3ff7f-50e0-432b-9404-9c8622c5682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005063503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2005063503
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.2765252670
Short name T83
Test name
Test status
Simulation time 51752938961 ps
CPU time 125.88 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 202036 kb
Host smart-ebdc8878-4fc0-46e7-a8c2-9276337d93ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765252670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.2765252670
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.4048052011
Short name T185
Test name
Test status
Simulation time 29549157368 ps
CPU time 59.99 seconds
Started Mar 28 12:55:07 PM PDT 24
Finished Mar 28 12:56:07 PM PDT 24
Peak memory 210432 kb
Host smart-c3faf5e5-9372-4859-b4a5-4d75746d508f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048052011 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.4048052011
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.1050621357
Short name T408
Test name
Test status
Simulation time 2093965958 ps
CPU time 1.08 seconds
Started Mar 28 12:55:11 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 201944 kb
Host smart-5f9bba98-c6e0-4d5d-8d61-785d8f20c1e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050621357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.1050621357
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1574947624
Short name T539
Test name
Test status
Simulation time 310351200612 ps
CPU time 108.74 seconds
Started Mar 28 12:55:25 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 201912 kb
Host smart-c7fd2294-2232-4865-b406-cb5202f8e9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574947624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1
574947624
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.3214006643
Short name T257
Test name
Test status
Simulation time 46252830189 ps
CPU time 65.04 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:56:22 PM PDT 24
Peak memory 202180 kb
Host smart-7beeb6f9-ed02-4d3b-9117-9c170b7bbdb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214006643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.3214006643
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.2499942446
Short name T745
Test name
Test status
Simulation time 5346478669 ps
CPU time 3.46 seconds
Started Mar 28 12:55:19 PM PDT 24
Finished Mar 28 12:55:23 PM PDT 24
Peak memory 201928 kb
Host smart-a92f023a-86b5-4073-8f1a-9855183c822f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499942446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.2499942446
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3491858599
Short name T430
Test name
Test status
Simulation time 2610144156 ps
CPU time 7.77 seconds
Started Mar 28 12:55:16 PM PDT 24
Finished Mar 28 12:55:24 PM PDT 24
Peak memory 201936 kb
Host smart-e8a80b0a-5cec-4d60-87c2-02d054d65248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491858599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.3491858599
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3466180719
Short name T522
Test name
Test status
Simulation time 2463671381 ps
CPU time 7.89 seconds
Started Mar 28 12:55:12 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201892 kb
Host smart-9888b3c3-da88-47a0-b324-73f71b92827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466180719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.3466180719
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.1264915929
Short name T550
Test name
Test status
Simulation time 2085335848 ps
CPU time 6.28 seconds
Started Mar 28 12:55:19 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201824 kb
Host smart-8e3c63e1-946f-4cd8-9442-d2c3fe0e80a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264915929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.1264915929
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.2681806278
Short name T780
Test name
Test status
Simulation time 2513265139 ps
CPU time 7.2 seconds
Started Mar 28 12:55:10 PM PDT 24
Finished Mar 28 12:55:17 PM PDT 24
Peak memory 201924 kb
Host smart-3557d1ea-6d02-4171-a5ac-ad12ddc80e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681806278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.2681806278
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.1145226306
Short name T673
Test name
Test status
Simulation time 2129393714 ps
CPU time 2.37 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:55:19 PM PDT 24
Peak memory 201732 kb
Host smart-976bc65b-00e8-4654-a813-e4198079adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145226306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1145226306
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.1303359707
Short name T543
Test name
Test status
Simulation time 9574956916 ps
CPU time 13.2 seconds
Started Mar 28 12:55:16 PM PDT 24
Finished Mar 28 12:55:29 PM PDT 24
Peak memory 201844 kb
Host smart-0299ef30-5a17-453d-8b1b-9d6f55dd0ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303359707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.1303359707
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4164393507
Short name T138
Test name
Test status
Simulation time 12773717849 ps
CPU time 4.23 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:22 PM PDT 24
Peak memory 201928 kb
Host smart-1f9758b6-384a-4e95-b8e3-75cff29cb94e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164393507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.4164393507
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.47750769
Short name T172
Test name
Test status
Simulation time 2022552877 ps
CPU time 2.99 seconds
Started Mar 28 12:55:19 PM PDT 24
Finished Mar 28 12:55:22 PM PDT 24
Peak memory 202024 kb
Host smart-b3365978-5668-4a4a-b53e-ed746480be06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47750769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test
.47750769
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3838476839
Short name T671
Test name
Test status
Simulation time 3375393573 ps
CPU time 9.88 seconds
Started Mar 28 12:55:12 PM PDT 24
Finished Mar 28 12:55:22 PM PDT 24
Peak memory 201884 kb
Host smart-d0f690d1-2959-401c-a6a6-36c323fa0801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838476839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.3
838476839
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2039165426
Short name T640
Test name
Test status
Simulation time 57048555771 ps
CPU time 14.62 seconds
Started Mar 28 12:55:22 PM PDT 24
Finished Mar 28 12:55:37 PM PDT 24
Peak memory 202164 kb
Host smart-86a4eeeb-893d-41bd-b265-a425c65d12ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039165426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.2039165426
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1786592248
Short name T305
Test name
Test status
Simulation time 2600122059 ps
CPU time 4.37 seconds
Started Mar 28 12:55:23 PM PDT 24
Finished Mar 28 12:55:28 PM PDT 24
Peak memory 201888 kb
Host smart-bd704103-470a-4214-aaf1-6d3929ea2005
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786592248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1786592248
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1745666419
Short name T662
Test name
Test status
Simulation time 3178444386 ps
CPU time 3.41 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:55:19 PM PDT 24
Peak memory 201960 kb
Host smart-f98df17e-2123-4e93-86b7-bfcda2215cdc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745666419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.1745666419
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1327139713
Short name T507
Test name
Test status
Simulation time 2625501614 ps
CPU time 2.36 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:55:19 PM PDT 24
Peak memory 201940 kb
Host smart-389c0a6c-2f56-4aa7-b714-a62e453caa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327139713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.1327139713
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.346867914
Short name T456
Test name
Test status
Simulation time 2468726164 ps
CPU time 7.47 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201920 kb
Host smart-ccf56975-2087-4d62-ba8f-b4bff0486787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346867914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.346867914
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.2385681506
Short name T418
Test name
Test status
Simulation time 2143744272 ps
CPU time 3.21 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:55:19 PM PDT 24
Peak memory 201836 kb
Host smart-a397d183-bbeb-40e8-a65e-ec830365876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385681506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.2385681506
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.4126822069
Short name T324
Test name
Test status
Simulation time 2508343786 ps
CPU time 7.81 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:26 PM PDT 24
Peak memory 201936 kb
Host smart-b2071daa-7620-47ac-b98f-d8ba174e30f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126822069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.4126822069
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.2388476292
Short name T303
Test name
Test status
Simulation time 2114408647 ps
CPU time 6.12 seconds
Started Mar 28 12:55:24 PM PDT 24
Finished Mar 28 12:55:31 PM PDT 24
Peak memory 201628 kb
Host smart-67fa5521-3656-4fc0-a1ac-9497ff5f455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388476292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2388476292
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.2943736088
Short name T392
Test name
Test status
Simulation time 208016530861 ps
CPU time 570.44 seconds
Started Mar 28 12:55:13 PM PDT 24
Finished Mar 28 01:04:44 PM PDT 24
Peak memory 202028 kb
Host smart-e6964b77-0f51-45cf-99fa-bdb698496cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943736088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.2943736088
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.313140537
Short name T165
Test name
Test status
Simulation time 127775214379 ps
CPU time 68.91 seconds
Started Mar 28 12:55:12 PM PDT 24
Finished Mar 28 12:56:21 PM PDT 24
Peak memory 210416 kb
Host smart-fa733bf7-f2f6-473b-bbb9-35db23d4d01b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313140537 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.313140537
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.398527863
Short name T74
Test name
Test status
Simulation time 3808333953 ps
CPU time 6.59 seconds
Started Mar 28 12:55:13 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201824 kb
Host smart-ff3cfd39-735e-4baf-8b17-5942f2e230e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398527863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_ultra_low_pwr.398527863
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.2798385709
Short name T131
Test name
Test status
Simulation time 2012285689 ps
CPU time 5.94 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:55:21 PM PDT 24
Peak memory 201928 kb
Host smart-3eaffc4c-79ad-4320-af10-709c3031e7a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798385709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.2798385709
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2256725447
Short name T571
Test name
Test status
Simulation time 3637398248 ps
CPU time 5.32 seconds
Started Mar 28 12:55:23 PM PDT 24
Finished Mar 28 12:55:29 PM PDT 24
Peak memory 201916 kb
Host smart-49ee977b-434d-495e-be7a-073266be5280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256725447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.2
256725447
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1685996392
Short name T365
Test name
Test status
Simulation time 33697394369 ps
CPU time 22.95 seconds
Started Mar 28 12:55:12 PM PDT 24
Finished Mar 28 12:55:36 PM PDT 24
Peak memory 202092 kb
Host smart-b27a15f2-fb20-4543-b4f4-0c9a69058e53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685996392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.1685996392
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.4269417817
Short name T714
Test name
Test status
Simulation time 3447093923 ps
CPU time 2.96 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201740 kb
Host smart-aa54ea97-993a-414a-855d-7b0d22c51ea0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269417817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.4269417817
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.700203358
Short name T160
Test name
Test status
Simulation time 5986304483 ps
CPU time 4.24 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:55:22 PM PDT 24
Peak memory 202016 kb
Host smart-78671354-f002-4fe7-827f-7ef10c3d5cb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700203358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_edge_detect.700203358
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1926663878
Short name T481
Test name
Test status
Simulation time 2610735706 ps
CPU time 7.25 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201916 kb
Host smart-12579867-fbb4-46cb-8e37-f2dbc3e80970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926663878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1926663878
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.163940081
Short name T488
Test name
Test status
Simulation time 2475304877 ps
CPU time 2.33 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:55:23 PM PDT 24
Peak memory 201912 kb
Host smart-f0f62b2c-d0e4-413b-b52f-07a7c0564352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163940081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.163940081
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2441322825
Short name T196
Test name
Test status
Simulation time 2233345944 ps
CPU time 3.52 seconds
Started Mar 28 12:55:24 PM PDT 24
Finished Mar 28 12:55:27 PM PDT 24
Peak memory 201808 kb
Host smart-30d5f535-27e1-4fb5-8d10-259089987a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441322825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2441322825
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.4148441734
Short name T329
Test name
Test status
Simulation time 2550745813 ps
CPU time 1.38 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201916 kb
Host smart-48fc4793-7b61-4514-aef7-6137890eedbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148441734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.4148441734
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3936817644
Short name T91
Test name
Test status
Simulation time 2123729326 ps
CPU time 2.06 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:55:17 PM PDT 24
Peak memory 201892 kb
Host smart-eeceedfe-2399-46a5-a13c-b7e92c2de253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936817644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3936817644
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.3746259236
Short name T751
Test name
Test status
Simulation time 11485179618 ps
CPU time 8.6 seconds
Started Mar 28 12:55:16 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201780 kb
Host smart-2c2be30a-3caf-426e-8327-169e55e112ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746259236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.3746259236
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2479701518
Short name T2
Test name
Test status
Simulation time 2994475371 ps
CPU time 6.3 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201928 kb
Host smart-ff9019ae-a8ee-4829-8749-e3b8d543be01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479701518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.2479701518
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.3103764318
Short name T425
Test name
Test status
Simulation time 2047427657 ps
CPU time 1.76 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:55:17 PM PDT 24
Peak memory 201924 kb
Host smart-7fd812d4-bf83-4320-9f9b-d5aa97d91df6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103764318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.3103764318
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2995231045
Short name T594
Test name
Test status
Simulation time 3430917260 ps
CPU time 5.16 seconds
Started Mar 28 12:55:27 PM PDT 24
Finished Mar 28 12:55:33 PM PDT 24
Peak memory 201964 kb
Host smart-2e500f7b-c10b-489e-bca7-d690857047c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995231045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
995231045
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.602806996
Short name T711
Test name
Test status
Simulation time 87885306639 ps
CPU time 232.28 seconds
Started Mar 28 12:55:20 PM PDT 24
Finished Mar 28 12:59:12 PM PDT 24
Peak memory 202048 kb
Host smart-1a82f7a1-c4cd-45a5-a071-91fd2ec450b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602806996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_combo_detect.602806996
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.1956391840
Short name T727
Test name
Test status
Simulation time 3498400870 ps
CPU time 3.48 seconds
Started Mar 28 12:55:13 PM PDT 24
Finished Mar 28 12:55:17 PM PDT 24
Peak memory 201932 kb
Host smart-54c33f25-bb17-45ce-9f57-911a0cd3657b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956391840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.1956391840
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.4151526250
Short name T199
Test name
Test status
Simulation time 5487341606 ps
CPU time 6.2 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201920 kb
Host smart-f9c8fb45-c83b-46f8-9bec-3a3f783c1cc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151526250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.4151526250
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1500631923
Short name T739
Test name
Test status
Simulation time 2613790360 ps
CPU time 7.76 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201816 kb
Host smart-81453efa-3355-4022-b73e-bcce5d11b12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500631923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1500631923
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1705168549
Short name T16
Test name
Test status
Simulation time 2472654050 ps
CPU time 7.54 seconds
Started Mar 28 12:55:24 PM PDT 24
Finished Mar 28 12:55:31 PM PDT 24
Peak memory 201840 kb
Host smart-3ce20f10-a33b-4c5b-a069-bc32442df3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705168549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1705168549
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.992717318
Short name T575
Test name
Test status
Simulation time 2077825321 ps
CPU time 5.47 seconds
Started Mar 28 12:55:28 PM PDT 24
Finished Mar 28 12:55:34 PM PDT 24
Peak memory 201180 kb
Host smart-0790a83c-95e4-4c91-9197-0e315ef2ad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992717318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.992717318
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1289780665
Short name T661
Test name
Test status
Simulation time 2567493380 ps
CPU time 1.2 seconds
Started Mar 28 12:55:19 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201932 kb
Host smart-e14e49fe-3ec4-4c70-a347-13b787e5e489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289780665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.1289780665
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.1719427845
Short name T423
Test name
Test status
Simulation time 2138430858 ps
CPU time 2.01 seconds
Started Mar 28 12:55:20 PM PDT 24
Finished Mar 28 12:55:22 PM PDT 24
Peak memory 201892 kb
Host smart-a63ebcbd-c402-47a0-8ac0-74d445045127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719427845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.1719427845
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.2042589212
Short name T233
Test name
Test status
Simulation time 133050557163 ps
CPU time 174.23 seconds
Started Mar 28 12:55:12 PM PDT 24
Finished Mar 28 12:58:07 PM PDT 24
Peak memory 202144 kb
Host smart-4d40c576-f5f7-4f4e-9999-53b6277f2656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042589212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.2042589212
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1830583308
Short name T297
Test name
Test status
Simulation time 44451840465 ps
CPU time 114.97 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 210556 kb
Host smart-2fa698b5-e1f5-4b8e-8503-1e72ea41d667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830583308 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.1830583308
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3932902631
Short name T567
Test name
Test status
Simulation time 7011269021 ps
CPU time 6.34 seconds
Started Mar 28 12:55:13 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201976 kb
Host smart-88fcd486-1e26-4fe3-af99-4d732b812346
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932902631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.3932902631
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.741670575
Short name T129
Test name
Test status
Simulation time 2015261195 ps
CPU time 6.04 seconds
Started Mar 28 12:55:28 PM PDT 24
Finished Mar 28 12:55:34 PM PDT 24
Peak memory 201160 kb
Host smart-e1063623-e139-4451-8fef-e5d5d602322b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741670575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.741670575
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.740378741
Short name T125
Test name
Test status
Simulation time 3031307402 ps
CPU time 8.28 seconds
Started Mar 28 12:55:21 PM PDT 24
Finished Mar 28 12:55:29 PM PDT 24
Peak memory 202016 kb
Host smart-5a375414-e395-4bc6-9a40-76aeccdc066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740378741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.740378741
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.722455735
Short name T117
Test name
Test status
Simulation time 58019523724 ps
CPU time 113.94 seconds
Started Mar 28 12:55:31 PM PDT 24
Finished Mar 28 12:57:25 PM PDT 24
Peak memory 202084 kb
Host smart-7816ed99-077f-40c9-825a-f4a0a3d507d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722455735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_combo_detect.722455735
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.576887844
Short name T519
Test name
Test status
Simulation time 30924354412 ps
CPU time 7.36 seconds
Started Mar 28 12:55:24 PM PDT 24
Finished Mar 28 12:55:32 PM PDT 24
Peak memory 202112 kb
Host smart-9ff97e8e-57d0-4f03-a9f9-e9628c8e29fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576887844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_wi
th_pre_cond.576887844
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2926151671
Short name T528
Test name
Test status
Simulation time 3092423837 ps
CPU time 2.54 seconds
Started Mar 28 12:55:20 PM PDT 24
Finished Mar 28 12:55:22 PM PDT 24
Peak memory 201888 kb
Host smart-cec32d3e-290a-4d1d-ba49-ab08a6e0cda1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926151671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.2926151671
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.3156047427
Short name T515
Test name
Test status
Simulation time 3414841477 ps
CPU time 2.81 seconds
Started Mar 28 12:55:24 PM PDT 24
Finished Mar 28 12:55:27 PM PDT 24
Peak memory 201604 kb
Host smart-4f5c41c3-bf90-493a-b226-d78fdf74b6b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156047427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.3156047427
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.809246846
Short name T410
Test name
Test status
Simulation time 2632990126 ps
CPU time 2.5 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201936 kb
Host smart-fa1e7a1b-02bc-4896-9b60-70ec19439a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809246846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.809246846
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.959361419
Short name T617
Test name
Test status
Simulation time 2485075891 ps
CPU time 4.22 seconds
Started Mar 28 12:55:16 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201868 kb
Host smart-3b85f4fb-8192-4adf-884f-5b45f54c9fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959361419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.959361419
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.4133701557
Short name T464
Test name
Test status
Simulation time 2276767903 ps
CPU time 2.06 seconds
Started Mar 28 12:55:14 PM PDT 24
Finished Mar 28 12:55:16 PM PDT 24
Peak memory 201916 kb
Host smart-399854a7-a2f5-4b16-9d7c-1f2600b738ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133701557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.4133701557
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.1684198480
Short name T173
Test name
Test status
Simulation time 2507408547 ps
CPU time 7.24 seconds
Started Mar 28 12:55:13 PM PDT 24
Finished Mar 28 12:55:21 PM PDT 24
Peak memory 201972 kb
Host smart-4dfaaf34-b9a3-464b-beec-d1c4ebfe0fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684198480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.1684198480
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.1486934373
Short name T759
Test name
Test status
Simulation time 2190457752 ps
CPU time 1.18 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:19 PM PDT 24
Peak memory 201928 kb
Host smart-02cc0f14-5c13-4f38-80b2-b38cf2de8438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486934373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1486934373
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.1134548092
Short name T32
Test name
Test status
Simulation time 12838012555 ps
CPU time 7.84 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:55:26 PM PDT 24
Peak memory 201808 kb
Host smart-da716c61-6c3d-4b2b-8fbc-bb4358759574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134548092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.1134548092
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1074316274
Short name T592
Test name
Test status
Simulation time 14555211947 ps
CPU time 38.93 seconds
Started Mar 28 12:55:23 PM PDT 24
Finished Mar 28 12:56:03 PM PDT 24
Peak memory 202012 kb
Host smart-72e5d8c8-a621-4a75-9737-f89cd7475d3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074316274 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.1074316274
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2505731681
Short name T788
Test name
Test status
Simulation time 1973196555202 ps
CPU time 155.97 seconds
Started Mar 28 12:55:28 PM PDT 24
Finished Mar 28 12:58:04 PM PDT 24
Peak memory 201844 kb
Host smart-9a9c133c-7a31-4f2e-8c88-861c2f8ee8b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505731681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.2505731681
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1938432350
Short name T142
Test name
Test status
Simulation time 2011389627 ps
CPU time 5.87 seconds
Started Mar 28 12:55:23 PM PDT 24
Finished Mar 28 12:55:29 PM PDT 24
Peak memory 201972 kb
Host smart-93642a45-ac2a-46e9-94ee-63eee3331f13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938432350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1938432350
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1032165151
Short name T562
Test name
Test status
Simulation time 3228029660 ps
CPU time 2.45 seconds
Started Mar 28 12:55:29 PM PDT 24
Finished Mar 28 12:55:32 PM PDT 24
Peak memory 200664 kb
Host smart-e53b0a3c-e6b6-4cbf-a0cc-b2dffc75f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032165151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1
032165151
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.2821292880
Short name T256
Test name
Test status
Simulation time 31841637360 ps
CPU time 83.08 seconds
Started Mar 28 12:55:29 PM PDT 24
Finished Mar 28 12:56:52 PM PDT 24
Peak memory 202020 kb
Host smart-ff5ca64c-39d6-4d0d-809a-17e527c44d70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821292880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.2821292880
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2033874500
Short name T333
Test name
Test status
Simulation time 83064175560 ps
CPU time 55.91 seconds
Started Mar 28 12:55:14 PM PDT 24
Finished Mar 28 12:56:10 PM PDT 24
Peak memory 201952 kb
Host smart-463de00b-0cd3-42ca-baef-5f9f3e701378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033874500 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.2033874500
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1313352768
Short name T52
Test name
Test status
Simulation time 4021560892 ps
CPU time 10.45 seconds
Started Mar 28 12:55:29 PM PDT 24
Finished Mar 28 12:55:40 PM PDT 24
Peak memory 201844 kb
Host smart-8b7fc217-5be4-4511-99a8-53e775b15e8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313352768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.1313352768
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1162415178
Short name T135
Test name
Test status
Simulation time 3072458619 ps
CPU time 4.51 seconds
Started Mar 28 12:55:15 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201960 kb
Host smart-8955f38a-8ce5-41c8-956f-c582b692d387
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162415178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.1162415178
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1055097067
Short name T472
Test name
Test status
Simulation time 2612881296 ps
CPU time 6.98 seconds
Started Mar 28 12:55:23 PM PDT 24
Finished Mar 28 12:55:31 PM PDT 24
Peak memory 201972 kb
Host smart-7fdbcc04-8627-48a6-89eb-0f5242c52fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055097067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.1055097067
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.3549039701
Short name T588
Test name
Test status
Simulation time 2467811689 ps
CPU time 2.37 seconds
Started Mar 28 12:55:29 PM PDT 24
Finished Mar 28 12:55:31 PM PDT 24
Peak memory 200784 kb
Host smart-34179c6c-3744-450a-ac5b-e03268d267b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549039701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.3549039701
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.812933396
Short name T648
Test name
Test status
Simulation time 2097208044 ps
CPU time 5.97 seconds
Started Mar 28 12:55:31 PM PDT 24
Finished Mar 28 12:55:38 PM PDT 24
Peak memory 201772 kb
Host smart-c3fc1709-e1cd-48d6-a6b1-e1feb13c83dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812933396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.812933396
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.211677152
Short name T414
Test name
Test status
Simulation time 2522063860 ps
CPU time 4.22 seconds
Started Mar 28 12:55:14 PM PDT 24
Finished Mar 28 12:55:18 PM PDT 24
Peak memory 201980 kb
Host smart-db595f72-5513-42d1-b26b-d8fd537231c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211677152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.211677152
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.128549463
Short name T527
Test name
Test status
Simulation time 2119236593 ps
CPU time 3.46 seconds
Started Mar 28 12:55:31 PM PDT 24
Finished Mar 28 12:55:35 PM PDT 24
Peak memory 201768 kb
Host smart-cfecf432-8ead-44ef-bb9e-eeceab47d8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128549463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.128549463
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.3710482870
Short name T46
Test name
Test status
Simulation time 15596585820 ps
CPU time 21.61 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:44 PM PDT 24
Peak memory 201940 kb
Host smart-61512ca1-488c-4362-a33d-677d98cdbaca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710482870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.3710482870
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1584427668
Short name T530
Test name
Test status
Simulation time 7614751184 ps
CPU time 1.4 seconds
Started Mar 28 12:55:14 PM PDT 24
Finished Mar 28 12:55:15 PM PDT 24
Peak memory 201960 kb
Host smart-4d379b92-6bcf-44ba-8831-a05b7cd79756
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584427668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.1584427668
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.955333748
Short name T694
Test name
Test status
Simulation time 2016648521 ps
CPU time 5.35 seconds
Started Mar 28 12:55:38 PM PDT 24
Finished Mar 28 12:55:44 PM PDT 24
Peak memory 201936 kb
Host smart-a52db8e0-d7bf-484e-8454-626ed3a29cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955333748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_tes
t.955333748
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1343030440
Short name T730
Test name
Test status
Simulation time 213176542749 ps
CPU time 539.48 seconds
Started Mar 28 12:55:35 PM PDT 24
Finished Mar 28 01:04:35 PM PDT 24
Peak memory 202076 kb
Host smart-b652bb90-cf74-4ea8-9945-89e699b68ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343030440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1
343030440
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3879865208
Short name T76
Test name
Test status
Simulation time 31583899987 ps
CPU time 13.81 seconds
Started Mar 28 12:55:29 PM PDT 24
Finished Mar 28 12:55:43 PM PDT 24
Peak memory 202120 kb
Host smart-c34991b3-858c-4b56-80a1-cceca71d9eed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879865208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3879865208
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.485753008
Short name T523
Test name
Test status
Simulation time 28581864007 ps
CPU time 77.98 seconds
Started Mar 28 12:55:36 PM PDT 24
Finished Mar 28 12:56:55 PM PDT 24
Peak memory 202216 kb
Host smart-8486465c-4568-4645-9b6c-798e624c9052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485753008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.485753008
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1527995077
Short name T626
Test name
Test status
Simulation time 3733822759 ps
CPU time 9.78 seconds
Started Mar 28 12:55:19 PM PDT 24
Finished Mar 28 12:55:29 PM PDT 24
Peak memory 201884 kb
Host smart-a13e7d86-de7a-4dc5-9c27-e45535fad467
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527995077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.1527995077
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.1687542441
Short name T10
Test name
Test status
Simulation time 3327853549 ps
CPU time 2.4 seconds
Started Mar 28 12:55:42 PM PDT 24
Finished Mar 28 12:55:45 PM PDT 24
Peak memory 201888 kb
Host smart-d2ae7cf3-ff18-4567-b089-000ba46d3515
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687542441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.1687542441
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1707824674
Short name T432
Test name
Test status
Simulation time 2618119642 ps
CPU time 3.81 seconds
Started Mar 28 12:55:13 PM PDT 24
Finished Mar 28 12:55:17 PM PDT 24
Peak memory 201884 kb
Host smart-23d47240-278b-463f-9d54-27fa99c7be00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707824674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1707824674
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.1630052622
Short name T614
Test name
Test status
Simulation time 2468928137 ps
CPU time 6.75 seconds
Started Mar 28 12:55:13 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201716 kb
Host smart-ffbaf89d-65c6-4b41-bce0-6ad5035f7f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630052622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1630052622
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3284384467
Short name T554
Test name
Test status
Simulation time 2164629738 ps
CPU time 1.9 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 201800 kb
Host smart-b38fe2e1-87ff-43cc-a3bd-1488112443fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284384467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3284384467
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.3390625166
Short name T176
Test name
Test status
Simulation time 2509038812 ps
CPU time 6.87 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201792 kb
Host smart-23189a1f-00f4-40e0-ae54-f9318a85841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390625166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3390625166
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.3862368016
Short name T163
Test name
Test status
Simulation time 2149527051 ps
CPU time 1.29 seconds
Started Mar 28 12:55:18 PM PDT 24
Finished Mar 28 12:55:19 PM PDT 24
Peak memory 201788 kb
Host smart-68ab18b1-7928-48c8-9a76-e671c32ace00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862368016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3862368016
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.1262469029
Short name T3
Test name
Test status
Simulation time 18042763520 ps
CPU time 8.23 seconds
Started Mar 28 12:55:37 PM PDT 24
Finished Mar 28 12:55:46 PM PDT 24
Peak memory 201976 kb
Host smart-1f954f94-eff4-45d0-932d-a4d8832578f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262469029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.1262469029
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2829406471
Short name T197
Test name
Test status
Simulation time 7288670160 ps
CPU time 4.24 seconds
Started Mar 28 12:55:35 PM PDT 24
Finished Mar 28 12:55:40 PM PDT 24
Peak memory 201960 kb
Host smart-9bcbfdd6-c489-44c9-bca9-db68efcdd304
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829406471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.2829406471
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.1060789909
Short name T484
Test name
Test status
Simulation time 2015296434 ps
CPU time 4.12 seconds
Started Mar 28 12:55:37 PM PDT 24
Finished Mar 28 12:55:41 PM PDT 24
Peak memory 202068 kb
Host smart-c13b75cc-dee6-4c50-81ef-9374fe24653b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060789909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.1060789909
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2278364478
Short name T586
Test name
Test status
Simulation time 3481024199 ps
CPU time 9.71 seconds
Started Mar 28 12:55:29 PM PDT 24
Finished Mar 28 12:55:39 PM PDT 24
Peak memory 201948 kb
Host smart-383bf027-d848-4d24-9cf4-edb2f8883582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278364478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.2
278364478
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.1153592981
Short name T393
Test name
Test status
Simulation time 136662184057 ps
CPU time 50.89 seconds
Started Mar 28 12:55:31 PM PDT 24
Finished Mar 28 12:56:22 PM PDT 24
Peak memory 202100 kb
Host smart-0d2d3eee-3e82-43d0-8662-efb2a1a964f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153592981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.1153592981
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.30686301
Short name T415
Test name
Test status
Simulation time 3210730941 ps
CPU time 2.84 seconds
Started Mar 28 12:55:38 PM PDT 24
Finished Mar 28 12:55:41 PM PDT 24
Peak memory 201860 kb
Host smart-500cd58e-f254-4207-9b2c-6a6b00aff54c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30686301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_ec_pwr_on_rst.30686301
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.370945636
Short name T182
Test name
Test status
Simulation time 3358603908 ps
CPU time 1.47 seconds
Started Mar 28 12:55:37 PM PDT 24
Finished Mar 28 12:55:38 PM PDT 24
Peak memory 201816 kb
Host smart-fece0f3f-ad19-44b1-9e0e-aed26a90047b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370945636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctr
l_edge_detect.370945636
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1242044204
Short name T65
Test name
Test status
Simulation time 2637722324 ps
CPU time 2.22 seconds
Started Mar 28 12:55:35 PM PDT 24
Finished Mar 28 12:55:38 PM PDT 24
Peak memory 201952 kb
Host smart-25ab94f1-388d-4965-9ffe-893b7f90d256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242044204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.1242044204
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.3621555061
Short name T449
Test name
Test status
Simulation time 2482728660 ps
CPU time 4.19 seconds
Started Mar 28 12:55:34 PM PDT 24
Finished Mar 28 12:55:39 PM PDT 24
Peak memory 201936 kb
Host smart-f76855f4-18ec-44f3-9f65-82d21b634d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621555061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.3621555061
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1387740341
Short name T461
Test name
Test status
Simulation time 2050206390 ps
CPU time 6.2 seconds
Started Mar 28 12:55:33 PM PDT 24
Finished Mar 28 12:55:40 PM PDT 24
Peak memory 201780 kb
Host smart-b84ca37d-d693-4d79-94e6-e1afa9698456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387740341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.1387740341
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3977494735
Short name T504
Test name
Test status
Simulation time 2532277840 ps
CPU time 2.48 seconds
Started Mar 28 12:55:35 PM PDT 24
Finished Mar 28 12:55:38 PM PDT 24
Peak memory 201864 kb
Host smart-c4657b2d-2f45-4f48-9c3b-51e5c77d20a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977494735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3977494735
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.1710684668
Short name T561
Test name
Test status
Simulation time 2121847980 ps
CPU time 2.1 seconds
Started Mar 28 12:55:40 PM PDT 24
Finished Mar 28 12:55:42 PM PDT 24
Peak memory 201804 kb
Host smart-df52cbe3-35cd-46af-9138-f7c29574f676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710684668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.1710684668
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.1502286124
Short name T157
Test name
Test status
Simulation time 10665043233 ps
CPU time 13.69 seconds
Started Mar 28 12:55:34 PM PDT 24
Finished Mar 28 12:55:48 PM PDT 24
Peak memory 201980 kb
Host smart-b23c86a4-0886-41d9-8c86-6ba49422d9b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502286124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.1502286124
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.44175234
Short name T719
Test name
Test status
Simulation time 35624679741 ps
CPU time 101.6 seconds
Started Mar 28 12:55:29 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 210500 kb
Host smart-cfbe9c5e-578e-4738-82f8-cae285f530fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44175234 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.44175234
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2330652068
Short name T123
Test name
Test status
Simulation time 9100223527 ps
CPU time 6.43 seconds
Started Mar 28 12:55:32 PM PDT 24
Finished Mar 28 12:55:39 PM PDT 24
Peak memory 201908 kb
Host smart-7dcc1683-61a9-44ee-afd8-72c70a3af9df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330652068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.2330652068
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1639058698
Short name T502
Test name
Test status
Simulation time 2015454210 ps
CPU time 6.04 seconds
Started Mar 28 12:54:54 PM PDT 24
Finished Mar 28 12:55:00 PM PDT 24
Peak memory 202020 kb
Host smart-c8e50a42-7bf1-410a-ac46-25d171afaebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639058698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1639058698
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2856799541
Short name T295
Test name
Test status
Simulation time 3651689646 ps
CPU time 10.21 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:55:00 PM PDT 24
Peak memory 201996 kb
Host smart-6a785a75-ab93-45b6-99fd-7b44180a2a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856799541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.2856799541
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3332471992
Short name T7
Test name
Test status
Simulation time 79220401714 ps
CPU time 58.29 seconds
Started Mar 28 12:54:46 PM PDT 24
Finished Mar 28 12:55:44 PM PDT 24
Peak memory 202148 kb
Host smart-7df83cd4-7731-47b3-bf1a-b6e315aaa4af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332471992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.3332471992
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.397761906
Short name T455
Test name
Test status
Simulation time 2393584027 ps
CPU time 7.01 seconds
Started Mar 28 12:54:52 PM PDT 24
Finished Mar 28 12:55:00 PM PDT 24
Peak memory 201916 kb
Host smart-f18b8778-c4fc-4ce6-a27e-f2a753207d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397761906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.397761906
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1614369653
Short name T332
Test name
Test status
Simulation time 2538763246 ps
CPU time 2.25 seconds
Started Mar 28 12:54:52 PM PDT 24
Finished Mar 28 12:54:54 PM PDT 24
Peak memory 201968 kb
Host smart-64f5e092-f783-4f0c-bf14-baba2b46c75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614369653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1614369653
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.228506529
Short name T629
Test name
Test status
Simulation time 57131452978 ps
CPU time 75.11 seconds
Started Mar 28 12:54:48 PM PDT 24
Finished Mar 28 12:56:03 PM PDT 24
Peak memory 202176 kb
Host smart-c1dd59a4-db10-4cba-b985-a473142bd87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228506529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wit
h_pre_cond.228506529
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3835340318
Short name T195
Test name
Test status
Simulation time 2545491652 ps
CPU time 2.27 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:52 PM PDT 24
Peak memory 201964 kb
Host smart-919c9ed5-2e33-4671-9073-258de604e848
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835340318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.3835340318
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1368653953
Short name T620
Test name
Test status
Simulation time 2626674177 ps
CPU time 2.27 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:52 PM PDT 24
Peak memory 201948 kb
Host smart-29e068a8-f7ce-4c44-8d0c-7797852809ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368653953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1368653953
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.2126409057
Short name T638
Test name
Test status
Simulation time 2463163402 ps
CPU time 3.94 seconds
Started Mar 28 12:54:53 PM PDT 24
Finished Mar 28 12:54:57 PM PDT 24
Peak memory 201956 kb
Host smart-14810263-b1b3-498e-912f-bab209a42491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126409057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2126409057
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.243119263
Short name T733
Test name
Test status
Simulation time 2214528484 ps
CPU time 3.56 seconds
Started Mar 28 12:54:47 PM PDT 24
Finished Mar 28 12:54:51 PM PDT 24
Peak memory 201908 kb
Host smart-cf1fb594-9bb3-49fb-a648-8340295f9ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243119263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.243119263
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1452847384
Short name T320
Test name
Test status
Simulation time 2513861078 ps
CPU time 7.21 seconds
Started Mar 28 12:54:46 PM PDT 24
Finished Mar 28 12:54:53 PM PDT 24
Peak memory 201964 kb
Host smart-7111b463-ab79-47cc-a2a3-988946f5fa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452847384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1452847384
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.1870181001
Short name T289
Test name
Test status
Simulation time 22013738479 ps
CPU time 59.61 seconds
Started Mar 28 12:54:52 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 221660 kb
Host smart-b0c6242f-95c5-42c1-82c0-546f19226044
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870181001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1870181001
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.3182778019
Short name T545
Test name
Test status
Simulation time 2129489000 ps
CPU time 2 seconds
Started Mar 28 12:55:01 PM PDT 24
Finished Mar 28 12:55:04 PM PDT 24
Peak memory 201848 kb
Host smart-583f479e-3bfc-4f83-baf5-2517d9a7eb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182778019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.3182778019
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.3136547391
Short name T166
Test name
Test status
Simulation time 13651503279 ps
CPU time 3.13 seconds
Started Mar 28 12:54:52 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 201960 kb
Host smart-50914e4a-90d1-4f03-9a65-2cd8d7d7cf2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136547391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.3136547391
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.4067231448
Short name T750
Test name
Test status
Simulation time 4869135266 ps
CPU time 7.02 seconds
Started Mar 28 12:54:46 PM PDT 24
Finished Mar 28 12:54:53 PM PDT 24
Peak memory 201956 kb
Host smart-f7f4367a-3728-4078-a06f-bca3d8848c3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067231448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.4067231448
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3047477983
Short name T659
Test name
Test status
Simulation time 2011654600 ps
CPU time 5.97 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:57 PM PDT 24
Peak memory 202020 kb
Host smart-127f3176-59c8-4a08-82f0-576b9c7b5cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047477983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3047477983
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2117236818
Short name T40
Test name
Test status
Simulation time 253214412558 ps
CPU time 155.36 seconds
Started Mar 28 12:55:30 PM PDT 24
Finished Mar 28 12:58:07 PM PDT 24
Peak memory 201920 kb
Host smart-fc44763c-1ddf-4f53-9a15-2fd8285824ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117236818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.2
117236818
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.2401952560
Short name T29
Test name
Test status
Simulation time 108914160311 ps
CPU time 286.2 seconds
Started Mar 28 12:55:32 PM PDT 24
Finished Mar 28 01:00:20 PM PDT 24
Peak memory 202040 kb
Host smart-5c7af1de-c3c8-426d-adf0-13d55a126356
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401952560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.2401952560
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1717523143
Short name T314
Test name
Test status
Simulation time 3131700284 ps
CPU time 7.53 seconds
Started Mar 28 12:55:44 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 201848 kb
Host smart-de441107-8805-4cf6-a79f-23a6c135fb0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717523143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.1717523143
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.2528134069
Short name T706
Test name
Test status
Simulation time 3536549829 ps
CPU time 2.9 seconds
Started Mar 28 12:55:42 PM PDT 24
Finished Mar 28 12:55:46 PM PDT 24
Peak memory 201888 kb
Host smart-9a5ac13d-a56e-4103-b068-ba1a59b36476
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528134069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.2528134069
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1270412352
Short name T68
Test name
Test status
Simulation time 2623207984 ps
CPU time 2.3 seconds
Started Mar 28 12:55:26 PM PDT 24
Finished Mar 28 12:55:28 PM PDT 24
Peak memory 201968 kb
Host smart-a827beb0-8e8b-400d-9b5c-8b29b80bf466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270412352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.1270412352
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1479273902
Short name T740
Test name
Test status
Simulation time 2508518375 ps
CPU time 1.75 seconds
Started Mar 28 12:55:35 PM PDT 24
Finished Mar 28 12:55:37 PM PDT 24
Peak memory 201944 kb
Host smart-3c48d922-778a-41c3-8ff9-dbabe5db8540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479273902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1479273902
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1672982988
Short name T412
Test name
Test status
Simulation time 2094571848 ps
CPU time 1.92 seconds
Started Mar 28 12:55:30 PM PDT 24
Finished Mar 28 12:55:33 PM PDT 24
Peak memory 201904 kb
Host smart-06683ba4-9869-4398-a5d5-e987effe0a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672982988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1672982988
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3845846263
Short name T577
Test name
Test status
Simulation time 2514793908 ps
CPU time 4.26 seconds
Started Mar 28 12:55:35 PM PDT 24
Finished Mar 28 12:55:40 PM PDT 24
Peak memory 201920 kb
Host smart-457977f5-4b13-4ffb-beb4-bf8f8fc9ff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845846263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.3845846263
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.2057561756
Short name T495
Test name
Test status
Simulation time 2113814609 ps
CPU time 5.87 seconds
Started Mar 28 12:55:37 PM PDT 24
Finished Mar 28 12:55:44 PM PDT 24
Peak memory 201868 kb
Host smart-e885afe6-885c-4a3a-99ca-d7c74546a69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057561756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.2057561756
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.3870041540
Short name T453
Test name
Test status
Simulation time 9737297705 ps
CPU time 13.93 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:56:03 PM PDT 24
Peak memory 201920 kb
Host smart-50737e69-ac1b-4717-9bd7-d92173ec32dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870041540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.3870041540
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3528814039
Short name T298
Test name
Test status
Simulation time 32191094591 ps
CPU time 87.96 seconds
Started Mar 28 12:55:35 PM PDT 24
Finished Mar 28 12:57:03 PM PDT 24
Peak memory 218532 kb
Host smart-b3a49d6b-0bba-4542-92c2-3e78988acec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528814039 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.3528814039
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1892103984
Short name T326
Test name
Test status
Simulation time 2797241007 ps
CPU time 3.04 seconds
Started Mar 28 12:55:40 PM PDT 24
Finished Mar 28 12:55:43 PM PDT 24
Peak memory 201904 kb
Host smart-b15f6e5a-ae64-45d2-93e8-cd697e6f253d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892103984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.1892103984
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.2897249692
Short name T563
Test name
Test status
Simulation time 2019996016 ps
CPU time 3.23 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201984 kb
Host smart-d5c1b67d-4cb6-4f44-902d-851d625b4603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897249692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.2897249692
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2323135937
Short name T580
Test name
Test status
Simulation time 3739639857 ps
CPU time 2.32 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:55:57 PM PDT 24
Peak memory 201908 kb
Host smart-16478739-5fca-46ae-ae89-46fa212f6076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323135937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.2
323135937
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.867453775
Short name T101
Test name
Test status
Simulation time 72273588753 ps
CPU time 47.74 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:56:38 PM PDT 24
Peak memory 202180 kb
Host smart-d70551fe-13e9-4e40-a6b7-9ab1349722eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867453775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_combo_detect.867453775
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3274422570
Short name T222
Test name
Test status
Simulation time 2840400436 ps
CPU time 3.06 seconds
Started Mar 28 12:55:46 PM PDT 24
Finished Mar 28 12:55:49 PM PDT 24
Peak memory 201940 kb
Host smart-78f27ff8-e9ee-4755-89f1-5de9e3e78c6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274422570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.3274422570
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.341964501
Short name T675
Test name
Test status
Simulation time 5298217968 ps
CPU time 11.79 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 201928 kb
Host smart-a89b5981-610d-487d-87e7-87729afea4ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341964501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctr
l_edge_detect.341964501
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1541623577
Short name T141
Test name
Test status
Simulation time 2611681634 ps
CPU time 7.53 seconds
Started Mar 28 12:55:45 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201960 kb
Host smart-e189f8ca-65e5-48e4-aab1-8a7b8c3973b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541623577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.1541623577
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2492308921
Short name T737
Test name
Test status
Simulation time 2453073249 ps
CPU time 7.25 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:58 PM PDT 24
Peak memory 201964 kb
Host smart-e0f5f648-7c58-4e89-88ff-a52ee186a825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492308921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2492308921
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.4130386063
Short name T200
Test name
Test status
Simulation time 2093853717 ps
CPU time 6.06 seconds
Started Mar 28 12:55:46 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 201876 kb
Host smart-51210cfc-99c4-402a-b69d-71f3373d5d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130386063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.4130386063
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.277554012
Short name T541
Test name
Test status
Simulation time 2542791098 ps
CPU time 2.32 seconds
Started Mar 28 12:55:46 PM PDT 24
Finished Mar 28 12:55:48 PM PDT 24
Peak memory 201936 kb
Host smart-6603b149-8bcb-4363-828b-ef6270f6239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277554012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.277554012
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.1315612390
Short name T457
Test name
Test status
Simulation time 2164939784 ps
CPU time 1.26 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201908 kb
Host smart-6e8ad098-6f7f-4dde-b5f9-228f74a2fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315612390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1315612390
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.2100315946
Short name T770
Test name
Test status
Simulation time 6546656476 ps
CPU time 1.51 seconds
Started Mar 28 12:55:46 PM PDT 24
Finished Mar 28 12:55:48 PM PDT 24
Peak memory 201856 kb
Host smart-ff133569-34ed-4e48-a3c9-23269e48b21d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100315946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.2100315946
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3782504408
Short name T482
Test name
Test status
Simulation time 9471248744 ps
CPU time 6.26 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:58 PM PDT 24
Peak memory 201624 kb
Host smart-b292c512-7670-457b-b11d-7ef75e901fbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782504408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.3782504408
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.2393596212
Short name T503
Test name
Test status
Simulation time 2022818243 ps
CPU time 3.07 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 201996 kb
Host smart-c0a4b4b0-e167-472e-96d2-3e8a2b85687e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393596212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.2393596212
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3762713307
Short name T578
Test name
Test status
Simulation time 3397564594 ps
CPU time 2.84 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201956 kb
Host smart-28f85515-e397-4588-af9e-c43fd7f36541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762713307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.3
762713307
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1085287184
Short name T678
Test name
Test status
Simulation time 85902285404 ps
CPU time 28.11 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:56:19 PM PDT 24
Peak memory 202108 kb
Host smart-3678a8d8-6fe2-4fe8-ae32-76d5a085aeec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085287184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.1085287184
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.477473069
Short name T790
Test name
Test status
Simulation time 3085299857 ps
CPU time 8.95 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:59 PM PDT 24
Peak memory 201924 kb
Host smart-3ce69066-ae90-48fd-b1fc-59f0608df080
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477473069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_ec_pwr_on_rst.477473069
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.1915185667
Short name T487
Test name
Test status
Simulation time 3527909089 ps
CPU time 1.61 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:51 PM PDT 24
Peak memory 201948 kb
Host smart-30d302a3-585c-4655-b759-00516331ee2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915185667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.1915185667
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3414048721
Short name T716
Test name
Test status
Simulation time 2645202760 ps
CPU time 1.46 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 201900 kb
Host smart-9dc3df40-fd88-4e23-aeb7-6ec95776df58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414048721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3414048721
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2632479108
Short name T760
Test name
Test status
Simulation time 2478343686 ps
CPU time 3.85 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201932 kb
Host smart-8e19441d-57ae-4145-bfb7-9ccbfbe769e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632479108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2632479108
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3214762983
Short name T153
Test name
Test status
Simulation time 2116473812 ps
CPU time 1.27 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201932 kb
Host smart-1eec6ad7-3232-426c-9a47-e65c89d47743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214762983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3214762983
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.253018712
Short name T581
Test name
Test status
Simulation time 2510263914 ps
CPU time 6.96 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:59 PM PDT 24
Peak memory 201912 kb
Host smart-00466e47-a553-4131-b728-775f4437164a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253018712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.253018712
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.2394604070
Short name T175
Test name
Test status
Simulation time 2108050081 ps
CPU time 5.96 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201872 kb
Host smart-4377dfa5-3a68-4bdf-8a5b-b078b88144cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394604070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2394604070
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.2801879588
Short name T764
Test name
Test status
Simulation time 9312196987 ps
CPU time 2.25 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 202016 kb
Host smart-e237dae6-2738-47ae-b738-4a94d1f30e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801879588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.2801879588
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3810511357
Short name T618
Test name
Test status
Simulation time 11377160728 ps
CPU time 4.04 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201896 kb
Host smart-b6359ed9-7dd0-42f7-bd97-bd840f3daf2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810511357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3810511357
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.1478607209
Short name T540
Test name
Test status
Simulation time 2024244313 ps
CPU time 3.2 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 202068 kb
Host smart-251ba4cb-218c-4a86-816d-836f4be8aeb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478607209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.1478607209
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.4207474333
Short name T22
Test name
Test status
Simulation time 3126450096 ps
CPU time 2.18 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201952 kb
Host smart-8e9f2e3f-3558-4600-94c6-3ae8eb03bb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207474333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.4
207474333
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.2795024906
Short name T254
Test name
Test status
Simulation time 123033558154 ps
CPU time 333.09 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 01:01:26 PM PDT 24
Peak memory 202028 kb
Host smart-842207da-42bf-4531-abb2-20541db339f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795024906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.2795024906
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1404334802
Short name T93
Test name
Test status
Simulation time 25585882663 ps
CPU time 35.54 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:56:26 PM PDT 24
Peak memory 202144 kb
Host smart-1eecddb8-2da1-4aed-a83a-bde0960d1f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404334802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.1404334802
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.82034257
Short name T544
Test name
Test status
Simulation time 3933030266 ps
CPU time 5.99 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:55:58 PM PDT 24
Peak memory 201900 kb
Host smart-25cfcd81-3f99-4929-a047-58712c1f8c14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82034257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_ec_pwr_on_rst.82034257
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.233442046
Short name T35
Test name
Test status
Simulation time 4486353144 ps
CPU time 3.06 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201956 kb
Host smart-e3d7e229-741e-4404-92a4-495fa56937d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233442046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctr
l_edge_detect.233442046
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.619032048
Short name T786
Test name
Test status
Simulation time 2618302680 ps
CPU time 4.59 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 202000 kb
Host smart-cca8e993-7e46-4774-9bfc-557649c51e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619032048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.619032048
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2834166101
Short name T722
Test name
Test status
Simulation time 2467894722 ps
CPU time 2.29 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201828 kb
Host smart-58ff9518-67be-4960-a74e-8a28226a3269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834166101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2834166101
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1521450356
Short name T431
Test name
Test status
Simulation time 2254287349 ps
CPU time 6.5 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201940 kb
Host smart-425e6732-754c-4113-9460-2f0688f8b0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521450356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1521450356
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.228966587
Short name T773
Test name
Test status
Simulation time 2528820655 ps
CPU time 2.37 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201972 kb
Host smart-ff9ac713-e7dd-4b22-998c-0981da5e1619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228966587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.228966587
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.3741248854
Short name T218
Test name
Test status
Simulation time 2116411817 ps
CPU time 3.48 seconds
Started Mar 28 12:55:47 PM PDT 24
Finished Mar 28 12:55:51 PM PDT 24
Peak memory 201876 kb
Host smart-b44bc98e-3001-4063-b8ce-3042cb8e6fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741248854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3741248854
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.3350034732
Short name T755
Test name
Test status
Simulation time 7061272261 ps
CPU time 19.64 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201700 kb
Host smart-bd9e7e88-d694-490a-97af-442e7a92061f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350034732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.3350034732
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.46950000
Short name T181
Test name
Test status
Simulation time 96501698402 ps
CPU time 36.51 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:56:28 PM PDT 24
Peak memory 210400 kb
Host smart-d4bff409-3785-40fd-a74b-2e999ac92aa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46950000 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.46950000
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.980377196
Short name T784
Test name
Test status
Simulation time 4509910659 ps
CPU time 2.3 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201744 kb
Host smart-bd8e2497-8713-4631-890a-723af0e8d67e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980377196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ultra_low_pwr.980377196
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.1175980950
Short name T695
Test name
Test status
Simulation time 2015802449 ps
CPU time 6.1 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:57 PM PDT 24
Peak memory 201876 kb
Host smart-b0e24a6a-8ccc-4fa8-8679-d110503c1deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175980950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.1175980950
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1888377975
Short name T731
Test name
Test status
Simulation time 182481059901 ps
CPU time 103.66 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:57:35 PM PDT 24
Peak memory 201992 kb
Host smart-c0e56ccc-a653-4242-968a-bce70c7971db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888377975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.1
888377975
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2378709706
Short name T368
Test name
Test status
Simulation time 176418031549 ps
CPU time 114.59 seconds
Started Mar 28 12:55:48 PM PDT 24
Finished Mar 28 12:57:42 PM PDT 24
Peak memory 202216 kb
Host smart-4f420850-ebf5-4008-ae50-50afb7de8aec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378709706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2378709706
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1124668754
Short name T757
Test name
Test status
Simulation time 88807798912 ps
CPU time 150.65 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:58:21 PM PDT 24
Peak memory 202188 kb
Host smart-1883eb61-8aa7-4bba-b0ee-17fdead64769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124668754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.1124668754
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.444049493
Short name T602
Test name
Test status
Simulation time 4669674027 ps
CPU time 3.58 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201924 kb
Host smart-11505043-9b26-458f-bda7-010a2ca1990b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444049493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ec_pwr_on_rst.444049493
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2706411820
Short name T793
Test name
Test status
Simulation time 4663299833 ps
CPU time 2.03 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 201960 kb
Host smart-c9dc0a94-f623-4aca-9130-ed6f608d5c03
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706411820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.2706411820
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.187793807
Short name T336
Test name
Test status
Simulation time 2630197342 ps
CPU time 2.41 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201928 kb
Host smart-0d75ae95-783e-4af1-9447-8aa3ecd562b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187793807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.187793807
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.399889138
Short name T470
Test name
Test status
Simulation time 2463303450 ps
CPU time 7.03 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201944 kb
Host smart-b8aa043e-a7c4-405b-baff-e02410461f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399889138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.399889138
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2408032914
Short name T421
Test name
Test status
Simulation time 2036784163 ps
CPU time 3.35 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201604 kb
Host smart-b261de45-d5df-460b-bd1f-9811549caecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408032914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.2408032914
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.895824961
Short name T328
Test name
Test status
Simulation time 2526704257 ps
CPU time 2.36 seconds
Started Mar 28 12:55:46 PM PDT 24
Finished Mar 28 12:55:49 PM PDT 24
Peak memory 201980 kb
Host smart-344842ef-27aa-44ac-91f3-b9e61be58a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895824961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.895824961
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.3294259254
Short name T301
Test name
Test status
Simulation time 2146849800 ps
CPU time 1.62 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201772 kb
Host smart-2d6f226d-a487-435d-b689-0a69d4f6a32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294259254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.3294259254
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.3410219313
Short name T105
Test name
Test status
Simulation time 217359713631 ps
CPU time 96.51 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:57:27 PM PDT 24
Peak memory 202124 kb
Host smart-03e724b7-6c55-471c-a3f0-2340f35765a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410219313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.3410219313
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1680696778
Short name T204
Test name
Test status
Simulation time 37156080721 ps
CPU time 26.04 seconds
Started Mar 28 12:55:48 PM PDT 24
Finished Mar 28 12:56:14 PM PDT 24
Peak memory 210520 kb
Host smart-b9c9d54b-9335-4aeb-a222-e84e8693d314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680696778 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1680696778
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2653992307
Short name T75
Test name
Test status
Simulation time 3150246510 ps
CPU time 7.16 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:56:02 PM PDT 24
Peak memory 201852 kb
Host smart-44111d8a-d110-4b14-a9d8-219d85e8eb18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653992307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.2653992307
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.2265997714
Short name T499
Test name
Test status
Simulation time 2124798048 ps
CPU time 0.98 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201952 kb
Host smart-c3b3b814-1d81-4e11-8766-2fd4cb275a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265997714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.2265997714
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3525046757
Short name T294
Test name
Test status
Simulation time 3336434343 ps
CPU time 2.72 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 202076 kb
Host smart-cd02239f-1c55-4d39-b645-2671eaa4f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525046757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.3
525046757
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.520297086
Short name T686
Test name
Test status
Simulation time 124215289619 ps
CPU time 156.36 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:58:29 PM PDT 24
Peak memory 202184 kb
Host smart-e20ab99b-c053-4eb0-8b5c-662bf9d0b6eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520297086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_combo_detect.520297086
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1008770896
Short name T99
Test name
Test status
Simulation time 22856979244 ps
CPU time 16.37 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 202108 kb
Host smart-72daa578-a7b8-4eac-9ef6-d0baf66f66b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008770896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.1008770896
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.128116156
Short name T154
Test name
Test status
Simulation time 4830783633 ps
CPU time 13.17 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:56:04 PM PDT 24
Peak memory 201936 kb
Host smart-cf4bc111-52d7-4525-8c9c-03131c1e90d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128116156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ec_pwr_on_rst.128116156
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.749386720
Short name T34
Test name
Test status
Simulation time 3918481036 ps
CPU time 2.01 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:51 PM PDT 24
Peak memory 201936 kb
Host smart-dc61498d-efc4-4167-b414-47acd6de7931
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749386720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctr
l_edge_detect.749386720
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.998071498
Short name T64
Test name
Test status
Simulation time 2612330155 ps
CPU time 6.87 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201932 kb
Host smart-4ff635c3-8e64-4311-9caa-c8ae87cfc44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998071498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.998071498
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.4171450576
Short name T524
Test name
Test status
Simulation time 2063123030 ps
CPU time 3.31 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201928 kb
Host smart-c9458804-d978-463f-a168-f3bfdfa14cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171450576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.4171450576
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.3500215020
Short name T681
Test name
Test status
Simulation time 2527459392 ps
CPU time 2.34 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:55:57 PM PDT 24
Peak memory 201972 kb
Host smart-1c22182f-a556-4bc1-ade5-6322098a1865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500215020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.3500215020
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.433155696
Short name T761
Test name
Test status
Simulation time 2133902663 ps
CPU time 2.08 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:51 PM PDT 24
Peak memory 201860 kb
Host smart-2680639b-e817-44e2-ac3a-26ffb7cb515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433155696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.433155696
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.3810615589
Short name T501
Test name
Test status
Simulation time 10470548756 ps
CPU time 14.67 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 201952 kb
Host smart-bc18eab2-bb69-4854-8abd-3ab5bb44c8e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810615589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.3810615589
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3465115797
Short name T656
Test name
Test status
Simulation time 4868495236 ps
CPU time 2.38 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201936 kb
Host smart-22c173a6-9a55-498a-8403-0e020d17f496
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465115797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.3465115797
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.2449441478
Short name T632
Test name
Test status
Simulation time 2040366083 ps
CPU time 1.51 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201968 kb
Host smart-48403eaa-5fa0-4ee1-9f3e-e1c75e5a7d4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449441478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.2449441478
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1463414598
Short name T732
Test name
Test status
Simulation time 3474564023 ps
CPU time 8.43 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:59 PM PDT 24
Peak memory 202032 kb
Host smart-7972d1c4-65e8-4892-aaaf-e6a42b66abe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463414598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.1
463414598
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1064941205
Short name T8
Test name
Test status
Simulation time 66563349733 ps
CPU time 169.36 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:58:41 PM PDT 24
Peak memory 201324 kb
Host smart-3085e842-b1b4-428a-89fa-e9542c571390
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064941205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.1064941205
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3529340044
Short name T493
Test name
Test status
Simulation time 2419957905 ps
CPU time 7.17 seconds
Started Mar 28 12:55:48 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 202000 kb
Host smart-0ebabbbe-1b8b-4fbb-85cc-5393db8c2428
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529340044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.3529340044
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.352760585
Short name T604
Test name
Test status
Simulation time 4250884750 ps
CPU time 3.6 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201972 kb
Host smart-754ace04-b73e-4f1a-9659-0e538bd4a78c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352760585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctr
l_edge_detect.352760585
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3834293650
Short name T476
Test name
Test status
Simulation time 2621049133 ps
CPU time 2.49 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 201728 kb
Host smart-73e56349-e740-4ee7-affd-79c6604a4171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834293650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3834293650
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2090466942
Short name T194
Test name
Test status
Simulation time 2463278466 ps
CPU time 7.41 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:58 PM PDT 24
Peak memory 201964 kb
Host smart-2829d6c1-49fe-464b-b380-4a970605a33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090466942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.2090466942
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.738386541
Short name T184
Test name
Test status
Simulation time 2255969220 ps
CPU time 2.66 seconds
Started Mar 28 12:55:56 PM PDT 24
Finished Mar 28 12:55:58 PM PDT 24
Peak memory 201864 kb
Host smart-62903034-1846-46ee-9d4f-6548e7d19f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738386541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.738386541
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.1576115259
Short name T619
Test name
Test status
Simulation time 2510635595 ps
CPU time 7.44 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:56:00 PM PDT 24
Peak memory 201880 kb
Host smart-43a71406-2816-4ea3-8a21-e08db616fa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576115259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.1576115259
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.4136009614
Short name T668
Test name
Test status
Simulation time 2110694219 ps
CPU time 6.34 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201796 kb
Host smart-bc11c543-8dfb-43e9-bc49-ea2250841aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136009614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.4136009614
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.2747165339
Short name T145
Test name
Test status
Simulation time 81315498463 ps
CPU time 58.42 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:56:50 PM PDT 24
Peak memory 202172 kb
Host smart-f71a95b1-5d22-4107-908d-714355ad3639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747165339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.2747165339
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1956144468
Short name T174
Test name
Test status
Simulation time 20015342069 ps
CPU time 14.25 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:56:08 PM PDT 24
Peak memory 210416 kb
Host smart-55a35390-1b19-433a-a684-5742a2eca8f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956144468 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.1956144468
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2300534134
Short name T591
Test name
Test status
Simulation time 3855134675 ps
CPU time 1.97 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201900 kb
Host smart-c63f3098-a747-4d86-9f6a-4da3d98850da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300534134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.2300534134
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.1112171965
Short name T758
Test name
Test status
Simulation time 2010373661 ps
CPU time 6.15 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:58 PM PDT 24
Peak memory 202016 kb
Host smart-b5ef2d07-8dd3-4a1d-b97b-8025c302189f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112171965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.1112171965
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2499314042
Short name T537
Test name
Test status
Simulation time 3324687232 ps
CPU time 9.37 seconds
Started Mar 28 12:55:57 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 202016 kb
Host smart-c4d452b7-8813-442b-9da1-7acc3a99cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499314042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
499314042
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.191044268
Short name T267
Test name
Test status
Simulation time 108968790740 ps
CPU time 123.75 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:57:58 PM PDT 24
Peak memory 202076 kb
Host smart-204cfe0e-e0e0-408c-b59c-aace3bdde2e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191044268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_combo_detect.191044268
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4048788379
Short name T471
Test name
Test status
Simulation time 3299452541 ps
CPU time 7.18 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201904 kb
Host smart-d7e9201d-cf24-49ca-9a18-b7cbcf8bf241
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048788379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.4048788379
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.1103631750
Short name T189
Test name
Test status
Simulation time 3307159388 ps
CPU time 1.67 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:55:57 PM PDT 24
Peak memory 201944 kb
Host smart-61f472a5-ad18-4465-a34a-d5a7e20b5fbb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103631750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.1103631750
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3415031634
Short name T736
Test name
Test status
Simulation time 2611214064 ps
CPU time 7.22 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:58 PM PDT 24
Peak memory 201192 kb
Host smart-96beb2db-70fc-4305-889b-edb86eb50e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415031634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.3415031634
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2762826049
Short name T762
Test name
Test status
Simulation time 2477815114 ps
CPU time 4.19 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201960 kb
Host smart-9813c9f4-e72f-462c-bced-e753bb7d34ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762826049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2762826049
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3956954684
Short name T685
Test name
Test status
Simulation time 2109663759 ps
CPU time 3.47 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:53 PM PDT 24
Peak memory 201884 kb
Host smart-09c65f8b-99c0-4913-9e96-bd26aea7f78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956954684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.3956954684
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.962651247
Short name T480
Test name
Test status
Simulation time 2528005580 ps
CPU time 2.19 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201940 kb
Host smart-162a5aaf-241c-4e9a-b290-0103bcb7ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962651247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.962651247
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.3000514546
Short name T146
Test name
Test status
Simulation time 2136231829 ps
CPU time 2.06 seconds
Started Mar 28 12:55:48 PM PDT 24
Finished Mar 28 12:55:51 PM PDT 24
Peak memory 201832 kb
Host smart-cafe2a09-712e-4906-88d8-86901f123554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000514546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.3000514546
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.280306234
Short name T609
Test name
Test status
Simulation time 63527557060 ps
CPU time 150.02 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:58:26 PM PDT 24
Peak memory 210444 kb
Host smart-20d49151-90fc-455a-8d2b-e2f93583c268
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280306234 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.280306234
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3759351409
Short name T747
Test name
Test status
Simulation time 3586973925 ps
CPU time 6.22 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:10 PM PDT 24
Peak memory 201820 kb
Host smart-26830246-0466-47a5-a7c8-89ad6331afb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759351409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.3759351409
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.601155267
Short name T497
Test name
Test status
Simulation time 2008883688 ps
CPU time 5.98 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201928 kb
Host smart-d4478f75-ac29-4210-99a3-2a0485bd0787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601155267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_tes
t.601155267
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.9395166
Short name T109
Test name
Test status
Simulation time 3297723002 ps
CPU time 10.01 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:56:04 PM PDT 24
Peak memory 201960 kb
Host smart-e822332c-0463-4f14-9d66-b0fab0ca4f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9395166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.9395166
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.134426830
Short name T258
Test name
Test status
Simulation time 129522151691 ps
CPU time 327.67 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 01:01:22 PM PDT 24
Peak memory 202144 kb
Host smart-100146b7-6eb3-4cf8-8170-d2bf6a6718df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134426830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_combo_detect.134426830
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3875379773
Short name T715
Test name
Test status
Simulation time 46130126176 ps
CPU time 60.25 seconds
Started Mar 28 12:55:56 PM PDT 24
Finished Mar 28 12:56:57 PM PDT 24
Peak memory 202120 kb
Host smart-c8a9cb9f-d0c3-45b5-a234-917056b17047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875379773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.3875379773
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2613225205
Short name T168
Test name
Test status
Simulation time 4754585475 ps
CPU time 13.67 seconds
Started Mar 28 12:55:46 PM PDT 24
Finished Mar 28 12:56:00 PM PDT 24
Peak memory 201932 kb
Host smart-0159d404-3b66-4688-8264-65fd630cc60f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613225205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.2613225205
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1975979695
Short name T754
Test name
Test status
Simulation time 3132869504 ps
CPU time 7.73 seconds
Started Mar 28 12:55:59 PM PDT 24
Finished Mar 28 12:56:07 PM PDT 24
Peak memory 201932 kb
Host smart-895b722f-f253-4790-b3dd-2571f4983c78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975979695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.1975979695
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.964380518
Short name T4
Test name
Test status
Simulation time 2610315638 ps
CPU time 7.31 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:56:00 PM PDT 24
Peak memory 201764 kb
Host smart-60ac99f9-2b10-4ff1-a76e-c4c896c50483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964380518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.964380518
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.2293924494
Short name T782
Test name
Test status
Simulation time 2459227912 ps
CPU time 7.15 seconds
Started Mar 28 12:56:02 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201948 kb
Host smart-dc60a3de-0989-4700-9c84-a5fee46a7c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293924494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.2293924494
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.531735681
Short name T186
Test name
Test status
Simulation time 2202755260 ps
CPU time 3.46 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:55:59 PM PDT 24
Peak memory 201884 kb
Host smart-5b738924-c073-4f25-9078-58253ffee4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531735681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.531735681
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1051700771
Short name T752
Test name
Test status
Simulation time 2511169691 ps
CPU time 7.15 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:56:02 PM PDT 24
Peak memory 201972 kb
Host smart-ba37cf89-c11f-4e13-a34b-a363c8b8f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051700771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1051700771
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.1772271068
Short name T246
Test name
Test status
Simulation time 2110086660 ps
CPU time 6.06 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:10 PM PDT 24
Peak memory 201860 kb
Host smart-cb163936-d86c-4a19-965a-e7692bdfb3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772271068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.1772271068
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3215831199
Short name T209
Test name
Test status
Simulation time 11913611607 ps
CPU time 29.52 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:56:21 PM PDT 24
Peak memory 201888 kb
Host smart-3a291220-4338-47dc-82a3-99ba75989f12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215831199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3215831199
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.646380202
Short name T155
Test name
Test status
Simulation time 38409334048 ps
CPU time 92.08 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 210528 kb
Host smart-538b5b00-efbb-4a4d-9366-a1075cc89af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646380202 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.646380202
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1731666433
Short name T713
Test name
Test status
Simulation time 3101859734 ps
CPU time 6.21 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:56:00 PM PDT 24
Peak memory 201904 kb
Host smart-05d592f3-ea34-413f-81fe-cca3467213a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731666433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.1731666433
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.4085739695
Short name T687
Test name
Test status
Simulation time 2037813941 ps
CPU time 1.92 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 202020 kb
Host smart-7167edf5-1336-4cfe-b4bb-b79dffd97764
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085739695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.4085739695
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.857539408
Short name T676
Test name
Test status
Simulation time 3377791714 ps
CPU time 2.32 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201992 kb
Host smart-0e8dd9da-0d0f-457a-9ea0-571b7f82f327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857539408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.857539408
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1768851120
Short name T705
Test name
Test status
Simulation time 147331903966 ps
CPU time 385.15 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 01:02:18 PM PDT 24
Peak memory 202124 kb
Host smart-4555d9d5-c702-484a-a060-ce2710e6de8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768851120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.1768851120
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1111770542
Short name T680
Test name
Test status
Simulation time 25113163184 ps
CPU time 16.59 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:56:07 PM PDT 24
Peak memory 202140 kb
Host smart-4181cd44-4ee4-4341-a2b2-c8d0f4b8a110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111770542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.1111770542
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.85063239
Short name T477
Test name
Test status
Simulation time 4999937587 ps
CPU time 4.29 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201920 kb
Host smart-b9e85f30-e168-4711-aa29-d95b4ffb03b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85063239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_ec_pwr_on_rst.85063239
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.337003360
Short name T514
Test name
Test status
Simulation time 3034134852 ps
CPU time 2.31 seconds
Started Mar 28 12:55:48 PM PDT 24
Finished Mar 28 12:55:51 PM PDT 24
Peak memory 201936 kb
Host smart-7393cef3-f2a2-4a4f-9cea-c6da70182979
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337003360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctr
l_edge_detect.337003360
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.1060452611
Short name T766
Test name
Test status
Simulation time 2610484526 ps
CPU time 6.13 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:55:58 PM PDT 24
Peak memory 201940 kb
Host smart-8ada1b51-f281-4269-af51-918daf13a2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060452611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.1060452611
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3606442178
Short name T311
Test name
Test status
Simulation time 2468137074 ps
CPU time 7.83 seconds
Started Mar 28 12:56:00 PM PDT 24
Finished Mar 28 12:56:08 PM PDT 24
Peak memory 201904 kb
Host smart-4bf1bde1-e6fc-49bf-a48a-9e002dd4e298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606442178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.3606442178
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.1415104015
Short name T492
Test name
Test status
Simulation time 2086512031 ps
CPU time 5.77 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:57 PM PDT 24
Peak memory 201836 kb
Host smart-4a8faa7b-7539-4095-9fa6-1e0900d6439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415104015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1415104015
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1197550933
Short name T583
Test name
Test status
Simulation time 2546865586 ps
CPU time 1.74 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:52 PM PDT 24
Peak memory 201972 kb
Host smart-a3ed4b7e-fe78-4fb0-84b6-3fd4abc0aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197550933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.1197550933
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.3462752126
Short name T419
Test name
Test status
Simulation time 2133143676 ps
CPU time 1.95 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201856 kb
Host smart-28cd53ed-b55c-433a-ae83-2bb364cfac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462752126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3462752126
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.2816801132
Short name T725
Test name
Test status
Simulation time 9171855828 ps
CPU time 6.86 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 202012 kb
Host smart-a7d8890b-924b-4e92-ba8c-6dd0198e1099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816801132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.2816801132
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.4223452888
Short name T151
Test name
Test status
Simulation time 75780998703 ps
CPU time 168.5 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:58:41 PM PDT 24
Peak memory 210512 kb
Host smart-55b9da95-0320-4da1-a0e6-78c8a9e09605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223452888 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.4223452888
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2053097953
Short name T576
Test name
Test status
Simulation time 5927290814 ps
CPU time 5.5 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201936 kb
Host smart-09913efb-ceac-4b8d-a838-fe36f25e451d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053097953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2053097953
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.1253331524
Short name T312
Test name
Test status
Simulation time 2025554879 ps
CPU time 2.01 seconds
Started Mar 28 12:55:01 PM PDT 24
Finished Mar 28 12:55:03 PM PDT 24
Peak memory 202016 kb
Host smart-afdafd91-00c4-4f08-a6fb-dea8af55d178
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253331524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.1253331524
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1460972599
Short name T700
Test name
Test status
Simulation time 3349470665 ps
CPU time 2.62 seconds
Started Mar 28 12:55:02 PM PDT 24
Finished Mar 28 12:55:05 PM PDT 24
Peak memory 202032 kb
Host smart-0ccc86b2-1771-4a6d-a5ed-c58c09806989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460972599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.1460972599
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1828194722
Short name T728
Test name
Test status
Simulation time 91007308151 ps
CPU time 227.4 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 12:58:56 PM PDT 24
Peak memory 202220 kb
Host smart-87bc431c-1654-4dac-a36c-7194fffb8ee2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828194722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.1828194722
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3487157853
Short name T413
Test name
Test status
Simulation time 2424704002 ps
CPU time 7.25 seconds
Started Mar 28 12:54:48 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 201920 kb
Host smart-ab660673-d79c-4e93-b7ef-9748178cbff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487157853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.3487157853
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3277648681
Short name T585
Test name
Test status
Simulation time 2530675648 ps
CPU time 7.37 seconds
Started Mar 28 12:54:54 PM PDT 24
Finished Mar 28 12:55:01 PM PDT 24
Peak memory 201944 kb
Host smart-87408a50-8ce9-401b-abf3-1fbdc461123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277648681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3277648681
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2859856633
Short name T226
Test name
Test status
Simulation time 4037229691 ps
CPU time 2.82 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 201896 kb
Host smart-d94b499f-6cd4-49e5-8f08-39550575e0bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859856633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.2859856633
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3443417290
Short name T621
Test name
Test status
Simulation time 2611990293 ps
CPU time 4.59 seconds
Started Mar 28 12:55:00 PM PDT 24
Finished Mar 28 12:55:06 PM PDT 24
Peak memory 201892 kb
Host smart-f8e49902-14f2-4170-a1cc-26951f5516da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443417290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.3443417290
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.264421355
Short name T637
Test name
Test status
Simulation time 2459572887 ps
CPU time 2.3 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:52 PM PDT 24
Peak memory 201928 kb
Host smart-f391321f-54c0-4fb4-802e-23f9a28ee3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264421355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.264421355
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3391649151
Short name T261
Test name
Test status
Simulation time 2194207433 ps
CPU time 1.56 seconds
Started Mar 28 12:54:52 PM PDT 24
Finished Mar 28 12:54:53 PM PDT 24
Peak memory 201856 kb
Host smart-019af633-df83-4852-9ffc-c3b693e939ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391649151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.3391649151
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.3394813666
Short name T744
Test name
Test status
Simulation time 2511396075 ps
CPU time 7.77 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:56 PM PDT 24
Peak memory 201932 kb
Host smart-08df0be9-a184-4344-ae9c-4dc45079a3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394813666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.3394813666
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.1816477135
Short name T288
Test name
Test status
Simulation time 22485529541 ps
CPU time 14.49 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:20 PM PDT 24
Peak memory 221876 kb
Host smart-b8f9083c-8f9c-43ea-a2dd-70c93af82b11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816477135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.1816477135
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.864974952
Short name T494
Test name
Test status
Simulation time 2135228940 ps
CPU time 1.92 seconds
Started Mar 28 12:54:49 PM PDT 24
Finished Mar 28 12:54:51 PM PDT 24
Peak memory 201852 kb
Host smart-0f6e7d39-684b-4ccc-88f6-8a79b74ec665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864974952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.864974952
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.1650902276
Short name T191
Test name
Test status
Simulation time 85606031174 ps
CPU time 60.86 seconds
Started Mar 28 12:54:58 PM PDT 24
Finished Mar 28 12:56:00 PM PDT 24
Peak memory 201992 kb
Host smart-ce0bdef0-f5ce-414b-bf5b-c3b25b5f69c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650902276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.1650902276
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1999121868
Short name T767
Test name
Test status
Simulation time 23615315987 ps
CPU time 63.93 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 202036 kb
Host smart-01561af8-67d2-49a7-a55c-ff55d4999f11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999121868 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.1999121868
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1885985359
Short name T627
Test name
Test status
Simulation time 7124724361 ps
CPU time 8.94 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:13 PM PDT 24
Peak memory 201904 kb
Host smart-8d7dcd17-3180-4eeb-946d-634f69c1c579
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885985359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.1885985359
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.3428013926
Short name T709
Test name
Test status
Simulation time 2038995714 ps
CPU time 1.88 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201936 kb
Host smart-287610ca-f04d-46d6-86bf-310cae7e10cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428013926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.3428013926
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1716354336
Short name T533
Test name
Test status
Simulation time 3232044695 ps
CPU time 4.8 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:55:59 PM PDT 24
Peak memory 202024 kb
Host smart-61d0bf9a-d287-4b52-bccd-7f4607c656ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716354336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.1
716354336
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.2717262867
Short name T359
Test name
Test status
Simulation time 173111859436 ps
CPU time 112.67 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:57:48 PM PDT 24
Peak memory 202080 kb
Host smart-d32359bf-cf3e-4bf7-8bb5-da386a4a3eff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717262867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.2717262867
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2951633147
Short name T23
Test name
Test status
Simulation time 22587815698 ps
CPU time 29.6 seconds
Started Mar 28 12:55:52 PM PDT 24
Finished Mar 28 12:56:21 PM PDT 24
Peak memory 202100 kb
Host smart-aa968238-fbc4-4b4a-990a-059b08943c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951633147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.2951633147
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3146979858
Short name T595
Test name
Test status
Simulation time 4496306875 ps
CPU time 2.01 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201896 kb
Host smart-00cf3c98-6ba8-4a68-ac1f-ec0fbca3fca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146979858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.3146979858
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.514384568
Short name T677
Test name
Test status
Simulation time 2935750594 ps
CPU time 5.88 seconds
Started Mar 28 12:55:49 PM PDT 24
Finished Mar 28 12:55:55 PM PDT 24
Peak memory 201860 kb
Host smart-0b3b8067-6d21-48de-b8bb-617fea66683a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514384568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctr
l_edge_detect.514384568
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1382683980
Short name T158
Test name
Test status
Simulation time 2611979029 ps
CPU time 7.48 seconds
Started Mar 28 12:55:51 PM PDT 24
Finished Mar 28 12:55:59 PM PDT 24
Peak memory 201904 kb
Host smart-ccd30989-3505-4e47-844f-5cebc673ce53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382683980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1382683980
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.2814504696
Short name T319
Test name
Test status
Simulation time 2466268675 ps
CPU time 3.7 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:54 PM PDT 24
Peak memory 201904 kb
Host smart-1c99477b-2afb-4afe-a091-c0038159662e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814504696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.2814504696
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.4134735953
Short name T546
Test name
Test status
Simulation time 2204037300 ps
CPU time 6.38 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:10 PM PDT 24
Peak memory 201796 kb
Host smart-c4facd4f-9d1d-49ac-a11e-1b857268af2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134735953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.4134735953
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1707228781
Short name T309
Test name
Test status
Simulation time 2601097753 ps
CPU time 1.21 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:07 PM PDT 24
Peak memory 201840 kb
Host smart-ca237cc1-e5ed-4bd6-9f85-a6305704507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707228781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1707228781
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.1807463699
Short name T230
Test name
Test status
Simulation time 2113710689 ps
CPU time 3.48 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:55:57 PM PDT 24
Peak memory 201892 kb
Host smart-790b2758-2e88-4e4c-8a56-6cf2ccb47e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807463699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1807463699
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.3387104948
Short name T178
Test name
Test status
Simulation time 323429475936 ps
CPU time 75.77 seconds
Started Mar 28 12:55:59 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 202004 kb
Host smart-d1e495fc-735f-4574-9d86-5c1dbb67d83e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387104948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.3387104948
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3216238339
Short name T292
Test name
Test status
Simulation time 34277941608 ps
CPU time 47.33 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:56:41 PM PDT 24
Peak memory 202032 kb
Host smart-58edf50d-fb23-45ef-8879-8acb6e5ad323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216238339 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.3216238339
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2885578214
Short name T84
Test name
Test status
Simulation time 5694700058 ps
CPU time 1.52 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 201820 kb
Host smart-f51fb9ff-b08e-4368-8d42-7a0ee7465ed6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885578214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.2885578214
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.2276262231
Short name T310
Test name
Test status
Simulation time 2013030676 ps
CPU time 5.55 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 202020 kb
Host smart-c62932dc-bffc-4585-9326-4eb75af0e361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276262231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.2276262231
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1464330567
Short name T611
Test name
Test status
Simulation time 3609895952 ps
CPU time 5.65 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:56:01 PM PDT 24
Peak memory 201964 kb
Host smart-87d8881e-ec55-4701-b7c8-751bacbaa08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464330567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.1
464330567
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.3798469155
Short name T612
Test name
Test status
Simulation time 155958144020 ps
CPU time 111.19 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:57:45 PM PDT 24
Peak memory 201936 kb
Host smart-fe2cf4e3-452b-4194-ad57-92af2d2a3a80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798469155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.3798469155
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2862257269
Short name T253
Test name
Test status
Simulation time 103299895089 ps
CPU time 278.36 seconds
Started Mar 28 12:56:01 PM PDT 24
Finished Mar 28 01:00:39 PM PDT 24
Peak memory 202164 kb
Host smart-5ac85e84-767d-4e14-ab72-7eb8f517af19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862257269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2862257269
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.435055203
Short name T718
Test name
Test status
Simulation time 3064900548 ps
CPU time 2.68 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201796 kb
Host smart-fab2f6a7-b3d9-48ce-b64f-e3e8257fe19a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435055203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_ec_pwr_on_rst.435055203
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.3037027088
Short name T615
Test name
Test status
Simulation time 3314609951 ps
CPU time 6.71 seconds
Started Mar 28 12:56:01 PM PDT 24
Finished Mar 28 12:56:08 PM PDT 24
Peak memory 201900 kb
Host smart-9fefe0f2-179b-48b3-a699-0d0bdbccb197
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037027088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.3037027088
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.781430407
Short name T605
Test name
Test status
Simulation time 2627710502 ps
CPU time 2.01 seconds
Started Mar 28 12:56:02 PM PDT 24
Finished Mar 28 12:56:04 PM PDT 24
Peak memory 201952 kb
Host smart-74329045-3321-41b5-9e68-dcfb80e4f0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781430407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.781430407
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2624017237
Short name T61
Test name
Test status
Simulation time 2453937228 ps
CPU time 7.6 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:13 PM PDT 24
Peak memory 201824 kb
Host smart-d5c489d2-f145-47a3-9178-f03f02323210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624017237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.2624017237
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2809743098
Short name T573
Test name
Test status
Simulation time 2160968047 ps
CPU time 6.13 seconds
Started Mar 28 12:55:50 PM PDT 24
Finished Mar 28 12:55:56 PM PDT 24
Peak memory 201884 kb
Host smart-060ae487-2bd1-40be-9205-050d9bd252d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809743098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2809743098
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2049598767
Short name T526
Test name
Test status
Simulation time 2509160962 ps
CPU time 7.38 seconds
Started Mar 28 12:55:54 PM PDT 24
Finished Mar 28 12:56:02 PM PDT 24
Peak memory 201964 kb
Host smart-f5bafca5-3492-45fd-b4b3-8809da5c3470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049598767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.2049598767
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.156893284
Short name T444
Test name
Test status
Simulation time 2107599433 ps
CPU time 6.31 seconds
Started Mar 28 12:55:53 PM PDT 24
Finished Mar 28 12:55:59 PM PDT 24
Peak memory 201836 kb
Host smart-53886192-8d52-4f14-a5ca-fcd9eef96ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156893284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.156893284
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.1700902143
Short name T315
Test name
Test status
Simulation time 13794870655 ps
CPU time 18.88 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:24 PM PDT 24
Peak memory 201864 kb
Host smart-a74ecc26-7d47-4ab0-8ed9-ea0f0f681739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700902143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.1700902143
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.835982713
Short name T167
Test name
Test status
Simulation time 146471398212 ps
CPU time 89.47 seconds
Started Mar 28 12:56:02 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 210540 kb
Host smart-dcc953d2-201c-44c8-92a0-51c54878908f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835982713 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.835982713
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3465937479
Short name T20
Test name
Test status
Simulation time 2738293355 ps
CPU time 3.54 seconds
Started Mar 28 12:55:55 PM PDT 24
Finished Mar 28 12:55:59 PM PDT 24
Peak memory 201904 kb
Host smart-5a679a39-f817-44c2-b516-8be2727bfbf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465937479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.3465937479
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.3485111652
Short name T652
Test name
Test status
Simulation time 2025151449 ps
CPU time 1.67 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 201912 kb
Host smart-de28e7d8-c698-40df-9436-02a3eb3a3a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485111652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.3485111652
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.872220887
Short name T654
Test name
Test status
Simulation time 3324811720 ps
CPU time 8.97 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 12:56:18 PM PDT 24
Peak memory 201960 kb
Host smart-00181fbe-3be3-4ddd-8bb5-e02101a18803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872220887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.872220887
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.1314883184
Short name T110
Test name
Test status
Simulation time 33279077299 ps
CPU time 22.63 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:28 PM PDT 24
Peak memory 201764 kb
Host smart-b939bd7a-ef14-46c5-88ca-f8ae530b62d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314883184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.1314883184
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4226223905
Short name T505
Test name
Test status
Simulation time 24829151303 ps
CPU time 69.92 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 12:57:18 PM PDT 24
Peak memory 202152 kb
Host smart-cb367736-85ec-419f-aedd-f45a8e1ef30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226223905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.4226223905
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.436414689
Short name T684
Test name
Test status
Simulation time 3040576417 ps
CPU time 4.81 seconds
Started Mar 28 12:56:01 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 201948 kb
Host smart-09a1c035-8a31-4ca7-b357-dfa35775186a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436414689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_ec_pwr_on_rst.436414689
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.4150565664
Short name T177
Test name
Test status
Simulation time 5458889762 ps
CPU time 3.23 seconds
Started Mar 28 12:56:02 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 201972 kb
Host smart-c6e66dac-7240-426e-b300-9f0a64b0175b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150565664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.4150565664
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3299991744
Short name T434
Test name
Test status
Simulation time 2608784954 ps
CPU time 7.5 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201716 kb
Host smart-ae0f5d71-0e4f-442b-8c30-4eb827c63e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299991744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3299991744
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3136819104
Short name T156
Test name
Test status
Simulation time 2449022931 ps
CPU time 2.53 seconds
Started Mar 28 12:56:02 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 201892 kb
Host smart-09c4c015-bc89-4c45-afda-d6bc4c85f117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136819104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3136819104
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1501022897
Short name T428
Test name
Test status
Simulation time 2168989909 ps
CPU time 3.41 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:10 PM PDT 24
Peak memory 201896 kb
Host smart-eb646afd-a467-4af7-b535-f834ddf07298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501022897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1501022897
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3710708563
Short name T216
Test name
Test status
Simulation time 2512467969 ps
CPU time 7.03 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:11 PM PDT 24
Peak memory 201932 kb
Host smart-2666550e-3bae-46ad-ab3f-3077b46e43f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710708563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.3710708563
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.3817729674
Short name T426
Test name
Test status
Simulation time 2111257737 ps
CPU time 5.83 seconds
Started Mar 28 12:56:01 PM PDT 24
Finished Mar 28 12:56:07 PM PDT 24
Peak memory 201864 kb
Host smart-639e7ed5-cc66-4136-ad7b-dc83c4357106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817729674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3817729674
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3268990670
Short name T746
Test name
Test status
Simulation time 3647038472 ps
CPU time 7.36 seconds
Started Mar 28 12:55:59 PM PDT 24
Finished Mar 28 12:56:07 PM PDT 24
Peak memory 201960 kb
Host smart-6787a2f6-8d94-434d-af59-8b247a6eec51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268990670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.3268990670
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.2870209561
Short name T698
Test name
Test status
Simulation time 2147899594 ps
CPU time 0.99 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 201960 kb
Host smart-55df0197-8f36-4af2-ac82-424cd2b64754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870209561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.2870209561
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3116978273
Short name T224
Test name
Test status
Simulation time 3410381644 ps
CPU time 3.06 seconds
Started Mar 28 12:56:02 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 202016 kb
Host smart-9625718b-0f29-4cc1-961c-88a48b1e6632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116978273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.3
116978273
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.1794745221
Short name T366
Test name
Test status
Simulation time 78557320423 ps
CPU time 48.65 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:52 PM PDT 24
Peak memory 202104 kb
Host smart-c33e7963-cf9c-43cd-b5b7-fc077578b84f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794745221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.1794745221
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1997335744
Short name T249
Test name
Test status
Simulation time 85559821848 ps
CPU time 235.35 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 01:00:03 PM PDT 24
Peak memory 202144 kb
Host smart-c56c5bae-9dda-4751-b80e-5a8e93e60719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997335744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.1997335744
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3485672648
Short name T525
Test name
Test status
Simulation time 4488577434 ps
CPU time 3.79 seconds
Started Mar 28 12:56:01 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 201956 kb
Host smart-1a3cc15a-dd9b-48cc-9bec-87c75020df2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485672648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.3485672648
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3580288183
Short name T6
Test name
Test status
Simulation time 2831961867 ps
CPU time 7.14 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:13 PM PDT 24
Peak memory 202012 kb
Host smart-f3e87a79-b410-4d9f-b1f7-e252035d705e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580288183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3580288183
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1425879432
Short name T327
Test name
Test status
Simulation time 2640873882 ps
CPU time 2.13 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:08 PM PDT 24
Peak memory 201824 kb
Host smart-6a574f34-b8b0-4ad3-9a50-b012f2194d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425879432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.1425879432
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.3467031660
Short name T508
Test name
Test status
Simulation time 2460407456 ps
CPU time 6.64 seconds
Started Mar 28 12:56:01 PM PDT 24
Finished Mar 28 12:56:08 PM PDT 24
Peak memory 201924 kb
Host smart-6cf66345-9814-48e9-a712-c638e10e9a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467031660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.3467031660
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.237755364
Short name T756
Test name
Test status
Simulation time 2187401686 ps
CPU time 6.18 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201908 kb
Host smart-d75b061b-e708-46fc-b82c-f09eaf4dfe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237755364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.237755364
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2071024718
Short name T479
Test name
Test status
Simulation time 2530307289 ps
CPU time 2.24 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 201980 kb
Host smart-233c59f9-a689-4960-b9de-e523b30d0c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071024718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.2071024718
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.1482386866
Short name T653
Test name
Test status
Simulation time 2108711618 ps
CPU time 6.18 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201876 kb
Host smart-76b7db52-e073-4fae-a498-58db2e07385e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482386866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1482386866
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.2820512778
Short name T646
Test name
Test status
Simulation time 8822185728 ps
CPU time 4.42 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:07 PM PDT 24
Peak memory 201836 kb
Host smart-aa3344df-6189-44ca-9500-5528f5264bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820512778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.2820512778
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3351776863
Short name T406
Test name
Test status
Simulation time 446218642162 ps
CPU time 205.4 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:59:31 PM PDT 24
Peak memory 218496 kb
Host smart-6dee7b61-2712-4707-85e9-159c9eeb22ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351776863 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3351776863
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1929083104
Short name T121
Test name
Test status
Simulation time 4802355748 ps
CPU time 2.42 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 201844 kb
Host smart-805753db-6e04-4f21-a804-58df4cc5b645
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929083104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.1929083104
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.4226721623
Short name T791
Test name
Test status
Simulation time 2014539668 ps
CPU time 6.1 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:13 PM PDT 24
Peak memory 202020 kb
Host smart-1a6d275a-a964-406d-a173-efe10ffc5e36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226721623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.4226721623
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2453343730
Short name T465
Test name
Test status
Simulation time 3647064353 ps
CPU time 10.72 seconds
Started Mar 28 12:56:02 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201992 kb
Host smart-fa67b6fc-71b8-4a46-9947-4a7a15645fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453343730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2
453343730
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.829775145
Short name T710
Test name
Test status
Simulation time 86513357423 ps
CPU time 240.78 seconds
Started Mar 28 12:56:01 PM PDT 24
Finished Mar 28 01:00:02 PM PDT 24
Peak memory 202192 kb
Host smart-85f9511a-1b21-443d-9f06-4568eb9ce4e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829775145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_combo_detect.829775145
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.4249803884
Short name T778
Test name
Test status
Simulation time 26330265032 ps
CPU time 68.37 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 12:57:16 PM PDT 24
Peak memory 202164 kb
Host smart-236b3a33-9c0c-4898-9ac1-3a2d90ef7ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249803884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.4249803884
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2703419290
Short name T667
Test name
Test status
Simulation time 3681238613 ps
CPU time 3 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 201864 kb
Host smart-db2b41ec-9641-4c5c-85b5-1292c819d8ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703419290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.2703419290
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1561258582
Short name T78
Test name
Test status
Simulation time 3230996081 ps
CPU time 1.91 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 201972 kb
Host smart-99129958-5404-4f39-a0f4-94d7183a827b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561258582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1561258582
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.300059214
Short name T765
Test name
Test status
Simulation time 2632603705 ps
CPU time 2.18 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:08 PM PDT 24
Peak memory 201952 kb
Host smart-2168045b-5076-4b0c-8590-b918d8ac39af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300059214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.300059214
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2771086101
Short name T21
Test name
Test status
Simulation time 2471710509 ps
CPU time 7.63 seconds
Started Mar 28 12:56:02 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201964 kb
Host smart-df227090-4f33-4879-b91b-96ad02095902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771086101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2771086101
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.2953975023
Short name T531
Test name
Test status
Simulation time 2130496502 ps
CPU time 3.59 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:10 PM PDT 24
Peak memory 201836 kb
Host smart-4d61d769-5ab9-45b7-a899-9d159420cd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953975023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2953975023
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.331431088
Short name T741
Test name
Test status
Simulation time 2519604768 ps
CPU time 4.21 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:08 PM PDT 24
Peak memory 201912 kb
Host smart-f85747ff-01c7-4cde-afde-2efe4c78f460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331431088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.331431088
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.818124487
Short name T115
Test name
Test status
Simulation time 2111192355 ps
CPU time 6.24 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201892 kb
Host smart-c7c5fa47-f726-4e38-82be-abfd945ff2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818124487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.818124487
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2940688039
Short name T126
Test name
Test status
Simulation time 111297517867 ps
CPU time 67.87 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:57:13 PM PDT 24
Peak memory 210352 kb
Host smart-ab52cc67-48a1-4d13-825b-e60011531c2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940688039 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2940688039
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.871336106
Short name T143
Test name
Test status
Simulation time 2010545459 ps
CPU time 5.34 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201996 kb
Host smart-80799c42-7a6f-4341-8e9c-7ccf73e9eb10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871336106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_tes
t.871336106
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.4042357907
Short name T231
Test name
Test status
Simulation time 3159546638 ps
CPU time 2.68 seconds
Started Mar 28 12:56:01 PM PDT 24
Finished Mar 28 12:56:04 PM PDT 24
Peak memory 202004 kb
Host smart-6f93d40b-2151-4774-b4d7-66c507f6ee87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042357907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.4
042357907
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.3431408524
Short name T120
Test name
Test status
Simulation time 135009153073 ps
CPU time 368.75 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 01:02:12 PM PDT 24
Peak memory 202224 kb
Host smart-942e7a16-254d-48c0-8262-7a80dad0b582
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431408524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.3431408524
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1019745601
Short name T38
Test name
Test status
Simulation time 25578119081 ps
CPU time 64.59 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 202208 kb
Host smart-0a907a7f-b8f7-4503-a48e-96c3382c4ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019745601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.1019745601
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3156968396
Short name T584
Test name
Test status
Simulation time 4612601106 ps
CPU time 13.18 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:17 PM PDT 24
Peak memory 201808 kb
Host smart-b2f74f62-6359-40e5-a8d5-18e6b8c99c18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156968396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.3156968396
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.2728480950
Short name T742
Test name
Test status
Simulation time 3719564449 ps
CPU time 7.17 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:14 PM PDT 24
Peak memory 201944 kb
Host smart-81aa6003-c79d-44df-ad7a-803f56ac32c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728480950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.2728480950
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1870563511
Short name T208
Test name
Test status
Simulation time 2615249388 ps
CPU time 4.2 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201944 kb
Host smart-eb7f5e5d-f40a-491a-9f62-8ee973495c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870563511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.1870563511
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.3042175753
Short name T712
Test name
Test status
Simulation time 2460498581 ps
CPU time 4.24 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201996 kb
Host smart-722f9ceb-7806-44b1-9bd0-7d4f83e96391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042175753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.3042175753
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.2110901381
Short name T536
Test name
Test status
Simulation time 2157712488 ps
CPU time 6.25 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:10 PM PDT 24
Peak memory 201948 kb
Host smart-50090c6a-3631-4b86-8ae6-89a1403c6675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110901381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.2110901381
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1638146280
Short name T437
Test name
Test status
Simulation time 2529865651 ps
CPU time 2.61 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201968 kb
Host smart-26eaf275-0cc4-42ff-8861-84284171ab9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638146280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1638146280
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.3852530522
Short name T650
Test name
Test status
Simulation time 2112444134 ps
CPU time 3.52 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 201804 kb
Host smart-e25fa290-ff8d-428c-b7b6-ac6ba2d93c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852530522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.3852530522
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.290659761
Short name T624
Test name
Test status
Simulation time 12665024067 ps
CPU time 8.66 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201904 kb
Host smart-1eda0513-39c6-44c6-9949-ff355b9f1121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290659761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_st
ress_all.290659761
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3417177615
Short name T73
Test name
Test status
Simulation time 6036978084 ps
CPU time 7.57 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201916 kb
Host smart-93e6e7e9-fff6-46ed-bbf5-f007dfd7320e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417177615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.3417177615
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.4261829741
Short name T789
Test name
Test status
Simulation time 2158092160 ps
CPU time 0.88 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 202012 kb
Host smart-928e19ba-d206-47fe-a9a1-76bc25cc9b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261829741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.4261829741
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1302280816
Short name T688
Test name
Test status
Simulation time 3852707251 ps
CPU time 5.29 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:11 PM PDT 24
Peak memory 201876 kb
Host smart-2f60f85e-f241-4a98-8b90-2afb318d41ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302280816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.1
302280816
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.356848551
Short name T697
Test name
Test status
Simulation time 95502513630 ps
CPU time 61.6 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:57:06 PM PDT 24
Peak memory 202204 kb
Host smart-6b414ca1-1529-426e-913e-0ae628d25827
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356848551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.356848551
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3721815291
Short name T669
Test name
Test status
Simulation time 25581690523 ps
CPU time 71.2 seconds
Started Mar 28 12:56:11 PM PDT 24
Finished Mar 28 12:57:22 PM PDT 24
Peak memory 202232 kb
Host smart-2ac40eb7-aa0e-43bb-a2b6-11e17cbc2a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721815291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.3721815291
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1581085328
Short name T548
Test name
Test status
Simulation time 4968443104 ps
CPU time 8.75 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 12:56:17 PM PDT 24
Peak memory 201884 kb
Host smart-a563143c-c4a4-4ad2-ad9f-14b47bc37f99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581085328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.1581085328
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2665035029
Short name T31
Test name
Test status
Simulation time 483385461857 ps
CPU time 52.53 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:57 PM PDT 24
Peak memory 201924 kb
Host smart-abf32bde-f022-418c-a7dc-413c6d8dc69a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665035029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.2665035029
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2851217403
Short name T551
Test name
Test status
Simulation time 2613526111 ps
CPU time 4.94 seconds
Started Mar 28 12:56:10 PM PDT 24
Finished Mar 28 12:56:15 PM PDT 24
Peak memory 201964 kb
Host smart-391c22f7-8609-43fd-9874-d9693b864ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851217403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.2851217403
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3187237247
Short name T642
Test name
Test status
Simulation time 2477190337 ps
CPU time 2.55 seconds
Started Mar 28 12:56:02 PM PDT 24
Finished Mar 28 12:56:05 PM PDT 24
Peak memory 201956 kb
Host smart-46d5b078-ae73-499b-b67c-e2b987b7fe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187237247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3187237247
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1521207004
Short name T187
Test name
Test status
Simulation time 2020511551 ps
CPU time 6.09 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201832 kb
Host smart-ccfa3316-c700-458d-a00d-0c5d2101a5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521207004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1521207004
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2556290777
Short name T66
Test name
Test status
Simulation time 2516822858 ps
CPU time 4.05 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:07 PM PDT 24
Peak memory 201916 kb
Host smart-982e4f03-3eb5-4ea0-9919-ba435bea193c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556290777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2556290777
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.1958041951
Short name T651
Test name
Test status
Simulation time 2133512469 ps
CPU time 1.99 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201860 kb
Host smart-f190b63f-ece0-417f-9215-7b30dd7ddf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958041951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1958041951
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.1276268406
Short name T363
Test name
Test status
Simulation time 161499062332 ps
CPU time 215.36 seconds
Started Mar 28 12:56:10 PM PDT 24
Finished Mar 28 12:59:45 PM PDT 24
Peak memory 202212 kb
Host smart-86bb4619-4764-425c-b59c-02b8a85c9079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276268406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.1276268406
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1852394558
Short name T239
Test name
Test status
Simulation time 643515828813 ps
CPU time 193.92 seconds
Started Mar 28 12:56:11 PM PDT 24
Finished Mar 28 12:59:25 PM PDT 24
Peak memory 218768 kb
Host smart-96f6c474-e4f9-4dfd-9c02-8770de78e635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852394558 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.1852394558
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.424922996
Short name T137
Test name
Test status
Simulation time 9056079089 ps
CPU time 5.27 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 12:56:13 PM PDT 24
Peak memory 201968 kb
Host smart-ab07ba6a-7ff9-483a-a0ce-938fbdc3806d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424922996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ultra_low_pwr.424922996
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.563588940
Short name T608
Test name
Test status
Simulation time 2013532529 ps
CPU time 6.05 seconds
Started Mar 28 12:56:10 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201960 kb
Host smart-4729a64c-33dd-4753-afc2-93e6888fca5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563588940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_tes
t.563588940
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3234653459
Short name T296
Test name
Test status
Simulation time 3267991811 ps
CPU time 3.88 seconds
Started Mar 28 12:56:09 PM PDT 24
Finished Mar 28 12:56:13 PM PDT 24
Peak memory 201928 kb
Host smart-52780413-63c4-4fe3-ae8e-93be591dcf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234653459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.3
234653459
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3121938754
Short name T89
Test name
Test status
Simulation time 164799809259 ps
CPU time 235.08 seconds
Started Mar 28 12:56:11 PM PDT 24
Finished Mar 28 01:00:06 PM PDT 24
Peak memory 202140 kb
Host smart-0257b8da-1490-4c2a-a952-f976c83bbf26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121938754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.3121938754
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.880707164
Short name T264
Test name
Test status
Simulation time 84962480020 ps
CPU time 224.33 seconds
Started Mar 28 12:56:10 PM PDT 24
Finished Mar 28 12:59:54 PM PDT 24
Peak memory 202104 kb
Host smart-fdf0c2c4-1b1b-4e95-8fc4-b1839e66cb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880707164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi
th_pre_cond.880707164
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.4117940849
Short name T53
Test name
Test status
Simulation time 4006736143 ps
CPU time 2.95 seconds
Started Mar 28 12:56:10 PM PDT 24
Finished Mar 28 12:56:13 PM PDT 24
Peak memory 201868 kb
Host smart-4fe9568f-65af-4499-a543-5f8e4a080ecc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117940849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.4117940849
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.2477536145
Short name T183
Test name
Test status
Simulation time 5471783618 ps
CPU time 5.61 seconds
Started Mar 28 12:56:10 PM PDT 24
Finished Mar 28 12:56:15 PM PDT 24
Peak memory 201872 kb
Host smart-9cccf9bb-54a6-4416-aea3-388cb5a55753
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477536145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.2477536145
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1845678987
Short name T446
Test name
Test status
Simulation time 2619845131 ps
CPU time 4.13 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:11 PM PDT 24
Peak memory 201868 kb
Host smart-87cc589a-3dc5-4696-a3cf-518edcd54622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845678987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.1845678987
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2095323863
Short name T318
Test name
Test status
Simulation time 2485150304 ps
CPU time 1.52 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 201928 kb
Host smart-0f2f18a6-2942-4a09-85ef-4489acb86583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095323863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2095323863
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1572420836
Short name T518
Test name
Test status
Simulation time 2153647777 ps
CPU time 6.53 seconds
Started Mar 28 12:56:08 PM PDT 24
Finished Mar 28 12:56:14 PM PDT 24
Peak memory 201904 kb
Host smart-7787118c-76dd-4a69-87ae-f1b287b44205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572420836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.1572420836
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2163824308
Short name T542
Test name
Test status
Simulation time 2533448006 ps
CPU time 2.09 seconds
Started Mar 28 12:56:11 PM PDT 24
Finished Mar 28 12:56:13 PM PDT 24
Peak memory 201972 kb
Host smart-019c18bc-c668-4882-a0d0-1b9c5c9486bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163824308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2163824308
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.2216133961
Short name T774
Test name
Test status
Simulation time 2112674765 ps
CPU time 5.63 seconds
Started Mar 28 12:56:03 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201828 kb
Host smart-c128c4d7-2344-4c76-82b0-eef3c0263674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216133961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.2216133961
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.1181835895
Short name T217
Test name
Test status
Simulation time 2519056667722 ps
CPU time 6057.58 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 02:37:05 PM PDT 24
Peak memory 201912 kb
Host smart-39482e96-00c9-4676-a987-0d662ba5761f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181835895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.1181835895
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2157976153
Short name T202
Test name
Test status
Simulation time 41586874774 ps
CPU time 111.25 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:57:55 PM PDT 24
Peak memory 210540 kb
Host smart-a88f9891-4592-4e56-a768-9493db8ade92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157976153 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2157976153
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1175713689
Short name T51
Test name
Test status
Simulation time 4160492136 ps
CPU time 2.06 seconds
Started Mar 28 12:56:09 PM PDT 24
Finished Mar 28 12:56:11 PM PDT 24
Peak memory 201872 kb
Host smart-e2bf1bfc-8488-404a-856e-d9d9c45a9e96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175713689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.1175713689
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3740293044
Short name T473
Test name
Test status
Simulation time 2035951500 ps
CPU time 3.13 seconds
Started Mar 28 12:56:13 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201916 kb
Host smart-b769ea1f-867d-4bf1-9bd6-6f4f7b67c5d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740293044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3740293044
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3369439250
Short name T107
Test name
Test status
Simulation time 96036291622 ps
CPU time 69.01 seconds
Started Mar 28 12:56:12 PM PDT 24
Finished Mar 28 12:57:21 PM PDT 24
Peak memory 201976 kb
Host smart-8a82c9b4-1bdd-436c-8daf-ead6e512891e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369439250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3
369439250
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.1691330665
Short name T552
Test name
Test status
Simulation time 92989647593 ps
CPU time 151.02 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:58:36 PM PDT 24
Peak memory 202032 kb
Host smart-8fc63db4-075d-4641-9e08-c995af04a9ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691330665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.1691330665
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3648648233
Short name T582
Test name
Test status
Simulation time 31698213038 ps
CPU time 89.05 seconds
Started Mar 28 12:56:12 PM PDT 24
Finished Mar 28 12:57:41 PM PDT 24
Peak memory 202164 kb
Host smart-fb86e1c5-3d47-499f-ad36-f16d71f9cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648648233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.3648648233
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.675994093
Short name T147
Test name
Test status
Simulation time 4720242792 ps
CPU time 3.88 seconds
Started Mar 28 12:56:12 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201900 kb
Host smart-78cfb943-f3bb-408f-872a-93b652036e0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675994093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.675994093
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.2282462159
Short name T227
Test name
Test status
Simulation time 17608692576 ps
CPU time 23.73 seconds
Started Mar 28 12:56:13 PM PDT 24
Finished Mar 28 12:56:37 PM PDT 24
Peak memory 201852 kb
Host smart-c64e95a1-739f-4bff-8fd8-388124425792
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282462159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.2282462159
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.577598283
Short name T452
Test name
Test status
Simulation time 2620717024 ps
CPU time 3.72 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:11 PM PDT 24
Peak memory 201832 kb
Host smart-24a9941c-4bd2-4310-8faf-ffb4a347fcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577598283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.577598283
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3500005904
Short name T599
Test name
Test status
Simulation time 2464368838 ps
CPU time 8.02 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:15 PM PDT 24
Peak memory 201840 kb
Host smart-14cd6b11-4953-47c1-86df-f7d6f443d986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500005904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3500005904
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3055558403
Short name T235
Test name
Test status
Simulation time 2275776259 ps
CPU time 2 seconds
Started Mar 28 12:56:04 PM PDT 24
Finished Mar 28 12:56:06 PM PDT 24
Peak memory 201864 kb
Host smart-b6aa331d-66ab-405b-a11c-6ec399d28d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055558403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3055558403
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1731196297
Short name T213
Test name
Test status
Simulation time 2510939982 ps
CPU time 6.97 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:14 PM PDT 24
Peak memory 201888 kb
Host smart-749d925d-bcc8-48da-8f59-76c8dd464993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731196297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1731196297
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.1673754857
Short name T753
Test name
Test status
Simulation time 2127611155 ps
CPU time 1.93 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:09 PM PDT 24
Peak memory 201784 kb
Host smart-c6f4f739-55e2-4ee1-a84d-7b97c8e1d8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673754857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1673754857
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.809712728
Short name T266
Test name
Test status
Simulation time 88750576908 ps
CPU time 117.29 seconds
Started Mar 28 12:56:12 PM PDT 24
Finished Mar 28 12:58:10 PM PDT 24
Peak memory 202200 kb
Host smart-0c190c39-7e2e-4c34-8642-a8dff17001d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809712728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st
ress_all.809712728
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.437839300
Short name T785
Test name
Test status
Simulation time 3856326466 ps
CPU time 3.77 seconds
Started Mar 28 12:56:12 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201916 kb
Host smart-d6f157c6-a2a8-4d32-86ce-2f30c68bd4f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437839300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ultra_low_pwr.437839300
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.3916655179
Short name T260
Test name
Test status
Simulation time 2029588492 ps
CPU time 1.98 seconds
Started Mar 28 12:56:31 PM PDT 24
Finished Mar 28 12:56:33 PM PDT 24
Peak memory 202036 kb
Host smart-90350181-a231-4736-95d6-d78415278a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916655179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.3916655179
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.343057961
Short name T41
Test name
Test status
Simulation time 12614064128 ps
CPU time 8.8 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:15 PM PDT 24
Peak memory 202004 kb
Host smart-b095d800-6347-4905-a46f-cb2b02e3b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343057961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.343057961
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.1087994024
Short name T215
Test name
Test status
Simulation time 98619190898 ps
CPU time 256.04 seconds
Started Mar 28 12:56:13 PM PDT 24
Finished Mar 28 01:00:29 PM PDT 24
Peak memory 202120 kb
Host smart-b4353271-bbb1-485f-83eb-1b3baf87064c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087994024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.1087994024
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3841709240
Short name T389
Test name
Test status
Simulation time 85663645390 ps
CPU time 30.37 seconds
Started Mar 28 12:56:25 PM PDT 24
Finished Mar 28 12:56:56 PM PDT 24
Peak memory 202140 kb
Host smart-c1ee9bc8-a070-4226-b34c-5559d19f99a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841709240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.3841709240
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2673835143
Short name T649
Test name
Test status
Simulation time 3233753683 ps
CPU time 9.31 seconds
Started Mar 28 12:56:07 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201944 kb
Host smart-ec8dc6a5-f78d-41a2-b563-61abd5610102
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673835143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.2673835143
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.3809268337
Short name T180
Test name
Test status
Simulation time 2866982698 ps
CPU time 7.38 seconds
Started Mar 28 12:56:25 PM PDT 24
Finished Mar 28 12:56:33 PM PDT 24
Peak memory 201872 kb
Host smart-3bd38e73-0a11-4655-ad9b-5371d4176da1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809268337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.3809268337
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2966249152
Short name T171
Test name
Test status
Simulation time 2613839552 ps
CPU time 7.26 seconds
Started Mar 28 12:56:05 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201700 kb
Host smart-fc683884-780c-4d5d-b479-a2fae390430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966249152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.2966249152
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.4051545473
Short name T717
Test name
Test status
Simulation time 2508199201 ps
CPU time 1.21 seconds
Started Mar 28 12:56:13 PM PDT 24
Finished Mar 28 12:56:14 PM PDT 24
Peak memory 201904 kb
Host smart-9ac2757e-8f3d-49d5-8943-150ec942b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051545473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.4051545473
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3427346648
Short name T417
Test name
Test status
Simulation time 2116065402 ps
CPU time 6.34 seconds
Started Mar 28 12:56:06 PM PDT 24
Finished Mar 28 12:56:12 PM PDT 24
Peak memory 201792 kb
Host smart-ff420fa4-e589-46c6-80fa-29733e151c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427346648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.3427346648
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1833801801
Short name T420
Test name
Test status
Simulation time 2509425981 ps
CPU time 7.84 seconds
Started Mar 28 12:56:11 PM PDT 24
Finished Mar 28 12:56:19 PM PDT 24
Peak memory 201956 kb
Host smart-8151fa27-ad16-4a52-aeb9-525f35e8111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833801801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1833801801
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.4000787531
Short name T411
Test name
Test status
Simulation time 2136081936 ps
CPU time 1.95 seconds
Started Mar 28 12:56:15 PM PDT 24
Finished Mar 28 12:56:17 PM PDT 24
Peak memory 201772 kb
Host smart-52598711-1f0e-4929-8554-9f16a9f9e2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000787531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.4000787531
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.1244685777
Short name T781
Test name
Test status
Simulation time 224472416195 ps
CPU time 25.56 seconds
Started Mar 28 12:56:24 PM PDT 24
Finished Mar 28 12:56:50 PM PDT 24
Peak memory 202028 kb
Host smart-2383dac0-d7ad-4a89-b412-3d0e3f7773fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244685777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.1244685777
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2916818229
Short name T442
Test name
Test status
Simulation time 24954572984 ps
CPU time 67.72 seconds
Started Mar 28 12:56:14 PM PDT 24
Finished Mar 28 12:57:22 PM PDT 24
Peak memory 210424 kb
Host smart-34d5ca06-0eaa-40aa-aca1-3513f2f23ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916818229 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.2916818229
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3204577957
Short name T72
Test name
Test status
Simulation time 149549654238 ps
CPU time 18.36 seconds
Started Mar 28 12:56:01 PM PDT 24
Finished Mar 28 12:56:20 PM PDT 24
Peak memory 201968 kb
Host smart-9c06ace3-9f3b-44bb-a610-65760f1c6a92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204577957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.3204577957
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.3880461030
Short name T596
Test name
Test status
Simulation time 2009444682 ps
CPU time 5.82 seconds
Started Mar 28 12:55:03 PM PDT 24
Finished Mar 28 12:55:10 PM PDT 24
Peak memory 202060 kb
Host smart-d7829c33-2a3c-41c0-af6f-80a85f5299e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880461030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.3880461030
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.3637449802
Short name T114
Test name
Test status
Simulation time 3683668170 ps
CPU time 9.47 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:14 PM PDT 24
Peak memory 201896 kb
Host smart-cfc97efa-6527-4aaa-8d03-1dcde0c9c944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637449802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.3637449802
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.1121503295
Short name T104
Test name
Test status
Simulation time 27613604641 ps
CPU time 37.78 seconds
Started Mar 28 12:55:03 PM PDT 24
Finished Mar 28 12:55:42 PM PDT 24
Peak memory 202192 kb
Host smart-df871029-e38c-4a10-9a92-d1e8c3be7cee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121503295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.1121503295
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2084838823
Short name T429
Test name
Test status
Simulation time 2184930251 ps
CPU time 4.12 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 201956 kb
Host smart-578496f0-e306-465a-ad8f-431a03a3bfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084838823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2084838823
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3796366541
Short name T500
Test name
Test status
Simulation time 2394590701 ps
CPU time 1.54 seconds
Started Mar 28 12:55:03 PM PDT 24
Finished Mar 28 12:55:06 PM PDT 24
Peak memory 201972 kb
Host smart-2f9daaf2-9263-47bc-8139-eeb1e740c788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796366541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3796366541
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1551856734
Short name T469
Test name
Test status
Simulation time 24831293034 ps
CPU time 65.66 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:56:15 PM PDT 24
Peak memory 202172 kb
Host smart-dfe02167-b9ff-4b82-9a3a-1eea6a26706e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551856734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.1551856734
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3433585653
Short name T337
Test name
Test status
Simulation time 3238274210 ps
CPU time 2.11 seconds
Started Mar 28 12:55:07 PM PDT 24
Finished Mar 28 12:55:10 PM PDT 24
Peak memory 201964 kb
Host smart-2d7e17da-6169-4fa6-9958-a522f929d3ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433585653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.3433585653
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2411717114
Short name T150
Test name
Test status
Simulation time 3393347431 ps
CPU time 2.76 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 201812 kb
Host smart-3010e1c0-bea6-4830-a492-c69053b18c95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411717114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.2411717114
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2261052117
Short name T783
Test name
Test status
Simulation time 2635153124 ps
CPU time 2.35 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:09 PM PDT 24
Peak memory 201880 kb
Host smart-04ccf15a-efc0-4691-8c5e-22177708d725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261052117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2261052117
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.397989503
Short name T647
Test name
Test status
Simulation time 2469409222 ps
CPU time 2.21 seconds
Started Mar 28 12:55:00 PM PDT 24
Finished Mar 28 12:55:03 PM PDT 24
Peak memory 201932 kb
Host smart-a0670260-4ee2-4234-a312-f408b12ded6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397989503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.397989503
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.3936237038
Short name T506
Test name
Test status
Simulation time 2181667756 ps
CPU time 2.01 seconds
Started Mar 28 12:55:07 PM PDT 24
Finished Mar 28 12:55:09 PM PDT 24
Peak memory 201952 kb
Host smart-b69b1b35-1dcd-401f-8562-8bf1ff8e18f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936237038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.3936237038
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1318672967
Short name T664
Test name
Test status
Simulation time 2515662687 ps
CPU time 4.21 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 12:55:13 PM PDT 24
Peak memory 201964 kb
Host smart-df6fc22d-f059-47f0-9d35-f753c20d0579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318672967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1318672967
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.2933384331
Short name T201
Test name
Test status
Simulation time 22076290648 ps
CPU time 11.32 seconds
Started Mar 28 12:55:01 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 221836 kb
Host smart-dda28c67-5262-486b-a4e0-e2b3b3aa6604
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933384331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.2933384331
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.435623912
Short name T433
Test name
Test status
Simulation time 2133665980 ps
CPU time 2.14 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:09 PM PDT 24
Peak memory 201804 kb
Host smart-acf10a4a-e723-4873-bc1c-e602e5dae1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435623912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.435623912
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1282745665
Short name T299
Test name
Test status
Simulation time 13876238991 ps
CPU time 34.73 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:41 PM PDT 24
Peak memory 211936 kb
Host smart-8e139b79-1f7d-430e-bc9c-d7e4ac00c7f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282745665 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.1282745665
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1270377388
Short name T54
Test name
Test status
Simulation time 4888317285 ps
CPU time 3.29 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 201928 kb
Host smart-c2793f31-46a4-4912-b0b3-141cac43e5e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270377388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.1270377388
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.2194113098
Short name T517
Test name
Test status
Simulation time 2011584171 ps
CPU time 5.84 seconds
Started Mar 28 12:56:17 PM PDT 24
Finished Mar 28 12:56:23 PM PDT 24
Peak memory 201928 kb
Host smart-2c56311a-dd7c-47d5-9bac-88656647b49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194113098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.2194113098
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3929682235
Short name T593
Test name
Test status
Simulation time 3183561397 ps
CPU time 2.67 seconds
Started Mar 28 12:56:21 PM PDT 24
Finished Mar 28 12:56:23 PM PDT 24
Peak memory 201976 kb
Host smart-1ea5ed6d-ef0a-410d-bb56-dc0178f8cffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929682235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3
929682235
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3778317634
Short name T103
Test name
Test status
Simulation time 76106164053 ps
CPU time 49.21 seconds
Started Mar 28 12:56:18 PM PDT 24
Finished Mar 28 12:57:07 PM PDT 24
Peak memory 202140 kb
Host smart-5bd5cb3f-03aa-481b-9a64-0f9c3a9fc51a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778317634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3778317634
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2868006755
Short name T467
Test name
Test status
Simulation time 3048312101 ps
CPU time 8.31 seconds
Started Mar 28 12:56:20 PM PDT 24
Finished Mar 28 12:56:29 PM PDT 24
Peak memory 201848 kb
Host smart-f7349eab-568a-4a65-b756-193af43bff8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868006755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.2868006755
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2490339748
Short name T116
Test name
Test status
Simulation time 2615933297 ps
CPU time 4.09 seconds
Started Mar 28 12:56:31 PM PDT 24
Finished Mar 28 12:56:36 PM PDT 24
Peak memory 201944 kb
Host smart-2839d649-27c2-4405-bac4-d61d07d722d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490339748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.2490339748
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2651033988
Short name T59
Test name
Test status
Simulation time 2489944136 ps
CPU time 4.15 seconds
Started Mar 28 12:56:15 PM PDT 24
Finished Mar 28 12:56:19 PM PDT 24
Peak memory 201980 kb
Host smart-eb69f83f-e909-4d1e-9a49-109bf4e3666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651033988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.2651033988
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2044426884
Short name T641
Test name
Test status
Simulation time 2218935969 ps
CPU time 3.43 seconds
Started Mar 28 12:56:16 PM PDT 24
Finished Mar 28 12:56:20 PM PDT 24
Peak memory 201912 kb
Host smart-4f67a7d4-c527-40eb-ad40-af03750d20a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044426884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.2044426884
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3573638312
Short name T321
Test name
Test status
Simulation time 2534915279 ps
CPU time 2.28 seconds
Started Mar 28 12:56:16 PM PDT 24
Finished Mar 28 12:56:19 PM PDT 24
Peak memory 201972 kb
Host smart-287279fd-cc45-438f-88f5-766430c8e274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573638312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.3573638312
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.2123318492
Short name T603
Test name
Test status
Simulation time 2121733442 ps
CPU time 3.23 seconds
Started Mar 28 12:56:13 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201848 kb
Host smart-cfe5de18-4991-4032-ada9-3966c3895033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123318492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.2123318492
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.1645156885
Short name T361
Test name
Test status
Simulation time 93751809508 ps
CPU time 128.88 seconds
Started Mar 28 12:56:31 PM PDT 24
Finished Mar 28 12:58:40 PM PDT 24
Peak memory 202212 kb
Host smart-26783727-96c1-4263-b5cb-0e02d619cc84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645156885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.1645156885
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.4091384432
Short name T139
Test name
Test status
Simulation time 46393111636 ps
CPU time 58.68 seconds
Started Mar 28 12:56:14 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 210480 kb
Host smart-322ede1f-a7d0-4b56-afaf-7b08d30d6835
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091384432 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.4091384432
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2380287593
Short name T794
Test name
Test status
Simulation time 6173774271 ps
CPU time 3.48 seconds
Started Mar 28 12:56:13 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201948 kb
Host smart-ef22073d-e630-4c5a-835d-056d6d681612
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380287593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.2380287593
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.3783661195
Short name T475
Test name
Test status
Simulation time 2030254415 ps
CPU time 1.85 seconds
Started Mar 28 12:56:25 PM PDT 24
Finished Mar 28 12:56:27 PM PDT 24
Peak memory 201944 kb
Host smart-e06acbc6-1e58-4943-b1b3-94c1c45caaba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783661195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.3783661195
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3645489930
Short name T516
Test name
Test status
Simulation time 3044007058 ps
CPU time 2.66 seconds
Started Mar 28 12:56:31 PM PDT 24
Finished Mar 28 12:56:34 PM PDT 24
Peak memory 201992 kb
Host smart-2c726ac9-2d56-4c49-a318-1eab312561e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645489930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.3
645489930
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.2744385892
Short name T87
Test name
Test status
Simulation time 134961832482 ps
CPU time 277.25 seconds
Started Mar 28 12:56:25 PM PDT 24
Finished Mar 28 01:01:02 PM PDT 24
Peak memory 202060 kb
Host smart-f4d72d85-aec5-42c5-9dee-e5c40eb955c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744385892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_combo_detect.2744385892
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.504174045
Short name T702
Test name
Test status
Simulation time 4145987400 ps
CPU time 11.01 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:34 PM PDT 24
Peak memory 201844 kb
Host smart-688c8dbf-e179-4ec1-a51a-bbebfe7d6b67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504174045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ec_pwr_on_rst.504174045
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.2712312552
Short name T113
Test name
Test status
Simulation time 4367080382 ps
CPU time 4.54 seconds
Started Mar 28 12:56:21 PM PDT 24
Finished Mar 28 12:56:25 PM PDT 24
Peak memory 201856 kb
Host smart-d2b2d7b5-ee02-4865-9884-377a6cdfa933
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712312552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.2712312552
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3489430167
Short name T643
Test name
Test status
Simulation time 2612513208 ps
CPU time 7.58 seconds
Started Mar 28 12:56:14 PM PDT 24
Finished Mar 28 12:56:22 PM PDT 24
Peak memory 201936 kb
Host smart-0d8cedfa-2f92-4d47-bbca-27d0c90f66d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489430167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.3489430167
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.202914059
Short name T547
Test name
Test status
Simulation time 2466544876 ps
CPU time 7.2 seconds
Started Mar 28 12:56:21 PM PDT 24
Finished Mar 28 12:56:28 PM PDT 24
Peak memory 201828 kb
Host smart-6b98a31b-d379-43da-a894-e059d49e5fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202914059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.202914059
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2256398164
Short name T769
Test name
Test status
Simulation time 2171023827 ps
CPU time 6.27 seconds
Started Mar 28 12:56:31 PM PDT 24
Finished Mar 28 12:56:38 PM PDT 24
Peak memory 201912 kb
Host smart-09fc50f4-5963-447a-a322-5c69289a7635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256398164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2256398164
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2020140525
Short name T509
Test name
Test status
Simulation time 2510310551 ps
CPU time 7.33 seconds
Started Mar 28 12:56:25 PM PDT 24
Finished Mar 28 12:56:33 PM PDT 24
Peak memory 201880 kb
Host smart-5756c7a8-d655-4fcc-8485-9c0f26d66621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020140525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.2020140525
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1206069941
Short name T234
Test name
Test status
Simulation time 2129216520 ps
CPU time 1.77 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:25 PM PDT 24
Peak memory 201892 kb
Host smart-51502751-d9ca-402e-ac32-55ac34805a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206069941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1206069941
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.380648537
Short name T367
Test name
Test status
Simulation time 64562458915 ps
CPU time 77.36 seconds
Started Mar 28 12:56:26 PM PDT 24
Finished Mar 28 12:57:43 PM PDT 24
Peak memory 202192 kb
Host smart-73022f1f-3a08-4479-8bdf-ad4c2a4bafb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380648537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st
ress_all.380648537
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2228588255
Short name T776
Test name
Test status
Simulation time 67026777911 ps
CPU time 166.29 seconds
Started Mar 28 12:56:21 PM PDT 24
Finished Mar 28 12:59:08 PM PDT 24
Peak memory 218532 kb
Host smart-9e7874e8-07de-465b-a1af-9a320ef3eb28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228588255 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2228588255
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.4149212335
Short name T122
Test name
Test status
Simulation time 7274203936 ps
CPU time 2.29 seconds
Started Mar 28 12:56:31 PM PDT 24
Finished Mar 28 12:56:34 PM PDT 24
Peak memory 201936 kb
Host smart-34805c3a-7126-4ba4-b4cf-d7aafd38f679
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149212335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.4149212335
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.2393037018
Short name T510
Test name
Test status
Simulation time 2013741453 ps
CPU time 6.1 seconds
Started Mar 28 12:56:24 PM PDT 24
Finished Mar 28 12:56:30 PM PDT 24
Peak memory 202020 kb
Host smart-b8069178-83f5-4771-aa2d-dfeea9beb240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393037018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.2393037018
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3258242609
Short name T119
Test name
Test status
Simulation time 3098243381 ps
CPU time 8.53 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:31 PM PDT 24
Peak memory 201908 kb
Host smart-926e576d-1a12-4b1b-ac0a-1ffcb7831f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258242609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.3
258242609
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.754277564
Short name T241
Test name
Test status
Simulation time 45185340742 ps
CPU time 32.49 seconds
Started Mar 28 12:56:17 PM PDT 24
Finished Mar 28 12:56:50 PM PDT 24
Peak memory 202080 kb
Host smart-038545a5-4552-4fc3-aa99-172737b4b4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754277564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_wi
th_pre_cond.754277564
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.676210686
Short name T644
Test name
Test status
Simulation time 4109308861 ps
CPU time 1.96 seconds
Started Mar 28 12:56:21 PM PDT 24
Finished Mar 28 12:56:23 PM PDT 24
Peak memory 201800 kb
Host smart-1b378fba-ecb1-4762-ac3e-70585d031970
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676210686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ec_pwr_on_rst.676210686
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.943740472
Short name T169
Test name
Test status
Simulation time 3412034832 ps
CPU time 1.17 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:25 PM PDT 24
Peak memory 201856 kb
Host smart-f99f38a9-4d58-4f39-b85c-1f0c32d5a4c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943740472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctr
l_edge_detect.943740472
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3639373003
Short name T454
Test name
Test status
Simulation time 2610281176 ps
CPU time 7.68 seconds
Started Mar 28 12:56:17 PM PDT 24
Finished Mar 28 12:56:25 PM PDT 24
Peak memory 201848 kb
Host smart-1cbb03a0-ebc2-4fd4-b9f6-02612910ae7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639373003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.3639373003
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.900288922
Short name T606
Test name
Test status
Simulation time 2464236504 ps
CPU time 2.25 seconds
Started Mar 28 12:56:21 PM PDT 24
Finished Mar 28 12:56:23 PM PDT 24
Peak memory 201888 kb
Host smart-5701de9f-286c-4c21-af64-040d177c6ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900288922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.900288922
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1800677636
Short name T489
Test name
Test status
Simulation time 2206902207 ps
CPU time 6.24 seconds
Started Mar 28 12:56:25 PM PDT 24
Finished Mar 28 12:56:32 PM PDT 24
Peak memory 201876 kb
Host smart-213d1f4f-c661-4037-b7dc-55cf9f577663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800677636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1800677636
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.329491755
Short name T645
Test name
Test status
Simulation time 2533058774 ps
CPU time 2.51 seconds
Started Mar 28 12:56:31 PM PDT 24
Finished Mar 28 12:56:34 PM PDT 24
Peak memory 201956 kb
Host smart-46462f69-bc0d-4b30-bddd-bd97031ca70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329491755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.329491755
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.138727406
Short name T616
Test name
Test status
Simulation time 2136543851 ps
CPU time 1.93 seconds
Started Mar 28 12:56:16 PM PDT 24
Finished Mar 28 12:56:18 PM PDT 24
Peak memory 201820 kb
Host smart-fc818a86-de97-448f-aca9-b996e0681aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138727406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.138727406
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.781983543
Short name T106
Test name
Test status
Simulation time 105057165101 ps
CPU time 68.23 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:57:31 PM PDT 24
Peak memory 202016 kb
Host smart-0d3c7cb5-fe94-415d-b2ff-2060df5747e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781983543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_st
ress_all.781983543
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3623749973
Short name T291
Test name
Test status
Simulation time 36063214410 ps
CPU time 78.05 seconds
Started Mar 28 12:56:17 PM PDT 24
Finished Mar 28 12:57:35 PM PDT 24
Peak memory 211720 kb
Host smart-a3bcffab-e8ef-4761-8c7d-a871e7e387f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623749973 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.3623749973
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1677773745
Short name T748
Test name
Test status
Simulation time 5873382766 ps
CPU time 2.27 seconds
Started Mar 28 12:56:20 PM PDT 24
Finished Mar 28 12:56:23 PM PDT 24
Peak memory 201868 kb
Host smart-ef4d468f-2009-48ca-b150-08f7cf353af4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677773745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.1677773745
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.3465593688
Short name T623
Test name
Test status
Simulation time 2032032948 ps
CPU time 2.54 seconds
Started Mar 28 12:56:16 PM PDT 24
Finished Mar 28 12:56:19 PM PDT 24
Peak memory 201900 kb
Host smart-38e96b24-e770-4a14-ab60-6b96867277e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465593688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.3465593688
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1215845667
Short name T601
Test name
Test status
Simulation time 3634115454 ps
CPU time 2.79 seconds
Started Mar 28 12:56:13 PM PDT 24
Finished Mar 28 12:56:16 PM PDT 24
Peak memory 201920 kb
Host smart-200595ec-3d28-4686-a1d9-beede2cd95cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215845667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.1
215845667
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.4204375377
Short name T735
Test name
Test status
Simulation time 119688287869 ps
CPU time 16.71 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:39 PM PDT 24
Peak memory 202156 kb
Host smart-180157b4-235e-43d9-9420-b9f82b02bd18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204375377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.4204375377
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3872442140
Short name T658
Test name
Test status
Simulation time 48520281247 ps
CPU time 35.38 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:58 PM PDT 24
Peak memory 202036 kb
Host smart-6f87e550-bc80-404d-a19c-cbfd4f232ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872442140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.3872442140
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2287132940
Short name T304
Test name
Test status
Simulation time 3818493520 ps
CPU time 5.79 seconds
Started Mar 28 12:56:15 PM PDT 24
Finished Mar 28 12:56:21 PM PDT 24
Peak memory 201944 kb
Host smart-4b2f5cc1-8c51-46ee-8250-3922d15108b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287132940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.2287132940
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.3167061332
Short name T11
Test name
Test status
Simulation time 3232880136 ps
CPU time 3.25 seconds
Started Mar 28 12:56:24 PM PDT 24
Finished Mar 28 12:56:27 PM PDT 24
Peak memory 201620 kb
Host smart-7b71f4e8-be73-43bd-ba6d-6ddcf05bd185
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167061332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.3167061332
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.135196494
Short name T306
Test name
Test status
Simulation time 2638233472 ps
CPU time 1.77 seconds
Started Mar 28 12:56:16 PM PDT 24
Finished Mar 28 12:56:18 PM PDT 24
Peak memory 201860 kb
Host smart-ba7d6df7-7d73-4c03-afbb-c9b835c346aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135196494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.135196494
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.156785436
Short name T598
Test name
Test status
Simulation time 2483253721 ps
CPU time 7.89 seconds
Started Mar 28 12:56:24 PM PDT 24
Finished Mar 28 12:56:32 PM PDT 24
Peak memory 201680 kb
Host smart-f818e096-bb08-4873-8da7-8910303e8265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156785436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.156785436
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1819378454
Short name T483
Test name
Test status
Simulation time 2176507577 ps
CPU time 1.75 seconds
Started Mar 28 12:56:24 PM PDT 24
Finished Mar 28 12:56:26 PM PDT 24
Peak memory 201948 kb
Host smart-8bbc7af6-17ff-4771-9168-8c97f8fef256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819378454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.1819378454
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.914737528
Short name T559
Test name
Test status
Simulation time 2510808601 ps
CPU time 5.76 seconds
Started Mar 28 12:56:24 PM PDT 24
Finished Mar 28 12:56:30 PM PDT 24
Peak memory 201964 kb
Host smart-f5a5dd88-21c9-4e3b-8638-b822afb4408f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914737528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.914737528
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.4139626027
Short name T211
Test name
Test status
Simulation time 2128803397 ps
CPU time 2.36 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:25 PM PDT 24
Peak memory 201892 kb
Host smart-0f59da2f-ccdb-4a3c-a4af-c4df56a8633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139626027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.4139626027
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.792206426
Short name T317
Test name
Test status
Simulation time 13501648708 ps
CPU time 9.08 seconds
Started Mar 28 12:56:16 PM PDT 24
Finished Mar 28 12:56:25 PM PDT 24
Peak memory 201860 kb
Host smart-676b88a4-2350-4ddd-858a-c25053e080e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792206426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_st
ress_all.792206426
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.278364248
Short name T193
Test name
Test status
Simulation time 423559375464 ps
CPU time 147.28 seconds
Started Mar 28 12:56:20 PM PDT 24
Finished Mar 28 12:58:47 PM PDT 24
Peak memory 210480 kb
Host smart-44c91bf5-9b4c-41bb-b936-66f85b670a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278364248 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.278364248
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1470242369
Short name T749
Test name
Test status
Simulation time 3394766040 ps
CPU time 7.19 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:30 PM PDT 24
Peak memory 201968 kb
Host smart-af8f15da-f103-437d-9f84-303d268368c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470242369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.1470242369
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.2876591195
Short name T513
Test name
Test status
Simulation time 2029237972 ps
CPU time 1.93 seconds
Started Mar 28 12:56:19 PM PDT 24
Finished Mar 28 12:56:21 PM PDT 24
Peak memory 201972 kb
Host smart-70690494-5abb-4ae0-9ea4-d18897066d39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876591195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.2876591195
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2058523443
Short name T570
Test name
Test status
Simulation time 3512349310 ps
CPU time 5.18 seconds
Started Mar 28 12:56:15 PM PDT 24
Finished Mar 28 12:56:20 PM PDT 24
Peak memory 202076 kb
Host smart-cdaf954e-1ab0-4cfd-95db-f7170d4d2330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058523443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.2
058523443
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.848866984
Short name T689
Test name
Test status
Simulation time 103952188804 ps
CPU time 99.91 seconds
Started Mar 28 12:56:17 PM PDT 24
Finished Mar 28 12:57:57 PM PDT 24
Peak memory 202120 kb
Host smart-61a38104-015a-4ff0-bbc0-31fb3097bd93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848866984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_combo_detect.848866984
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1719796698
Short name T248
Test name
Test status
Simulation time 3144361502 ps
CPU time 2.77 seconds
Started Mar 28 12:56:17 PM PDT 24
Finished Mar 28 12:56:20 PM PDT 24
Peak memory 201916 kb
Host smart-2f21e661-8613-4885-b247-f683b771eb31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719796698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.1719796698
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3801287398
Short name T772
Test name
Test status
Simulation time 2887366257 ps
CPU time 8.4 seconds
Started Mar 28 12:56:15 PM PDT 24
Finished Mar 28 12:56:24 PM PDT 24
Peak memory 201960 kb
Host smart-d3a47c6d-5f9b-48e8-aea1-fed9348535db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801287398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3801287398
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3566029431
Short name T228
Test name
Test status
Simulation time 2633696923 ps
CPU time 2.37 seconds
Started Mar 28 12:56:23 PM PDT 24
Finished Mar 28 12:56:26 PM PDT 24
Peak memory 201968 kb
Host smart-25cc87e4-010d-49f5-9e69-ea6a35924df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566029431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.3566029431
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1658081352
Short name T334
Test name
Test status
Simulation time 2476976522 ps
CPU time 6.63 seconds
Started Mar 28 12:56:17 PM PDT 24
Finished Mar 28 12:56:23 PM PDT 24
Peak memory 201956 kb
Host smart-c67ad6df-c572-4d09-ad3f-8d92f6b023c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658081352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.1658081352
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2549706312
Short name T459
Test name
Test status
Simulation time 2159261296 ps
CPU time 6.17 seconds
Started Mar 28 12:56:24 PM PDT 24
Finished Mar 28 12:56:30 PM PDT 24
Peak memory 201944 kb
Host smart-b163d1b4-6914-458b-a585-183b5cccfdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549706312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.2549706312
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.89311201
Short name T307
Test name
Test status
Simulation time 2513744312 ps
CPU time 6.91 seconds
Started Mar 28 12:56:15 PM PDT 24
Finished Mar 28 12:56:21 PM PDT 24
Peak memory 201912 kb
Host smart-b7364bda-edb7-4b21-8a27-664c6ad53c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89311201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.89311201
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.4274228267
Short name T665
Test name
Test status
Simulation time 2146062933 ps
CPU time 1.2 seconds
Started Mar 28 12:56:20 PM PDT 24
Finished Mar 28 12:56:21 PM PDT 24
Peak memory 201892 kb
Host smart-5d7c71d2-b063-4eb7-a75a-01ecb46a4936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274228267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.4274228267
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.2778058588
Short name T45
Test name
Test status
Simulation time 14806901545 ps
CPU time 42.46 seconds
Started Mar 28 12:56:19 PM PDT 24
Finished Mar 28 12:57:01 PM PDT 24
Peak memory 202032 kb
Host smart-899c4c2b-110b-4128-9945-2cd75b4b3111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778058588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.2778058588
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.565132551
Short name T538
Test name
Test status
Simulation time 17644796361 ps
CPU time 28.67 seconds
Started Mar 28 12:56:18 PM PDT 24
Finished Mar 28 12:56:47 PM PDT 24
Peak memory 210584 kb
Host smart-46fdbbea-c35b-40a3-8e31-049e32814f66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565132551 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.565132551
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4100908800
Short name T690
Test name
Test status
Simulation time 8544774280 ps
CPU time 6.33 seconds
Started Mar 28 12:56:27 PM PDT 24
Finished Mar 28 12:56:33 PM PDT 24
Peak memory 201896 kb
Host smart-3c53e5d0-3a9f-4c26-835e-68d143bf94f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100908800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.4100908800
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.2624818628
Short name T219
Test name
Test status
Simulation time 2009593277 ps
CPU time 6.04 seconds
Started Mar 28 12:56:46 PM PDT 24
Finished Mar 28 12:56:52 PM PDT 24
Peak memory 202020 kb
Host smart-dce3bf8f-acd8-4d58-9797-bf503c66bb0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624818628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.2624818628
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.754542778
Short name T622
Test name
Test status
Simulation time 3562920487 ps
CPU time 2.76 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:56:42 PM PDT 24
Peak memory 202004 kb
Host smart-b2a6721b-c878-431a-b679-df1424ebd409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754542778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.754542778
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.2457188150
Short name T132
Test name
Test status
Simulation time 103874154077 ps
CPU time 59.72 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:57:39 PM PDT 24
Peak memory 202148 kb
Host smart-a23fec44-8351-4405-8716-215313aa914a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457188150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.2457188150
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3066089292
Short name T251
Test name
Test status
Simulation time 124931720819 ps
CPU time 149.01 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:59:10 PM PDT 24
Peak memory 202152 kb
Host smart-b04f2918-3786-45e4-b55a-b506b01ee68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066089292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.3066089292
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.889203211
Short name T568
Test name
Test status
Simulation time 2674879631 ps
CPU time 4.12 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:56:45 PM PDT 24
Peak memory 201912 kb
Host smart-1c312115-a99a-46be-9a69-6303bd77dae2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889203211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ec_pwr_on_rst.889203211
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3101349655
Short name T133
Test name
Test status
Simulation time 3124675364 ps
CPU time 2.83 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:56:44 PM PDT 24
Peak memory 201916 kb
Host smart-237cce85-2961-4639-917c-0ded8d2aa11f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101349655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.3101349655
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.285589454
Short name T443
Test name
Test status
Simulation time 2617964401 ps
CPU time 4.04 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:56:43 PM PDT 24
Peak memory 201928 kb
Host smart-5ffa5cfa-7662-4def-884d-c8c93d1b3f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285589454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.285589454
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.386852439
Short name T214
Test name
Test status
Simulation time 2449216083 ps
CPU time 4.53 seconds
Started Mar 28 12:56:15 PM PDT 24
Finished Mar 28 12:56:20 PM PDT 24
Peak memory 201928 kb
Host smart-cea436d2-f88e-401f-ac11-91b2a8125638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386852439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.386852439
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3493709334
Short name T511
Test name
Test status
Simulation time 2154555782 ps
CPU time 6.37 seconds
Started Mar 28 12:56:17 PM PDT 24
Finished Mar 28 12:56:24 PM PDT 24
Peak memory 201932 kb
Host smart-5dd37a78-0f04-4b57-a5d4-446f2d8f2be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493709334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.3493709334
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.71688326
Short name T574
Test name
Test status
Simulation time 2526269187 ps
CPU time 2.47 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:56:42 PM PDT 24
Peak memory 201952 kb
Host smart-130387ed-807b-442e-b48d-1e0683630b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71688326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.71688326
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.2884560439
Short name T225
Test name
Test status
Simulation time 2132240241 ps
CPU time 1.91 seconds
Started Mar 28 12:56:20 PM PDT 24
Finished Mar 28 12:56:22 PM PDT 24
Peak memory 201864 kb
Host smart-cbb7ce7f-b660-4ee6-a455-3737c55f4725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884560439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2884560439
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.424123814
Short name T404
Test name
Test status
Simulation time 17297385964 ps
CPU time 8.33 seconds
Started Mar 28 12:56:41 PM PDT 24
Finished Mar 28 12:56:49 PM PDT 24
Peak memory 201940 kb
Host smart-2b26b5fd-0a02-4d0d-a8c7-ded7aa6dfbc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424123814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_st
ress_all.424123814
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.993719265
Short name T293
Test name
Test status
Simulation time 25258778593 ps
CPU time 59.53 seconds
Started Mar 28 12:56:45 PM PDT 24
Finished Mar 28 12:57:45 PM PDT 24
Peak memory 209472 kb
Host smart-2be8ed0c-9ab2-4501-90cc-7ea357abb93c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993719265 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.993719265
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.72864877
Short name T435
Test name
Test status
Simulation time 5252938457 ps
CPU time 1.55 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:56:40 PM PDT 24
Peak memory 202020 kb
Host smart-b84a8420-d50a-4626-953e-a75aabcc0bfc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72864877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_ultra_low_pwr.72864877
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.3003863572
Short name T636
Test name
Test status
Simulation time 2028298737 ps
CPU time 2.23 seconds
Started Mar 28 12:56:42 PM PDT 24
Finished Mar 28 12:56:45 PM PDT 24
Peak memory 201976 kb
Host smart-7948d9ec-9cbb-478b-83bf-cef5d133c2f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003863572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.3003863572
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.272448279
Short name T566
Test name
Test status
Simulation time 97907445434 ps
CPU time 65.24 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:57:46 PM PDT 24
Peak memory 201932 kb
Host smart-d9671b7d-6133-472d-9bc9-946321f411d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272448279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.272448279
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.2650045262
Short name T28
Test name
Test status
Simulation time 121883410088 ps
CPU time 336.26 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 01:02:17 PM PDT 24
Peak memory 202024 kb
Host smart-161c43fe-8c9a-4577-ab7b-179fac536408
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650045262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.2650045262
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.631779347
Short name T98
Test name
Test status
Simulation time 24582019703 ps
CPU time 64.66 seconds
Started Mar 28 12:56:45 PM PDT 24
Finished Mar 28 12:57:50 PM PDT 24
Peak memory 202192 kb
Host smart-c5417d99-c50a-4f45-bbc8-30aa0b6397f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631779347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_wi
th_pre_cond.631779347
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2961748874
Short name T259
Test name
Test status
Simulation time 3131374433 ps
CPU time 8.7 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:56:49 PM PDT 24
Peak memory 201968 kb
Host smart-6dfd4a4b-8bad-4679-a5ff-85c008780174
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961748874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.2961748874
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.4184783910
Short name T721
Test name
Test status
Simulation time 2735022019 ps
CPU time 4.95 seconds
Started Mar 28 12:56:45 PM PDT 24
Finished Mar 28 12:56:50 PM PDT 24
Peak memory 200744 kb
Host smart-6da5b480-3a20-472e-bbbd-d6c3385fa7c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184783910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.4184783910
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.4212936734
Short name T447
Test name
Test status
Simulation time 2649107556 ps
CPU time 1.91 seconds
Started Mar 28 12:56:43 PM PDT 24
Finished Mar 28 12:56:45 PM PDT 24
Peak memory 201928 kb
Host smart-340a6504-a263-4943-b9c9-8a9f95538d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212936734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.4212936734
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3196263216
Short name T556
Test name
Test status
Simulation time 2457902283 ps
CPU time 3.89 seconds
Started Mar 28 12:56:43 PM PDT 24
Finished Mar 28 12:56:47 PM PDT 24
Peak memory 201972 kb
Host smart-292f7083-04ba-4883-a668-a74cc4d8fa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196263216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3196263216
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2076213240
Short name T726
Test name
Test status
Simulation time 2035090064 ps
CPU time 2.02 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:56:42 PM PDT 24
Peak memory 201888 kb
Host smart-cebcc7d7-8126-4734-9d2c-a85154a37b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076213240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2076213240
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3498367021
Short name T720
Test name
Test status
Simulation time 2525101664 ps
CPU time 2.35 seconds
Started Mar 28 12:56:37 PM PDT 24
Finished Mar 28 12:56:40 PM PDT 24
Peak memory 201840 kb
Host smart-357d7b39-ef8d-4df2-8a67-567fb0b3474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498367021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.3498367021
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.878074514
Short name T701
Test name
Test status
Simulation time 2187726793 ps
CPU time 1.15 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:56:40 PM PDT 24
Peak memory 201816 kb
Host smart-87e846b8-3a44-4de7-90af-67ca86e76c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878074514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.878074514
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.1323610797
Short name T67
Test name
Test status
Simulation time 129964421973 ps
CPU time 19.39 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:57:00 PM PDT 24
Peak memory 202144 kb
Host smart-1be4a12a-ecdb-43e6-a252-3c4d22ce1f84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323610797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.1323610797
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3426176801
Short name T128
Test name
Test status
Simulation time 9169680698 ps
CPU time 1.62 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:56:41 PM PDT 24
Peak memory 201948 kb
Host smart-22f654e4-046e-4246-bb9e-435feede0e2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426176801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.3426176801
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.2857218702
Short name T743
Test name
Test status
Simulation time 2071607034 ps
CPU time 1.37 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:56:41 PM PDT 24
Peak memory 202020 kb
Host smart-ea2d7478-8c12-4345-a607-8d3683536c16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857218702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.2857218702
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3288974723
Short name T47
Test name
Test status
Simulation time 3431525916 ps
CPU time 2.66 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:56:42 PM PDT 24
Peak memory 201912 kb
Host smart-a245561d-d830-4ba8-b5d3-4a480f427c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288974723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3
288974723
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.2424475525
Short name T703
Test name
Test status
Simulation time 135582495106 ps
CPU time 57.05 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:57:36 PM PDT 24
Peak memory 202132 kb
Host smart-3c1af74e-e17c-4519-b208-c9a591de7af7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424475525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.2424475525
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.382598572
Short name T377
Test name
Test status
Simulation time 71785886963 ps
CPU time 72.11 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:57:52 PM PDT 24
Peak memory 202088 kb
Host smart-847d2a18-f97d-4aa5-8ee1-20a194c9fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382598572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_wi
th_pre_cond.382598572
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3579918896
Short name T210
Test name
Test status
Simulation time 2931168196 ps
CPU time 2.61 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:56:42 PM PDT 24
Peak memory 201856 kb
Host smart-b75e5c72-c6bc-4153-b729-dd11637e9113
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579918896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.3579918896
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.3995164440
Short name T190
Test name
Test status
Simulation time 2798289086 ps
CPU time 4 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:56:45 PM PDT 24
Peak memory 201876 kb
Host smart-bce9707e-1018-47ce-913d-0df5cc1295af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995164440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.3995164440
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2307428004
Short name T49
Test name
Test status
Simulation time 2629574745 ps
CPU time 2.33 seconds
Started Mar 28 12:56:42 PM PDT 24
Finished Mar 28 12:56:45 PM PDT 24
Peak memory 201956 kb
Host smart-eee476af-49e6-4d73-bf46-049e23b12b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307428004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.2307428004
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2550801596
Short name T787
Test name
Test status
Simulation time 2536427423 ps
CPU time 1.09 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:56:40 PM PDT 24
Peak memory 201956 kb
Host smart-03e9e8b7-0d13-42cc-833c-5248d1ae7067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550801596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2550801596
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3851215724
Short name T262
Test name
Test status
Simulation time 2047072910 ps
CPU time 3.45 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:56:44 PM PDT 24
Peak memory 201848 kb
Host smart-ad5ffe7b-f1bb-41a8-9a73-fbef76025c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851215724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3851215724
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3320779443
Short name T729
Test name
Test status
Simulation time 2522169708 ps
CPU time 3.8 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:56:44 PM PDT 24
Peak memory 201972 kb
Host smart-f067a2c9-6061-47c2-96ef-9427314baf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320779443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.3320779443
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.2303261650
Short name T263
Test name
Test status
Simulation time 2114301340 ps
CPU time 6 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:56:44 PM PDT 24
Peak memory 201776 kb
Host smart-9f90eb52-21af-4849-8f45-07f995c7ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303261650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2303261650
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.4057421449
Short name T587
Test name
Test status
Simulation time 14073717165 ps
CPU time 34.6 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 201828 kb
Host smart-58efe128-6f13-4624-bc43-6f6664f79f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057421449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.4057421449
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1986823143
Short name T277
Test name
Test status
Simulation time 29917664686 ps
CPU time 82.1 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:58:00 PM PDT 24
Peak memory 210512 kb
Host smart-8ce14baa-3bdf-40ca-8b0c-5909cf6b4e21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986823143 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1986823143
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3128056007
Short name T564
Test name
Test status
Simulation time 7264582611 ps
CPU time 5.86 seconds
Started Mar 28 12:56:39 PM PDT 24
Finished Mar 28 12:56:45 PM PDT 24
Peak memory 201940 kb
Host smart-1852f224-5693-46a3-8431-3f835cc6aa3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128056007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.3128056007
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3383551289
Short name T247
Test name
Test status
Simulation time 2010742299 ps
CPU time 5.86 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 202016 kb
Host smart-5a392015-9fef-4b84-a11b-3c6254fbaa86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383551289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3383551289
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1443940204
Short name T553
Test name
Test status
Simulation time 3518160209 ps
CPU time 9.67 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 201872 kb
Host smart-d51024cc-1a4e-4db7-aad3-f459d266f498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443940204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1
443940204
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.3052662685
Short name T398
Test name
Test status
Simulation time 178928364701 ps
CPU time 444.06 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 01:04:34 PM PDT 24
Peak memory 202052 kb
Host smart-1de264f1-a1a2-482f-95bb-88f1d715234f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052662685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.3052662685
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3134819334
Short name T360
Test name
Test status
Simulation time 67489610242 ps
CPU time 179.35 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 01:00:06 PM PDT 24
Peak memory 202028 kb
Host smart-c9118399-5ff1-45f7-8bf9-619953eec9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134819334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.3134819334
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2413622932
Short name T628
Test name
Test status
Simulation time 3039695590 ps
CPU time 8.66 seconds
Started Mar 28 12:56:43 PM PDT 24
Finished Mar 28 12:56:52 PM PDT 24
Peak memory 201912 kb
Host smart-5129d757-16ad-4f2a-b4f5-60c2bc3390e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413622932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.2413622932
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.2507577384
Short name T159
Test name
Test status
Simulation time 5493543764 ps
CPU time 12.67 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:18 PM PDT 24
Peak memory 201892 kb
Host smart-519d44c1-01d9-4a2d-b082-a4103cbde5d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507577384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.2507577384
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3218369252
Short name T308
Test name
Test status
Simulation time 2692741917 ps
CPU time 1.29 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:56:42 PM PDT 24
Peak memory 201908 kb
Host smart-6459492b-7b83-4314-b228-42a0c2a84011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218369252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3218369252
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3667222506
Short name T58
Test name
Test status
Simulation time 2458593176 ps
CPU time 6.86 seconds
Started Mar 28 12:56:36 PM PDT 24
Finished Mar 28 12:56:43 PM PDT 24
Peak memory 201892 kb
Host smart-278dca54-d176-4f35-9448-0b9dc3446289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667222506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3667222506
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.290422671
Short name T738
Test name
Test status
Simulation time 2101269401 ps
CPU time 2.17 seconds
Started Mar 28 12:56:40 PM PDT 24
Finished Mar 28 12:56:43 PM PDT 24
Peak memory 201756 kb
Host smart-b0f9f4f3-ee35-4500-9e4c-49b06fd6d7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290422671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.290422671
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3122900799
Short name T198
Test name
Test status
Simulation time 2519811183 ps
CPU time 4.09 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:56:42 PM PDT 24
Peak memory 201964 kb
Host smart-c4c98108-f13a-4228-b750-f97a742cb141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122900799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3122900799
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3538043383
Short name T13
Test name
Test status
Simulation time 2107988115 ps
CPU time 5.72 seconds
Started Mar 28 12:56:38 PM PDT 24
Finished Mar 28 12:56:44 PM PDT 24
Peak memory 201732 kb
Host smart-bc8d8d2c-dc8e-4a58-9edc-8cde295cb654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538043383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3538043383
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.861927816
Short name T396
Test name
Test status
Simulation time 157128052355 ps
CPU time 72.53 seconds
Started Mar 28 12:57:07 PM PDT 24
Finished Mar 28 12:58:20 PM PDT 24
Peak memory 202260 kb
Host smart-f66ae4ee-0e5b-48fb-9fbd-ae6b7319420c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861927816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_st
ress_all.861927816
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.959140796
Short name T124
Test name
Test status
Simulation time 5332903138 ps
CPU time 2.32 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:11 PM PDT 24
Peak memory 201944 kb
Host smart-bca56237-4ff9-4277-9d8b-4e4ed6ea528a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959140796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_ultra_low_pwr.959140796
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.3815761170
Short name T532
Test name
Test status
Simulation time 2044868085 ps
CPU time 1.98 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:57:08 PM PDT 24
Peak memory 201992 kb
Host smart-5478e01a-da41-4b28-b8a6-b35850fe0e99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815761170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.3815761170
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.885544829
Short name T589
Test name
Test status
Simulation time 6240828168 ps
CPU time 3.85 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 202016 kb
Host smart-644691fe-eb43-451d-959e-0bc7389d578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885544829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.885544829
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1795753194
Short name T270
Test name
Test status
Simulation time 147522277638 ps
CPU time 404.76 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 01:03:52 PM PDT 24
Peak memory 202192 kb
Host smart-0e8b3a31-014c-434f-8dc4-62108c4e797a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795753194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.1795753194
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3555091005
Short name T379
Test name
Test status
Simulation time 51077215555 ps
CPU time 62.56 seconds
Started Mar 28 12:57:04 PM PDT 24
Finished Mar 28 12:58:07 PM PDT 24
Peak memory 202164 kb
Host smart-49023ff7-6daa-43a1-aecb-a9f79c1fbd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555091005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.3555091005
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3196997671
Short name T635
Test name
Test status
Simulation time 3193846774 ps
CPU time 8.61 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 201940 kb
Host smart-1219ab0f-4ec1-4c01-a56e-7fc8de1a2293
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196997671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.3196997671
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.3337260209
Short name T674
Test name
Test status
Simulation time 2850614681 ps
CPU time 7.56 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 201576 kb
Host smart-9f76602e-411b-472c-ba35-1345cccc3169
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337260209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.3337260209
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3272233424
Short name T630
Test name
Test status
Simulation time 2643988443 ps
CPU time 1.78 seconds
Started Mar 28 12:57:04 PM PDT 24
Finished Mar 28 12:57:06 PM PDT 24
Peak memory 201860 kb
Host smart-04e9f3e9-318e-409c-a7de-3ae6612a36e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272233424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.3272233424
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4246769609
Short name T440
Test name
Test status
Simulation time 2490801151 ps
CPU time 2.33 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:07 PM PDT 24
Peak memory 201568 kb
Host smart-4efdcfdd-28dc-434a-97bc-ac2ce5ab28ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246769609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.4246769609
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.12039611
Short name T463
Test name
Test status
Simulation time 2266187113 ps
CPU time 1.63 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:07 PM PDT 24
Peak memory 201944 kb
Host smart-1aa90f0c-5357-4efa-87cd-19abf9d74192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12039611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.12039611
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1805658971
Short name T520
Test name
Test status
Simulation time 2549896948 ps
CPU time 1.92 seconds
Started Mar 28 12:57:04 PM PDT 24
Finished Mar 28 12:57:06 PM PDT 24
Peak memory 201860 kb
Host smart-e8dab76e-09b7-4f7c-9b48-d60b4bb59fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805658971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1805658971
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.3190329995
Short name T529
Test name
Test status
Simulation time 2122060948 ps
CPU time 3.36 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:12 PM PDT 24
Peak memory 201800 kb
Host smart-ee294a54-acfb-4859-a97f-840625108349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190329995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.3190329995
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.2859004070
Short name T445
Test name
Test status
Simulation time 9728153442 ps
CPU time 19.19 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:24 PM PDT 24
Peak memory 202028 kb
Host smart-8df56c6a-6c76-4759-8b74-2792353e9621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859004070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.2859004070
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3044044558
Short name T597
Test name
Test status
Simulation time 8609133229 ps
CPU time 7.17 seconds
Started Mar 28 12:57:07 PM PDT 24
Finished Mar 28 12:57:15 PM PDT 24
Peak memory 201900 kb
Host smart-d042e86f-f2f0-4c9a-897f-0d1d89212396
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044044558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3044044558
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.1260245136
Short name T768
Test name
Test status
Simulation time 2013826087 ps
CPU time 6.11 seconds
Started Mar 28 12:54:57 PM PDT 24
Finished Mar 28 12:55:04 PM PDT 24
Peak memory 202016 kb
Host smart-e2c9cf84-eebd-49c9-a660-5fff3dd5eea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260245136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.1260245136
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.4016314769
Short name T639
Test name
Test status
Simulation time 172867492245 ps
CPU time 439.62 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 01:02:26 PM PDT 24
Peak memory 201968 kb
Host smart-2fd92b7c-2de4-4e58-b119-a4478d3f44d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016314769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.4016314769
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.2465529975
Short name T399
Test name
Test status
Simulation time 142076399667 ps
CPU time 355.73 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 01:01:02 PM PDT 24
Peak memory 202152 kb
Host smart-c35e3105-f777-4c83-a5fa-8b35c562beae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465529975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.2465529975
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1193875196
Short name T409
Test name
Test status
Simulation time 2705620329 ps
CPU time 7.95 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:13 PM PDT 24
Peak memory 201948 kb
Host smart-3efb8fd2-54db-41ca-9bd7-89491d975779
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193875196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.1193875196
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.259547353
Short name T468
Test name
Test status
Simulation time 3330182472 ps
CPU time 9.19 seconds
Started Mar 28 12:54:57 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 201912 kb
Host smart-0fa1c57d-4e2d-455d-bc86-f5e746d9eb4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259547353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl
_edge_detect.259547353
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3860656303
Short name T792
Test name
Test status
Simulation time 2610884183 ps
CPU time 7.89 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:13 PM PDT 24
Peak memory 201940 kb
Host smart-3928a885-68ad-4c49-b29c-bac806007983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860656303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.3860656303
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2722357832
Short name T220
Test name
Test status
Simulation time 2465112801 ps
CPU time 7.56 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:14 PM PDT 24
Peak memory 201964 kb
Host smart-cf3734e0-99e4-4a9a-86b6-688b9bedc157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722357832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.2722357832
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.700477912
Short name T188
Test name
Test status
Simulation time 2220346484 ps
CPU time 3.38 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 201804 kb
Host smart-a278c0bc-b788-4609-8ed8-e81933b58cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700477912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.700477912
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3404576576
Short name T441
Test name
Test status
Simulation time 2510866777 ps
CPU time 6.79 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:16 PM PDT 24
Peak memory 201980 kb
Host smart-d26e863f-5a4e-4bb1-86d3-5c330b56efa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404576576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.3404576576
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.1502827720
Short name T339
Test name
Test status
Simulation time 2109479940 ps
CPU time 6.21 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:16 PM PDT 24
Peak memory 201820 kb
Host smart-9d1c147f-c700-4375-abc1-73fc9a155309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502827720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1502827720
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.3712760974
Short name T316
Test name
Test status
Simulation time 8806652763 ps
CPU time 4.3 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:10 PM PDT 24
Peak memory 201968 kb
Host smart-9d26a74f-cfb1-4205-9278-10d10abfe863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712760974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.3712760974
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2495561685
Short name T144
Test name
Test status
Simulation time 5027550160 ps
CPU time 2.36 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 12:55:11 PM PDT 24
Peak memory 201964 kb
Host smart-173144e3-73b3-415a-abf1-cc17bbbe8196
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495561685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.2495561685
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.484536339
Short name T238
Test name
Test status
Simulation time 24854971081 ps
CPU time 17.44 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 202080 kb
Host smart-dbab5059-acb3-4084-acfa-d55f17a862ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484536339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_wi
th_pre_cond.484536339
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1945451491
Short name T92
Test name
Test status
Simulation time 25862175417 ps
CPU time 15.56 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:25 PM PDT 24
Peak memory 202204 kb
Host smart-3fb7bb5f-8d4b-4b03-b366-d1cb854088a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945451491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.1945451491
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.625331443
Short name T672
Test name
Test status
Simulation time 39705823917 ps
CPU time 37.24 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:43 PM PDT 24
Peak memory 202052 kb
Host smart-fd004fc9-6711-4950-875a-bdae81336eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625331443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_wi
th_pre_cond.625331443
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.190782675
Short name T252
Test name
Test status
Simulation time 37111528432 ps
CPU time 94.87 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:58:40 PM PDT 24
Peak memory 202200 kb
Host smart-01afc319-8f4c-4399-9dfa-78250f18abfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190782675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_wi
th_pre_cond.190782675
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1969431994
Short name T12
Test name
Test status
Simulation time 76177342521 ps
CPU time 52.81 seconds
Started Mar 28 12:57:07 PM PDT 24
Finished Mar 28 12:58:00 PM PDT 24
Peak memory 202068 kb
Host smart-93b1d02c-979a-4e9f-9b28-a4403451d830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969431994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.1969431994
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.4136697635
Short name T405
Test name
Test status
Simulation time 52801031009 ps
CPU time 148.82 seconds
Started Mar 28 12:57:02 PM PDT 24
Finished Mar 28 12:59:31 PM PDT 24
Peak memory 202096 kb
Host smart-4e7d8aa3-9d3e-46e0-9ca3-448e45ad6200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136697635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.4136697635
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2826359065
Short name T380
Test name
Test status
Simulation time 86505760579 ps
CPU time 113.98 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:59:00 PM PDT 24
Peak memory 202044 kb
Host smart-fd7f9050-3073-4d54-88f2-55cf52cd18be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826359065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.2826359065
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2995033636
Short name T707
Test name
Test status
Simulation time 22582889330 ps
CPU time 59.76 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:58:06 PM PDT 24
Peak memory 202232 kb
Host smart-a018ed25-f049-4341-ac60-3d30910865fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995033636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.2995033636
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1318870760
Short name T95
Test name
Test status
Simulation time 24578305758 ps
CPU time 68.43 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:58:14 PM PDT 24
Peak memory 202188 kb
Host smart-7203f015-3e61-40df-b15b-e6e514b2781b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318870760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.1318870760
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.1966447459
Short name T634
Test name
Test status
Simulation time 2036588650 ps
CPU time 1.74 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 202072 kb
Host smart-861d50ee-c7d9-455d-aa77-47842d94bac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966447459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.1966447459
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3704478199
Short name T679
Test name
Test status
Simulation time 3571805390 ps
CPU time 5.32 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 201976 kb
Host smart-83060a05-b098-45a1-ac7b-da904f4e39c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704478199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.3704478199
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.1626315378
Short name T699
Test name
Test status
Simulation time 64739026411 ps
CPU time 14.77 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:21 PM PDT 24
Peak memory 202156 kb
Host smart-40eee8e0-2645-40f3-bfe5-4f256f685f1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626315378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.1626315378
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2030601492
Short name T242
Test name
Test status
Simulation time 3397013107 ps
CPU time 7.41 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:13 PM PDT 24
Peak memory 201960 kb
Host smart-12890151-0832-4df9-9389-a0d654981790
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030601492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.2030601492
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.754761377
Short name T9
Test name
Test status
Simulation time 4191472401 ps
CPU time 9.37 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 12:55:17 PM PDT 24
Peak memory 201964 kb
Host smart-feace750-6105-453f-bc74-421308b6ffff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754761377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl
_edge_detect.754761377
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3112596678
Short name T302
Test name
Test status
Simulation time 2628277334 ps
CPU time 2.2 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 201912 kb
Host smart-66d5d5cb-b819-44e1-b7e8-a9ab5225c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112596678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3112596678
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1543105111
Short name T416
Test name
Test status
Simulation time 2443472800 ps
CPU time 7.21 seconds
Started Mar 28 12:55:03 PM PDT 24
Finished Mar 28 12:55:11 PM PDT 24
Peak memory 201924 kb
Host smart-42b67cd0-c7c2-41ea-8ca7-19d045c4dd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543105111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1543105111
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.877026690
Short name T450
Test name
Test status
Simulation time 2181625895 ps
CPU time 3.46 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 201992 kb
Host smart-f8cf720a-7dd0-48df-8fc3-c4f8534eac9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877026690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.877026690
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.827866100
Short name T322
Test name
Test status
Simulation time 2608231123 ps
CPU time 1.29 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:06 PM PDT 24
Peak memory 201984 kb
Host smart-17faf883-5ddd-43d7-8f82-c2b6860108c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827866100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.827866100
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.3780112493
Short name T777
Test name
Test status
Simulation time 2108056719 ps
CPU time 5.84 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:15 PM PDT 24
Peak memory 201716 kb
Host smart-f844ed67-7122-40af-a4b8-89fe0d945494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780112493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3780112493
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.3559098435
Short name T535
Test name
Test status
Simulation time 15680514371 ps
CPU time 40.76 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:47 PM PDT 24
Peak memory 201960 kb
Host smart-bf719f3d-889e-4f71-848e-20090d20fadd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559098435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.3559098435
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.794293600
Short name T290
Test name
Test status
Simulation time 21170810142 ps
CPU time 55.14 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:56:04 PM PDT 24
Peak memory 212712 kb
Host smart-8e9fa242-6ddb-4cc2-9755-2af8f6599c41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794293600 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.794293600
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1180530588
Short name T407
Test name
Test status
Simulation time 545292341129 ps
CPU time 154.6 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:57:39 PM PDT 24
Peak memory 201956 kb
Host smart-8eb9d9c9-22a7-46fb-b3a1-0a0f6df483b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180530588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.1180530588
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1637967024
Short name T244
Test name
Test status
Simulation time 29353797437 ps
CPU time 18.57 seconds
Started Mar 28 12:57:07 PM PDT 24
Finished Mar 28 12:57:26 PM PDT 24
Peak memory 202220 kb
Host smart-00deeac1-92cb-4e3b-b92b-1e6d0e36ffa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637967024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.1637967024
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.4017034921
Short name T70
Test name
Test status
Simulation time 33836860595 ps
CPU time 25.97 seconds
Started Mar 28 12:57:07 PM PDT 24
Finished Mar 28 12:57:33 PM PDT 24
Peak memory 202128 kb
Host smart-0fa88d8b-0cce-4210-9029-20ba05db4940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017034921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.4017034921
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3912648010
Short name T384
Test name
Test status
Simulation time 93225594310 ps
CPU time 41.59 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:51 PM PDT 24
Peak memory 202204 kb
Host smart-d519b5ac-3b47-44a0-928b-4b523ec16d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912648010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.3912648010
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.439400752
Short name T130
Test name
Test status
Simulation time 191882093990 ps
CPU time 44.13 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:57:51 PM PDT 24
Peak memory 202196 kb
Host smart-ff742cbb-f0bc-4908-846a-0896a36f47da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439400752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_wi
th_pre_cond.439400752
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2654373933
Short name T460
Test name
Test status
Simulation time 26332581865 ps
CPU time 74.53 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:58:20 PM PDT 24
Peak memory 202092 kb
Host smart-d7caa478-3738-4021-bc60-93a46e8c4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654373933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.2654373933
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3490056649
Short name T97
Test name
Test status
Simulation time 27368987508 ps
CPU time 14.17 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 202120 kb
Host smart-091d8881-91a8-4cf8-a8fb-647699440130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490056649 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.3490056649
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.3604309685
Short name T245
Test name
Test status
Simulation time 2011271045 ps
CPU time 6.03 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:13 PM PDT 24
Peak memory 202020 kb
Host smart-d3de85a1-b36a-46c8-8dea-ffeb5c33a19a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604309685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.3604309685
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1004952196
Short name T474
Test name
Test status
Simulation time 3595268359 ps
CPU time 10.11 seconds
Started Mar 28 12:55:07 PM PDT 24
Finished Mar 28 12:55:17 PM PDT 24
Peak memory 202032 kb
Host smart-024ba5f4-a8b1-4ece-8a3f-773ebd4f55a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004952196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.1004952196
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1107874862
Short name T660
Test name
Test status
Simulation time 3459630000 ps
CPU time 9.17 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:14 PM PDT 24
Peak memory 202004 kb
Host smart-ec5aba9b-eef5-44de-a664-be2ec657969e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107874862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.1107874862
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.3137274561
Short name T36
Test name
Test status
Simulation time 3612376887 ps
CPU time 1.33 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:06 PM PDT 24
Peak memory 202012 kb
Host smart-7f20191e-5049-40ac-b678-1a86d8cb0a7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137274561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.3137274561
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.915946313
Short name T572
Test name
Test status
Simulation time 2618670018 ps
CPU time 3.85 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:13 PM PDT 24
Peak memory 201892 kb
Host smart-581b710b-b205-4d66-bb67-39d26ebca1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915946313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.915946313
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.239416839
Short name T60
Test name
Test status
Simulation time 2463229372 ps
CPU time 3.69 seconds
Started Mar 28 12:55:07 PM PDT 24
Finished Mar 28 12:55:11 PM PDT 24
Peak memory 201964 kb
Host smart-bb43f661-b17c-4583-a4eb-26cd39fdce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239416839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.239416839
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.219771126
Short name T486
Test name
Test status
Simulation time 2220691388 ps
CPU time 6.43 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:16 PM PDT 24
Peak memory 201936 kb
Host smart-be7d178c-87a7-4209-b19c-acd8ca682501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219771126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.219771126
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.454689269
Short name T549
Test name
Test status
Simulation time 2537128953 ps
CPU time 2.49 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:09 PM PDT 24
Peak memory 201864 kb
Host smart-3c797d99-30ea-43f3-bf15-3f2f1816ea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454689269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.454689269
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.1639424205
Short name T692
Test name
Test status
Simulation time 2125155512 ps
CPU time 1.66 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 201840 kb
Host smart-b34c38b5-ae63-4122-8912-89427ea78cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639424205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1639424205
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.3685296657
Short name T364
Test name
Test status
Simulation time 640493475775 ps
CPU time 194.46 seconds
Started Mar 28 12:55:04 PM PDT 24
Finished Mar 28 12:58:19 PM PDT 24
Peak memory 202188 kb
Host smart-e1aa1ae2-480e-4126-857e-6e5d76873061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685296657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.3685296657
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.140192423
Short name T134
Test name
Test status
Simulation time 73646315068 ps
CPU time 195.52 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 01:00:21 PM PDT 24
Peak memory 202168 kb
Host smart-b09878f3-13ca-49a6-b597-222c0e5830bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140192423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_wi
th_pre_cond.140192423
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1014073617
Short name T111
Test name
Test status
Simulation time 68699038801 ps
CPU time 42.58 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:57:50 PM PDT 24
Peak memory 202032 kb
Host smart-1a83eeb7-084d-4692-a4ec-796816c3ca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014073617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.1014073617
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.796205765
Short name T382
Test name
Test status
Simulation time 88021036860 ps
CPU time 61.13 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:58:08 PM PDT 24
Peak memory 202096 kb
Host smart-41719360-1730-4bce-af0f-8e7feeeb4211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796205765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_wi
th_pre_cond.796205765
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3089128701
Short name T462
Test name
Test status
Simulation time 26838214881 ps
CPU time 37.23 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:47 PM PDT 24
Peak memory 202108 kb
Host smart-df2bd04a-4ca8-4cfa-9525-410ad5f991e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089128701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.3089128701
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.275611610
Short name T237
Test name
Test status
Simulation time 102387130615 ps
CPU time 55.36 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:58:01 PM PDT 24
Peak memory 201884 kb
Host smart-d8d13cf2-d006-4d64-9a1a-48ef2a60c9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275611610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_wi
th_pre_cond.275611610
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3570162891
Short name T704
Test name
Test status
Simulation time 27121955947 ps
CPU time 11.1 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:17 PM PDT 24
Peak memory 202060 kb
Host smart-45c838f4-6d85-45ea-be78-5c0b0f0b9659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570162891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.3570162891
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1672710937
Short name T610
Test name
Test status
Simulation time 73025668773 ps
CPU time 46.3 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:57:52 PM PDT 24
Peak memory 202140 kb
Host smart-8b2f75dc-81d6-4e31-adb3-6e9a300d603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672710937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.1672710937
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.532840458
Short name T466
Test name
Test status
Simulation time 2011704179 ps
CPU time 5.78 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:15 PM PDT 24
Peak memory 201996 kb
Host smart-2db42221-87c6-427d-9653-844ad5abe397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532840458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test
.532840458
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.802490684
Short name T39
Test name
Test status
Simulation time 3548739042 ps
CPU time 10.27 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:55:28 PM PDT 24
Peak memory 201928 kb
Host smart-e551312d-e4b9-4634-897a-6c0c0ccf51d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802490684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.802490684
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.674575292
Short name T240
Test name
Test status
Simulation time 53054181360 ps
CPU time 36.06 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 12:55:45 PM PDT 24
Peak memory 202100 kb
Host smart-2f2d76f1-e36f-4f04-8e22-3ebce3f0e707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674575292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wit
h_pre_cond.674575292
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1775229144
Short name T221
Test name
Test status
Simulation time 2565585654 ps
CPU time 2.28 seconds
Started Mar 28 12:55:07 PM PDT 24
Finished Mar 28 12:55:09 PM PDT 24
Peak memory 201876 kb
Host smart-623ee00c-5a4e-4ca9-8bc7-3c1612b06480
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775229144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.1775229144
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.952157462
Short name T558
Test name
Test status
Simulation time 2995334660 ps
CPU time 8.3 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:15 PM PDT 24
Peak memory 201896 kb
Host smart-fce04ba8-47de-4fea-8111-8e45e8350625
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952157462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl
_edge_detect.952157462
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2467592942
Short name T439
Test name
Test status
Simulation time 2626899064 ps
CPU time 2.43 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:09 PM PDT 24
Peak memory 201908 kb
Host smart-a8368e35-03a4-4bff-91cf-00189fe6e886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467592942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.2467592942
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1660657709
Short name T152
Test name
Test status
Simulation time 2473020539 ps
CPU time 2.29 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 12:55:11 PM PDT 24
Peak memory 201848 kb
Host smart-4ba8810c-66a4-4dd8-aa81-40adf57b1989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660657709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1660657709
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1476001625
Short name T491
Test name
Test status
Simulation time 2179290104 ps
CPU time 1.43 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:06 PM PDT 24
Peak memory 201948 kb
Host smart-5c37208e-98c5-4c7c-9f61-13d535cfcdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476001625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.1476001625
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3096953294
Short name T335
Test name
Test status
Simulation time 2531796249 ps
CPU time 2.31 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:07 PM PDT 24
Peak memory 201916 kb
Host smart-492cf6f7-7fe4-47ca-af07-9a22121aa47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096953294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.3096953294
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.2208616247
Short name T657
Test name
Test status
Simulation time 2117281831 ps
CPU time 3.11 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 201788 kb
Host smart-600abc8f-fda7-4ec3-b03a-2b56b835c7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208616247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.2208616247
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.3472931769
Short name T149
Test name
Test status
Simulation time 8615313871 ps
CPU time 10.8 seconds
Started Mar 28 12:55:14 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201888 kb
Host smart-24314385-db09-4cb0-904f-8cecf96a9d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472931769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.3472931769
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.122689876
Short name T192
Test name
Test status
Simulation time 22374806899 ps
CPU time 58.41 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:56:23 PM PDT 24
Peak memory 211488 kb
Host smart-c5b78caa-c1bb-4b8d-8f7d-b61d37e8423d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122689876 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.122689876
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1838599483
Short name T325
Test name
Test status
Simulation time 6619472899 ps
CPU time 2.18 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 201868 kb
Host smart-352c18b4-0c6b-445d-b1e2-e13740a86ae5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838599483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.1838599483
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.444147407
Short name T723
Test name
Test status
Simulation time 66397324829 ps
CPU time 52.25 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:58:02 PM PDT 24
Peak memory 202188 kb
Host smart-72bf0800-2a16-400c-9939-7a2ef2a1630d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444147407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_wi
th_pre_cond.444147407
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.3081807866
Short name T691
Test name
Test status
Simulation time 40228665579 ps
CPU time 106.75 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:58:52 PM PDT 24
Peak memory 202220 kb
Host smart-2f30522f-e367-4e20-868a-ff3399d764e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081807866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_w
ith_pre_cond.3081807866
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3431894275
Short name T387
Test name
Test status
Simulation time 60263715823 ps
CPU time 164.71 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:59:54 PM PDT 24
Peak memory 202176 kb
Host smart-2e377051-49bb-4f62-b564-ab771d93479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431894275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.3431894275
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2777284079
Short name T391
Test name
Test status
Simulation time 51436385955 ps
CPU time 130.62 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:59:16 PM PDT 24
Peak memory 202180 kb
Host smart-bb5653fd-eff3-43d4-8cb2-3ec371b6f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777284079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.2777284079
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1258558602
Short name T682
Test name
Test status
Simulation time 53440802999 ps
CPU time 68.22 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:58:19 PM PDT 24
Peak memory 202088 kb
Host smart-ae393db7-e4e4-41a4-ac15-a1bdb8ef2b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258558602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.1258558602
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2792174237
Short name T243
Test name
Test status
Simulation time 32476363298 ps
CPU time 79.01 seconds
Started Mar 28 12:57:04 PM PDT 24
Finished Mar 28 12:58:23 PM PDT 24
Peak memory 202200 kb
Host smart-642c6b65-d2fa-484a-8d5a-88c2281df900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792174237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.2792174237
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.331185960
Short name T390
Test name
Test status
Simulation time 79346428378 ps
CPU time 200.71 seconds
Started Mar 28 12:57:07 PM PDT 24
Finished Mar 28 01:00:28 PM PDT 24
Peak memory 202108 kb
Host smart-0559c618-b557-4aa1-bc46-81fff785f545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331185960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_wi
th_pre_cond.331185960
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2594234409
Short name T402
Test name
Test status
Simulation time 33811372243 ps
CPU time 94.73 seconds
Started Mar 28 12:57:05 PM PDT 24
Finished Mar 28 12:58:40 PM PDT 24
Peak memory 202208 kb
Host smart-75e58be5-dd06-403b-a04d-75113ed9c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594234409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.2594234409
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.2295110801
Short name T331
Test name
Test status
Simulation time 2022842872 ps
CPU time 1.95 seconds
Started Mar 28 12:55:10 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 201996 kb
Host smart-86789c0f-7757-490f-af7a-d42988514bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295110801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.2295110801
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.391637699
Short name T232
Test name
Test status
Simulation time 3373640416 ps
CPU time 9.13 seconds
Started Mar 28 12:55:01 PM PDT 24
Finished Mar 28 12:55:11 PM PDT 24
Peak memory 202040 kb
Host smart-5fa701cd-2348-4702-9c34-2701275ab5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391637699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.391637699
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.2005396817
Short name T268
Test name
Test status
Simulation time 22945123649 ps
CPU time 33 seconds
Started Mar 28 12:55:08 PM PDT 24
Finished Mar 28 12:55:41 PM PDT 24
Peak memory 202040 kb
Host smart-9fb631e9-26c4-4426-a9e4-d17a0f52c45e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005396817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.2005396817
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1837051026
Short name T485
Test name
Test status
Simulation time 59736096743 ps
CPU time 141.27 seconds
Started Mar 28 12:55:02 PM PDT 24
Finished Mar 28 12:57:23 PM PDT 24
Peak memory 202184 kb
Host smart-3b7eff23-806d-4232-ab7c-ea9b75adcd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837051026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.1837051026
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.138354002
Short name T422
Test name
Test status
Simulation time 3726182961 ps
CPU time 3.03 seconds
Started Mar 28 12:55:05 PM PDT 24
Finished Mar 28 12:55:08 PM PDT 24
Peak memory 201932 kb
Host smart-03b02fed-b3f1-4f4a-b501-e6695bf52001
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138354002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ec_pwr_on_rst.138354002
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.2655965992
Short name T203
Test name
Test status
Simulation time 4133482585 ps
CPU time 2.77 seconds
Started Mar 28 12:55:10 PM PDT 24
Finished Mar 28 12:55:13 PM PDT 24
Peak memory 201948 kb
Host smart-093ed8d4-4a69-4467-95b2-2ec94d72cded
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655965992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.2655965992
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1467514010
Short name T696
Test name
Test status
Simulation time 2625191496 ps
CPU time 2.46 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:11 PM PDT 24
Peak memory 201924 kb
Host smart-a3249bd9-c866-4d17-9260-5e2f9e954d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467514010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.1467514010
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3875144298
Short name T212
Test name
Test status
Simulation time 2483098405 ps
CPU time 2.45 seconds
Started Mar 28 12:55:03 PM PDT 24
Finished Mar 28 12:55:06 PM PDT 24
Peak memory 201828 kb
Host smart-0cafb3b8-928b-4074-9c11-1368c2e55660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875144298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3875144298
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3677112514
Short name T498
Test name
Test status
Simulation time 2151034017 ps
CPU time 2.03 seconds
Started Mar 28 12:55:03 PM PDT 24
Finished Mar 28 12:55:06 PM PDT 24
Peak memory 201808 kb
Host smart-8a1bfe43-4e61-48c4-86e6-db785884083f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677112514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.3677112514
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3836683102
Short name T590
Test name
Test status
Simulation time 2531775344 ps
CPU time 2.28 seconds
Started Mar 28 12:55:17 PM PDT 24
Finished Mar 28 12:55:19 PM PDT 24
Peak memory 201940 kb
Host smart-5184e6d3-45ae-4162-a441-1bd85821f335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836683102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3836683102
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.2164322758
Short name T478
Test name
Test status
Simulation time 2115149531 ps
CPU time 3.37 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:55:25 PM PDT 24
Peak memory 201736 kb
Host smart-0caa74ad-1540-4925-9eca-257d388a2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164322758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.2164322758
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.32412320
Short name T362
Test name
Test status
Simulation time 45878743593 ps
CPU time 112.35 seconds
Started Mar 28 12:55:06 PM PDT 24
Finished Mar 28 12:56:58 PM PDT 24
Peak memory 202136 kb
Host smart-3da480c2-eacb-45b7-af8d-7852b5957664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32412320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stre
ss_all.32412320
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3174335634
Short name T223
Test name
Test status
Simulation time 354415947754 ps
CPU time 234.83 seconds
Started Mar 28 12:55:10 PM PDT 24
Finished Mar 28 12:59:05 PM PDT 24
Peak memory 215416 kb
Host smart-f46acb5d-d832-414e-ac76-bf99486035a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174335634 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.3174335634
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1168507741
Short name T613
Test name
Test status
Simulation time 5544264937 ps
CPU time 2.45 seconds
Started Mar 28 12:55:09 PM PDT 24
Finished Mar 28 12:55:12 PM PDT 24
Peak memory 201944 kb
Host smart-fa86c039-a211-4add-b851-d63f02ae7fe8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168507741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.1168507741
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3374036485
Short name T490
Test name
Test status
Simulation time 55929424482 ps
CPU time 37.41 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:47 PM PDT 24
Peak memory 202132 kb
Host smart-ebd4fbb8-dd3c-4478-8bef-f4a894ea89c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374036485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.3374036485
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.813670269
Short name T388
Test name
Test status
Simulation time 122525965305 ps
CPU time 314.02 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 01:02:20 PM PDT 24
Peak memory 202152 kb
Host smart-856a0386-1a24-4572-b532-95e2d6f0f8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813670269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_wi
th_pre_cond.813670269
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.92328450
Short name T557
Test name
Test status
Simulation time 73928560909 ps
CPU time 110.29 seconds
Started Mar 28 12:57:06 PM PDT 24
Finished Mar 28 12:58:57 PM PDT 24
Peak memory 202136 kb
Host smart-0956e5f4-e764-4cdf-b971-a2892880d5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92328450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_wit
h_pre_cond.92328450
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2867972135
Short name T395
Test name
Test status
Simulation time 140886540032 ps
CPU time 365.68 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 01:03:15 PM PDT 24
Peak memory 202140 kb
Host smart-4364150a-9703-4dbf-8093-638169c57c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867972135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.2867972135
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1112444550
Short name T763
Test name
Test status
Simulation time 99495294968 ps
CPU time 67.48 seconds
Started Mar 28 12:57:10 PM PDT 24
Finished Mar 28 12:58:18 PM PDT 24
Peak memory 202012 kb
Host smart-9e52b860-4feb-49ac-987a-e0791b5ddfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112444550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.1112444550
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2124880953
Short name T44
Test name
Test status
Simulation time 23855008801 ps
CPU time 13.37 seconds
Started Mar 28 12:57:08 PM PDT 24
Finished Mar 28 12:57:22 PM PDT 24
Peak memory 202232 kb
Host smart-c3020ecd-ad5d-42f4-944f-3952ea78dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124880953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.2124880953
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3936702653
Short name T458
Test name
Test status
Simulation time 25358959702 ps
CPU time 16.81 seconds
Started Mar 28 12:57:09 PM PDT 24
Finished Mar 28 12:57:26 PM PDT 24
Peak memory 202144 kb
Host smart-c18965e8-b6f7-40bd-bb0d-0d7b8f9b2172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936702653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.3936702653
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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