Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T5,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T4,T5,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T5,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T5,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T26
0	1	Covered	T72,T93,T96
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T26
0	1	Covered	T4,T5,T26
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T5,T26
1	-	Covered	T4,T5,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T5,T26
DetectSt	168	Covered	T4,T5,T26
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T4,T5,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T5,T26
DebounceSt->IdleSt	163	Covered	T4,T26,T48
DetectSt->IdleSt	186	Covered	T72,T93,T96
DetectSt->StableSt	191	Covered	T4,T5,T26
IdleSt->DebounceSt	148	Covered	T4,T5,T26
StableSt->IdleSt	206	Covered	T4,T5,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T5,T26
0	1	Covered	T4,T5,T26
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T26
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T5,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T5,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T26,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T5,T26
DetectSt	-	-	-	-	1	-	-	Covered	T72,T93,T96
DetectSt	-	-	-	-	0	1	-	Covered	T4,T5,T26
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T4,T5,T26
StableSt	-	-	-	-	-	-	0	Covered	T4,T5,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	314	0	0
CntIncr_A	7891491	51392	0	0
CntNoWrap_A	7891491	7231072	0	0
DetectStDropOut_A	7891491	4	0	0
DetectedOut_A	7891491	997	0	0
DetectedPulseOut_A	7891491	140	0	0
DisabledIdleSt_A	7891491	7172708	0	0
DisabledNoDetection_A	7891491	7175053	0	0
EnterDebounceSt_A	7891491	176	0	0
EnterDetectSt_A	7891491	144	0	0
EnterStableSt_A	7891491	140	0	0
PulseIsPulse_A	7891491	140	0	0
StayInStableSt	7891491	857	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7891491	6892	0	0
gen_low_level_sva.LowLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	140	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	314	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	3	0	0
T5	11957	2	0	0
T8	0	6	0	0
T12	0	3	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	2	0	0
T26	0	3	0	0
T48	0	5	0	0
T49	0	2	0	0
T52	0	7	0	0
T84	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	51392	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	4796	0	0
T5	11957	68	0	0
T8	0	153	0	0
T12	0	121	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	68	0	0
T26	0	162	0	0
T48	0	56	0	0
T49	0	22	0	0
T52	0	314	0	0
T84	0	129	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231072	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4930	0	0
T5	11957	11554	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	4	0	0
T72	72847	1	0	0
T93	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T108	748	0	0	0
T109	658	0	0	0
T110	711	0	0	0
T111	997	0	0	0
T112	4413	0	0	0
T113	441	0	0	0
T114	428	0	0	0
T115	406	0	0	0
T116	958	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	997	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	6	0	0
T5	11957	6	0	0
T8	0	21	0	0
T12	0	9	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	10	0	0
T26	0	4	0	0
T48	0	13	0	0
T49	0	4	0	0
T52	0	19	0	0
T84	0	19	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	140	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	1	0	0
T5	11957	1	0	0
T8	0	3	0	0
T12	0	1	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	3	0	0
T84	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7172708	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	52	0	0
T5	11957	11437	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7175053	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	53	0	0
T5	11957	11438	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	176	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	2	0	0
T5	11957	1	0	0
T8	0	3	0	0
T12	0	2	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T48	0	3	0	0
T49	0	1	0	0
T52	0	5	0	0
T84	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	144	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	1	0	0
T5	11957	1	0	0
T8	0	3	0	0
T12	0	1	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	3	0	0
T84	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	140	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	1	0	0
T5	11957	1	0	0
T8	0	3	0	0
T12	0	1	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	3	0	0
T84	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	140	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	1	0	0
T5	11957	1	0	0
T8	0	3	0	0
T12	0	1	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	3	0	0
T84	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	857	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	5	0	0
T5	11957	5	0	0
T8	0	18	0	0
T12	0	8	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	9	0	0
T26	0	3	0	0
T48	0	11	0	0
T49	0	3	0	0
T52	0	16	0	0
T84	0	17	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6892	0	0
T1	16990	27	0	0
T2	837	4	0	0
T3	11228	31	0	0
T4	5334	3	0	0
T5	11957	3	0	0
T6	0	28	0	0
T13	493	6	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	1	0	0
T22	0	6	0	0
T23	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	140	0	0
T1	16990	0	0	0
T2	837	0	0	0
T3	11228	0	0	0
T4	5334	1	0	0
T5	11957	1	0	0
T8	0	3	0	0
T12	0	1	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	3	0	0
T84	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T2,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T8,T37,T68
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Unreachable
1	0	Covered	T2,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T8
DetectSt	168	Covered	T2,T6,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T8
DebounceSt->IdleSt	163	Covered	T8,T60,T68
DetectSt->IdleSt	186	Covered	T8,T37,T68
DetectSt->StableSt	191	Covered	T2,T6,T8
IdleSt->DebounceSt	148	Covered	T2,T6,T8
StableSt->IdleSt	206	Covered	T2,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T60,T68
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T37,T68
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	206	0	0
CntIncr_A	7891491	87371	0	0
CntNoWrap_A	7891491	7231180	0	0
DetectStDropOut_A	7891491	29	0	0
DetectedOut_A	7891491	362128	0	0
DetectedPulseOut_A	7891491	50	0	0
DisabledIdleSt_A	7891491	5130426	0	0
DisabledNoDetection_A	7891491	5132821	0	0
EnterDebounceSt_A	7891491	128	0	0
EnterDetectSt_A	7891491	79	0	0
EnterStableSt_A	7891491	50	0	0
PulseIsPulse_A	7891491	50	0	0
StayInStableSt	7891491	362078	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7891491	6892	0	0
gen_low_level_sva.LowLevelEvent_A	7891491	7233785	0	0
gen_sticky_sva.StableStDropOut_A	7891491	1101523	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	206	0	0
T2	837	4	0	0
T3	11228	0	0	0
T6	28425	2	0	0
T8	0	14	0	0
T11	0	2	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	2	0	0
T60	0	1	0	0
T61	429	0	0	0
T67	0	4	0	0
T68	0	6	0	0
T69	0	2	0	0
T70	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	87371	0	0
T2	837	92	0	0
T3	11228	0	0	0
T6	28425	63	0	0
T8	0	184	0	0
T11	0	81	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	43	0	0
T60	0	88	0	0
T61	429	0	0	0
T67	0	106	0	0
T68	0	380	0	0
T69	0	65	0	0
T70	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231180	0	0
T1	16990	16578	0	0
T2	837	432	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	29	0	0
T8	39472	4	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T37	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T68	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T118	0	1	0	0
T119	0	2	0	0
T120	0	3	0	0
T121	0	1	0	0
T122	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	362128	0	0
T2	837	63	0	0
T3	11228	0	0	0
T6	28425	355	0	0
T8	0	1	0	0
T11	0	27	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T61	429	0	0	0
T67	0	359	0	0
T68	0	1	0	0
T70	0	18	0	0
T118	0	36	0	0
T119	0	56	0	0
T120	0	94	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	1	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T70	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	5130426	0	0
T1	16990	16578	0	0
T2	837	137	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	5132821	0	0
T1	16990	16582	0	0
T2	837	138	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	128	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	9	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T60	0	1	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	4	0	0
T69	0	2	0	0
T70	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	79	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	5	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	2	0	0
T70	0	1	0	0
T118	0	2	0	0
T119	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	1	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T70	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	1	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T70	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	362078	0	0
T2	837	61	0	0
T3	11228	0	0	0
T6	28425	354	0	0
T11	0	26	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T61	429	0	0	0
T67	0	357	0	0
T70	0	17	0	0
T77	0	139	0	0
T118	0	35	0	0
T119	0	55	0	0
T120	0	92	0	0
T123	0	47	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6892	0	0
T1	16990	27	0	0
T2	837	4	0	0
T3	11228	31	0	0
T4	5334	3	0	0
T5	11957	3	0	0
T6	0	28	0	0
T13	493	6	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	1	0	0
T22	0	6	0	0
T23	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1101523	0	0
T2	837	126	0	0
T3	11228	0	0	0
T6	28425	375	0	0
T8	0	143	0	0
T11	0	49	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T61	429	0	0	0
T67	0	418	0	0
T68	0	62	0	0
T70	0	64	0	0
T118	0	319	0	0
T119	0	125	0	0
T120	0	496	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T2,T17

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T13,T2,T17
1	1	Covered	T13,T2,T17

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T13,T2,T17
1	1	Covered	T2,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T77,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Unreachable
1	0	Covered	T2,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T8
DetectSt	168	Covered	T2,T6,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T8
DebounceSt->IdleSt	163	Covered	T8,T60,T69
DetectSt->IdleSt	186	Covered	T77,T82,T83
DetectSt->StableSt	191	Covered	T2,T6,T8
IdleSt->DebounceSt	148	Covered	T2,T6,T8
StableSt->IdleSt	206	Covered	T2,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T13,T2,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T60,T116
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T77,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	181	0	0
CntIncr_A	7891491	189284	0	0
CntNoWrap_A	7891491	7231205	0	0
DetectStDropOut_A	7891491	8	0	0
DetectedOut_A	7891491	981467	0	0
DetectedPulseOut_A	7891491	48	0	0
DisabledIdleSt_A	7891491	5130426	0	0
DisabledNoDetection_A	7891491	5132821	0	0
EnterDebounceSt_A	7891491	126	0	0
EnterDetectSt_A	7891491	56	0	0
EnterStableSt_A	7891491	48	0	0
PulseIsPulse_A	7891491	48	0	0
StayInStableSt	7891491	981419	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_sticky_sva.StableStDropOut_A	7891491	243897	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	181	0	0
T2	837	4	0	0
T3	11228	0	0	0
T6	28425	2	0	0
T8	0	6	0	0
T11	0	2	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	2	0	0
T60	0	1	0	0
T61	429	0	0	0
T67	0	4	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	189284	0	0
T2	837	110	0	0
T3	11228	0	0	0
T6	28425	80	0	0
T8	0	450	0	0
T11	0	65	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	28	0	0
T60	0	26	0	0
T61	429	0	0	0
T67	0	42	0	0
T68	0	61	0	0
T69	0	65	0	0
T70	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231205	0	0
T1	16990	16578	0	0
T2	837	432	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	8	0	0
T77	803	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T122	0	1	0	0
T123	130652	0	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	450	0	0	0
T127	20791	0	0	0
T128	8774	0	0	0
T129	625	0	0	0
T130	622	0	0	0
T131	505	0	0	0
T132	523	0	0	0
T133	2408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	981467	0	0
T2	837	88	0	0
T3	11228	0	0	0
T6	28425	540	0	0
T8	0	666	0	0
T11	0	61	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	9	0	0
T61	429	0	0	0
T67	0	130	0	0
T68	0	422	0	0
T70	0	8	0	0
T118	0	441	0	0
T119	0	320	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	48	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	1	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T70	0	1	0	0
T118	0	1	0	0
T119	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	5130426	0	0
T1	16990	16578	0	0
T2	837	137	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	5132821	0	0
T1	16990	16582	0	0
T2	837	138	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	126	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	5	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T60	0	1	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	56	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	1	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T70	0	1	0	0
T118	0	1	0	0
T119	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	48	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	1	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T70	0	1	0	0
T118	0	1	0	0
T119	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	48	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	1	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T61	429	0	0	0
T67	0	2	0	0
T68	0	1	0	0
T70	0	1	0	0
T118	0	1	0	0
T119	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	981419	0	0
T2	837	86	0	0
T3	11228	0	0	0
T6	28425	539	0	0
T8	0	665	0	0
T11	0	60	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	8	0	0
T61	429	0	0	0
T67	0	128	0	0
T68	0	421	0	0
T70	0	7	0	0
T118	0	440	0	0
T119	0	317	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	243897	0	0
T2	837	71	0	0
T3	11228	0	0	0
T6	28425	178	0	0
T8	0	106	0	0
T11	0	27	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	81	0	0
T61	429	0	0	0
T67	0	709	0	0
T68	0	85	0	0
T70	0	45	0	0
T118	0	92	0	0
T119	0	156	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T2,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T1,T13,T2
1	1	Covered	T2,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Unreachable
1	0	Covered	T2,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T8
DetectSt	168	Covered	T2,T6,T8
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T2,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T8
DebounceSt->IdleSt	163	Covered	T2,T60,T67
DetectSt->IdleSt	186	Covered	T2,T77,T78
DetectSt->StableSt	191	Covered	T2,T6,T8
IdleSt->DebounceSt	148	Covered	T2,T6,T8
StableSt->IdleSt	206	Covered	T2,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T8
0	1	Covered	T2,T6,T8
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T8
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T60,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T2,T77,T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	165	0	0
CntIncr_A	7891491	191671	0	0
CntNoWrap_A	7891491	7231221	0	0
DetectStDropOut_A	7891491	11	0	0
DetectedOut_A	7891491	306722	0	0
DetectedPulseOut_A	7891491	54	0	0
DisabledIdleSt_A	7891491	5130426	0	0
DisabledNoDetection_A	7891491	5132821	0	0
EnterDebounceSt_A	7891491	101	0	0
EnterDetectSt_A	7891491	65	0	0
EnterStableSt_A	7891491	54	0	0
PulseIsPulse_A	7891491	54	0	0
StayInStableSt	7891491	306668	0	0
gen_high_event_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_sticky_sva.StableStDropOut_A	7891491	1598498	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	165	0	0
T2	837	5	0	0
T3	11228	0	0	0
T6	28425	2	0	0
T8	0	4	0	0
T11	0	2	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	2	0	0
T60	0	1	0	0
T61	429	0	0	0
T67	0	7	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	191671	0	0
T2	837	141	0	0
T3	11228	0	0	0
T6	28425	100	0	0
T8	0	150	0	0
T11	0	15	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	56	0	0
T60	0	34	0	0
T61	429	0	0	0
T67	0	490	0	0
T68	0	28	0	0
T69	0	67	0	0
T70	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231221	0	0
T1	16990	16578	0	0
T2	837	431	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	11	0	0
T2	837	1	0	0
T3	11228	0	0	0
T6	28425	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T61	429	0	0	0
T77	0	2	0	0
T78	0	2	0	0
T134	0	2	0	0
T135	0	1	0	0
T136	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	306722	0	0
T2	837	1	0	0
T3	11228	0	0	0
T6	28425	657	0	0
T8	0	851	0	0
T11	0	4	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	49	0	0
T61	429	0	0	0
T68	0	196	0	0
T116	0	142	0	0
T118	0	123	0	0
T119	0	198	0	0
T120	0	201	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	54	0	0
T2	837	1	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T61	429	0	0	0
T68	0	1	0	0
T116	0	1	0	0
T118	0	1	0	0
T119	0	3	0	0
T120	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	5130426	0	0
T1	16990	16578	0	0
T2	837	137	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	5132821	0	0
T1	16990	16582	0	0
T2	837	138	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	101	0	0
T2	837	3	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T60	0	1	0	0
T61	429	0	0	0
T67	0	7	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	65	0	0
T2	837	2	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T61	429	0	0	0
T68	0	1	0	0
T116	0	1	0	0
T118	0	1	0	0
T119	0	3	0	0
T120	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	54	0	0
T2	837	1	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T61	429	0	0	0
T68	0	1	0	0
T116	0	1	0	0
T118	0	1	0	0
T119	0	3	0	0
T120	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	54	0	0
T2	837	1	0	0
T3	11228	0	0	0
T6	28425	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	1	0	0
T61	429	0	0	0
T68	0	1	0	0
T116	0	1	0	0
T118	0	1	0	0
T119	0	3	0	0
T120	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	306668	0	0
T6	28425	656	0	0
T8	0	849	0	0
T11	0	3	0	0
T22	497	0	0	0
T23	525	0	0	0
T24	502	0	0	0
T26	741	0	0	0
T27	5366	0	0	0
T32	1111	0	0	0
T37	0	48	0	0
T48	1667	0	0	0
T58	603	0	0	0
T61	429	0	0	0
T68	0	195	0	0
T116	0	141	0	0
T118	0	122	0	0
T119	0	195	0	0
T120	0	198	0	0
T137	0	38	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1598498	0	0
T2	837	43	0	0
T3	11228	0	0	0
T6	28425	51	0	0
T8	0	325	0	0
T11	0	145	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T37	0	27	0	0
T61	429	0	0	0
T68	0	356	0	0
T116	0	173	0	0
T118	0	497	0	0
T119	0	411	0	0
T120	0	852	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T42,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T42,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T42,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T41,T42
1	0	Covered	T4,T1,T5
1	1	Covered	T12,T42,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T42,T46
0	1	Covered	T81,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T42,T46
0	1	Covered	T12,T46,T38
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T42,T46
1	-	Covered	T12,T46,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T42,T46
DetectSt	168	Covered	T12,T42,T46
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T42,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T42,T46
DebounceSt->IdleSt	163	Covered	T69,T138
DetectSt->IdleSt	186	Covered	T81,T98
DetectSt->StableSt	191	Covered	T12,T42,T46
IdleSt->DebounceSt	148	Covered	T12,T42,T46
StableSt->IdleSt	206	Covered	T12,T42,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T42,T46
0	1	Covered	T12,T42,T46
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T42,T46
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T42,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T42,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T138
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T42,T46
DetectSt	-	-	-	-	1	-	-	Covered	T81,T98
DetectSt	-	-	-	-	0	1	-	Covered	T12,T42,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T46,T38
StableSt	-	-	-	-	-	-	0	Covered	T12,T42,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	94	0	0
CntIncr_A	7891491	102366	0	0
CntNoWrap_A	7891491	7231292	0	0
DetectStDropOut_A	7891491	2	0	0
DetectedOut_A	7891491	67225	0	0
DetectedPulseOut_A	7891491	44	0	0
DisabledIdleSt_A	7891491	6879143	0	0
DisabledNoDetection_A	7891491	6881487	0	0
EnterDebounceSt_A	7891491	48	0	0
EnterDetectSt_A	7891491	46	0	0
EnterStableSt_A	7891491	44	0	0
PulseIsPulse_A	7891491	44	0	0
StayInStableSt	7891491	67156	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	94	0	0
T12	63037	8	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	2	0	0
T38	0	4	0	0
T41	528	0	0	0
T42	0	2	0	0
T46	0	4	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	2	0	0
T111	0	2	0	0
T139	0	2	0	0
T140	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	102366	0	0
T12	63037	269	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	43	0	0
T38	0	58	0	0
T41	528	0	0	0
T42	0	54	0	0
T46	0	34	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	25	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	55	0	0
T111	0	94	0	0
T139	0	35496	0	0
T140	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231292	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2	0	0
T81	942	1	0	0
T98	0	1	0	0
T141	526	0	0	0
T142	6723	0	0	0
T143	1301	0	0	0
T144	402	0	0	0
T145	407	0	0	0
T146	728	0	0	0
T147	902	0	0	0
T148	738	0	0	0
T149	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	67225	0	0
T12	63037	223	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	41	0	0
T38	0	83	0	0
T41	528	0	0	0
T42	0	358	0	0
T46	0	82	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	39	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	52	0	0
T111	0	50	0	0
T139	0	46	0	0
T140	0	173	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	44	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T41	528	0	0	0
T42	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	1	0	0
T111	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6879143	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6881487	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	48	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T41	528	0	0	0
T42	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	1	0	0
T111	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	46	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T41	528	0	0	0
T42	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	1	0	0
T111	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	44	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T41	528	0	0	0
T42	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	1	0	0
T111	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	44	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T38	0	2	0	0
T41	528	0	0	0
T42	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	1	0	0
T111	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	67156	0	0
T12	63037	217	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	39	0	0
T38	0	80	0	0
T41	528	0	0	0
T42	0	356	0	0
T46	0	79	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	38	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	50	0	0
T111	0	49	0	0
T139	0	44	0	0
T140	0	171	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	18	0	0
T12	63037	2	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	1	0	0
T41	528	0	0	0
T46	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T25,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T8,T12,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T25,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T13,T3
1	1	Covered	T8,T12,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T43
0	1	Covered	T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T43
0	1	Covered	T12,T25,T39
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T25,T43
1	-	Covered	T12,T25,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T12,T25
DetectSt	168	Covered	T12,T25,T43
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T25,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T25,T43
DebounceSt->IdleSt	163	Covered	T8,T69,T73
DetectSt->IdleSt	186	Covered	T155
DetectSt->StableSt	191	Covered	T12,T25,T43
IdleSt->DebounceSt	148	Covered	T8,T12,T25
StableSt->IdleSt	206	Covered	T12,T25,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T25,T43
0	1	Covered	T8,T12,T25
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T25,T43
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T12,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T25,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T154,T156
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T12,T25
DetectSt	-	-	-	-	1	-	-	Covered	T155
DetectSt	-	-	-	-	0	1	-	Covered	T12,T25,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T25,T39
StableSt	-	-	-	-	-	-	0	Covered	T12,T25,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	122	0	0
CntIncr_A	7891491	13615	0	0
CntNoWrap_A	7891491	7231264	0	0
DetectStDropOut_A	7891491	1	0	0
DetectedOut_A	7891491	4735	0	0
DetectedPulseOut_A	7891491	58	0	0
DisabledIdleSt_A	7891491	7203396	0	0
DisabledNoDetection_A	7891491	7205742	0	0
EnterDebounceSt_A	7891491	65	0	0
EnterDetectSt_A	7891491	59	0	0
EnterStableSt_A	7891491	58	0	0
PulseIsPulse_A	7891491	58	0	0
StayInStableSt	7891491	4649	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7891491	2679	0	0
gen_low_level_sva.LowLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	122	0	0
T12	63037	6	0	0
T25	7704	2	0	0
T33	22365	0	0	0
T37	0	2	0	0
T39	0	2	0	0
T41	528	0	0	0
T43	0	2	0	0
T45	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T73	0	3	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	2	0	0
T158	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	13615	0	0
T8	39472	6436	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	237	0	0
T25	0	26	0	0
T37	0	85	0	0
T39	0	68	0	0
T43	0	54	0	0
T45	0	62	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T69	0	26	0	0
T157	0	27	0	0
T158	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231264	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1	0	0
T135	717	0	0	0
T155	611	1	0	0
T159	422	0	0	0
T160	8401	0	0	0
T161	713	0	0	0
T162	38443	0	0	0
T163	490	0	0	0
T164	1651	0	0	0
T165	423	0	0	0
T166	539	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	4735	0	0
T12	63037	134	0	0
T25	7704	72	0	0
T33	22365	0	0	0
T37	0	166	0	0
T39	0	206	0	0
T41	528	0	0	0
T43	0	218	0	0
T45	0	130	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	63	0	0
T85	568	0	0	0
T86	735	0	0	0
T150	0	210	0	0
T157	0	39	0	0
T158	0	98	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	58	0	0
T12	63037	3	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T41	528	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T150	0	5	0	0
T157	0	1	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7203396	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7205742	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	65	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	3	0	0
T25	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T69	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	59	0	0
T12	63037	3	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T41	528	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T150	0	5	0	0
T157	0	1	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	58	0	0
T12	63037	3	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T41	528	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T150	0	5	0	0
T157	0	1	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	58	0	0
T12	63037	3	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T41	528	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T150	0	5	0	0
T157	0	1	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	4649	0	0
T12	63037	131	0	0
T25	7704	71	0	0
T33	22365	0	0	0
T37	0	164	0	0
T39	0	205	0	0
T41	528	0	0	0
T43	0	216	0	0
T45	0	128	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	61	0	0
T85	568	0	0	0
T86	735	0	0	0
T150	0	204	0	0
T157	0	37	0	0
T158	0	96	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2679	0	0
T2	837	0	0	0
T3	11228	0	0	0
T6	28425	20	0	0
T8	0	23	0	0
T13	493	2	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	3	0	0
T22	497	4	0	0
T23	525	6	0	0
T24	0	4	0	0
T54	0	6	0	0
T61	0	2	0	0
T62	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	29	0	0
T12	63037	3	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T39	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T150	0	4	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0