Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	90.21	93.48	90.48		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	97.61	97.83	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	97.61	97.83	95.24		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.21	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.61	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.61	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T7,T10,T34
1	0	Covered	T69,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T71,T69,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T6
1	-	Covered	T1,T3,T6

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.21	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T5,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T5,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T5,T26

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T26
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T5,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T26
0	1	Covered	T43,T72,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T26
0	1	Covered	T4,T5,T26
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T5,T26
1	-	Covered	T4,T5,T26

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T27
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T27
0	1	Covered	T27,T9,T47
1	0	Covered	T3,T9,T47

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
1	0	Covered	T74,T75,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T1,T3,T9

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T1,T13,T2
1	1	Covered	T2,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T2,T77,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Unreachable
1	0	Covered	T2,T6,T8

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.61	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.61	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T8,T12,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T8,T12,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T8,T12,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T4,T1,T5
1	1	Covered	T8,T12,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T25
0	1	Covered	T79,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T25
0	1	Covered	T8,T12,T25
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T12,T25
1	-	Covered	T8,T12,T25

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T13,T2,T17

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T13,T2,T17
1	1	Covered	T13,T2,T17

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T13,T2,T17
1	1	Covered	T2,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T77,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Unreachable
1	0	Covered	T2,T6,T8

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T2,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T8
1	0	Covered	T4,T1,T5
1	1	Covered	T2,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Covered	T8,T37,T68
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T8
0	1	Unreachable
1	0	Covered	T2,T6,T8

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T5,T26
DetectSt	168	Covered	T4,T5,T26
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T4,T5,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T5,T26
DebounceSt->IdleSt	163	Covered	T4,T26,T48
DetectSt->IdleSt	186	Covered	T8,T43,T37
DetectSt->StableSt	191	Covered	T4,T5,T26
IdleSt->DebounceSt	148	Covered	T4,T5,T26
StableSt->IdleSt	206	Covered	T4,T5,T26

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.21	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T26
0	1	Covered	T4,T5,T26
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T26
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T5,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T5,T26
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T26,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T5,T26
DetectSt	-	-	-	-	1	-	-	Covered	T8,T43,T37
DetectSt	-	-	-	-	0	1	-	Covered	T4,T5,T26
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T4,T5,T26
StableSt	-	-	-	-	-	-	0	Covered	T4,T5,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T60,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T3,T27
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T27
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	205178766	17692	0	0
CntIncr_A	205178766	1760655	0	0
CntNoWrap_A	205178766	187998344	0	0
DetectStDropOut_A	205178766	1899	0	0
DetectedOut_A	205178766	2286250	0	0
DetectedPulseOut_A	205178766	5798	0	0
DisabledIdleSt_A	205178766	175807784	0	0
DisabledNoDetection_A	205178766	175865748	0	0
EnterDebounceSt_A	205178766	9162	0	0
EnterDetectSt_A	205178766	8558	0	0
EnterStableSt_A	205178766	5797	0	0
PulseIsPulse_A	205178766	5797	0	0
StayInStableSt	205178766	2279687	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	71023419	51999	0	0
gen_high_event_sva.HighLevelEvent_A	39457455	36168925	0	0
gen_high_level_sva.HighLevelEvent_A	134155347	122974345	0	0
gen_low_level_sva.LowLevelEvent_A	71023419	65104065	0	0
gen_not_sticky_sva.StableStDropOut_A	181504293	4784	0	0
gen_sticky_sva.StableStDropOut_A	23674473	2943918	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	17692	0	0
T1	152910	24	0	0
T2	7533	0	0	0
T3	101052	2	0	0
T4	5334	3	0	0
T5	107613	2	0	0
T6	227400	6	0	0
T7	0	2	0	0
T8	0	13	0	0
T9	0	44	0	0
T12	63037	10	0	0
T13	4437	0	0	0
T14	6867	0	0	0
T15	6363	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T25	7704	4	0	0
T26	0	3	0	0
T27	0	44	0	0
T33	22365	34	0	0
T41	528	0	0	0
T47	0	48	0	0
T48	0	5	0	0
T49	0	2	0	0
T51	5071	60	0	0
T52	0	8	0	0
T53	0	46	0	0
T59	2455	1	0	0
T63	3020	0	0	0
T64	526	0	0	0
T84	0	14	0	0
T85	568	0	0	0
T86	735	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	1760655	0	0
T1	152910	911	0	0
T2	7533	0	0	0
T3	101052	57	0	0
T4	5334	4796	0	0
T5	107613	68	0	0
T6	227400	152	0	0
T7	0	74	0	0
T8	39472	531	0	0
T9	18832	1729	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	483	0	0
T13	4437	0	0	0
T14	6867	0	0	0
T15	6363	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T25	0	93	0	0
T26	0	162	0	0
T27	0	1209	0	0
T33	0	1259	0	0
T47	6969	1272	0	0
T48	0	56	0	0
T49	0	22	0	0
T50	650	0	0	0
T51	0	1467	0	0
T52	0	334	0	0
T53	0	1486	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T59	0	20	0	0
T84	0	1009	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	187998344	0	0
T1	441740	430924	0	0
T2	21762	11323	0	0
T3	291928	280944	0	0
T4	138684	128255	0	0
T5	310882	300454	0	0
T13	12818	2392	0	0
T14	19838	9412	0	0
T15	18382	7956	0	0
T16	10452	26	0	0
T17	11050	624	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	1899	0	0
T9	0	6	0	0
T24	502	0	0	0
T26	741	0	0	0
T27	5366	22	0	0
T32	1111	0	0	0
T51	0	30	0	0
T53	0	7	0	0
T66	0	25	0	0
T72	145694	1	0	0
T87	0	13	0	0
T88	0	9	0	0
T89	18364	2	0	0
T90	0	3	0	0
T91	0	2	0	0
T92	0	4	0	0
T93	0	1	0	0
T94	0	7	0	0
T95	0	10	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	10	0	0
T100	0	6	0	0
T101	0	3	0	0
T102	525	0	0	0
T103	11132	0	0	0
T104	405	0	0	0
T105	680	0	0	0
T106	424	0	0	0
T107	402	0	0	0
T108	1496	0	0	0
T109	1316	0	0	0
T110	711	0	0	0
T111	997	0	0	0
T112	4413	0	0	0
T113	441	0	0	0
T114	428	0	0	0
T115	406	0	0	0
T116	958	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	2286250	0	0
T1	152910	1067	0	0
T2	7533	0	0	0
T3	101052	0	0	0
T4	5334	6	0	0
T5	107613	6	0	0
T6	227400	16	0	0
T7	0	13	0	0
T8	0	99	0	0
T12	63037	35	0	0
T13	4437	0	0	0
T14	6867	0	0	0
T15	6363	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T25	7704	13	0	0
T26	0	4	0	0
T33	22365	1269	0	0
T34	0	64	0	0
T37	0	57	0	0
T41	528	0	0	0
T47	0	1509	0	0
T48	0	13	0	0
T49	0	4	0	0
T51	5071	0	0	0
T52	0	19	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T65	0	110	0	0
T74	0	2047	0	0
T75	0	5063	0	0
T84	0	57	0	0
T85	568	0	0	0
T86	735	0	0	0
T117	0	1261	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	5798	0	0
T1	152910	12	0	0
T2	7533	0	0	0
T3	101052	0	0	0
T4	5334	1	0	0
T5	107613	1	0	0
T6	227400	3	0	0
T7	0	1	0	0
T8	0	5	0	0
T12	63037	4	0	0
T13	4437	0	0	0
T14	6867	0	0	0
T15	6363	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T25	7704	2	0	0
T26	0	1	0	0
T33	22365	17	0	0
T34	0	2	0	0
T37	0	4	0	0
T41	528	0	0	0
T47	0	24	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	5071	0	0	0
T52	0	3	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T65	0	6	0	0
T74	0	29	0	0
T75	0	13	0	0
T84	0	7	0	0
T85	568	0	0	0
T86	735	0	0	0
T117	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	175807784	0	0
T1	441740	395513	0	0
T2	21762	10439	0	0
T3	291928	263517	0	0
T4	138684	123377	0	0
T5	310882	300337	0	0
T13	12818	2392	0	0
T14	19838	9412	0	0
T15	18382	7956	0	0
T16	10452	26	0	0
T17	11050	624	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	175865748	0	0
T1	441740	395605	0	0
T2	21762	10465	0	0
T3	291928	263585	0	0
T4	138684	123403	0	0
T5	310882	300363	0	0
T13	12818	2418	0	0
T14	19838	9438	0	0
T15	18382	7982	0	0
T16	10452	52	0	0
T17	11050	650	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	9162	0	0
T1	152910	12	0	0
T2	7533	0	0	0
T3	101052	1	0	0
T4	5334	2	0	0
T5	107613	1	0	0
T6	227400	3	0	0
T7	0	1	0	0
T8	39472	8	0	0
T9	18832	22	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	6	0	0
T13	4437	0	0	0
T14	6867	0	0	0
T15	6363	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T25	0	2	0	0
T26	0	2	0	0
T27	0	22	0	0
T33	0	17	0	0
T47	6969	24	0	0
T48	0	3	0	0
T49	0	1	0	0
T50	650	0	0	0
T51	0	30	0	0
T52	0	6	0	0
T53	0	23	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T59	0	1	0	0
T84	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	8558	0	0
T1	152910	12	0	0
T2	7533	0	0	0
T3	101052	1	0	0
T4	5334	1	0	0
T5	107613	1	0	0
T6	227400	3	0	0
T7	0	1	0	0
T8	0	5	0	0
T9	0	22	0	0
T12	63037	4	0	0
T13	4437	0	0	0
T14	6867	0	0	0
T15	6363	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T25	7704	2	0	0
T26	0	1	0	0
T27	0	22	0	0
T33	22365	17	0	0
T34	0	2	0	0
T37	0	4	0	0
T41	528	0	0	0
T47	0	24	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	5071	30	0	0
T52	0	3	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T84	0	7	0	0
T85	568	0	0	0
T86	735	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	5797	0	0
T1	152910	12	0	0
T2	7533	0	0	0
T3	101052	0	0	0
T4	5334	1	0	0
T5	107613	1	0	0
T6	227400	3	0	0
T7	0	1	0	0
T8	0	5	0	0
T12	63037	4	0	0
T13	4437	0	0	0
T14	6867	0	0	0
T15	6363	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T25	7704	2	0	0
T26	0	1	0	0
T33	22365	17	0	0
T34	0	2	0	0
T37	0	4	0	0
T41	528	0	0	0
T47	0	24	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	5071	0	0	0
T52	0	3	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T65	0	6	0	0
T74	0	29	0	0
T75	0	13	0	0
T84	0	7	0	0
T85	568	0	0	0
T86	735	0	0	0
T117	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	5797	0	0
T1	152910	12	0	0
T2	7533	0	0	0
T3	101052	0	0	0
T4	5334	1	0	0
T5	107613	1	0	0
T6	227400	3	0	0
T7	0	1	0	0
T8	0	5	0	0
T12	63037	4	0	0
T13	4437	0	0	0
T14	6867	0	0	0
T15	6363	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T25	7704	2	0	0
T26	0	1	0	0
T33	22365	17	0	0
T34	0	2	0	0
T37	0	4	0	0
T41	528	0	0	0
T47	0	24	0	0
T48	0	2	0	0
T49	0	1	0	0
T51	5071	0	0	0
T52	0	3	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T65	0	6	0	0
T74	0	29	0	0
T75	0	13	0	0
T84	0	7	0	0
T85	568	0	0	0
T86	735	0	0	0
T117	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	205178766	2279687	0	0
T1	152910	1054	0	0
T2	7533	0	0	0
T3	101052	0	0	0
T4	5334	5	0	0
T5	107613	5	0	0
T6	227400	13	0	0
T7	0	12	0	0
T8	0	94	0	0
T12	63037	31	0	0
T13	4437	0	0	0
T14	6867	0	0	0
T15	6363	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T25	7704	11	0	0
T26	0	3	0	0
T33	22365	1250	0	0
T34	0	62	0	0
T37	0	53	0	0
T41	528	0	0	0
T47	0	1485	0	0
T48	0	11	0	0
T49	0	3	0	0
T51	5071	0	0	0
T52	0	16	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T65	0	104	0	0
T74	0	2018	0	0
T75	0	5047	0	0
T84	0	50	0	0
T85	568	0	0	0
T86	735	0	0	0
T117	0	1254	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71023419	51999	0	0
T1	118930	189	0	0
T2	7533	16	0	0
T3	101052	201	0	0
T4	16002	9	0	0
T5	83699	9	0	0
T6	170550	254	0	0
T8	0	23	0	0
T13	4437	59	0	0
T14	6867	2	0	0
T15	6363	3	0	0
T16	3618	0	0	0
T17	3825	18	0	0
T22	994	53	0	0
T23	1050	44	0	0
T24	0	22	0	0
T27	0	90	0	0
T54	0	6	0	0
T58	0	3	0	0
T61	0	16	0	0
T62	0	4	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39457455	36168925	0	0
T1	84950	82910	0	0
T2	4185	2185	0	0
T3	56140	54075	0	0
T4	26670	24670	0	0
T5	59785	57785	0	0
T13	2465	465	0	0
T14	3815	1815	0	0
T15	3535	1535	0	0
T16	2010	10	0	0
T17	2125	125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134155347	122974345	0	0
T1	288830	281894	0	0
T2	14229	7429	0	0
T3	190876	183855	0	0
T4	90678	83878	0	0
T5	203269	196469	0	0
T13	8381	1581	0	0
T14	12971	6171	0	0
T15	12019	5219	0	0
T16	6834	34	0	0
T17	7225	425	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71023419	65104065	0	0
T1	152910	149238	0	0
T2	7533	3933	0	0
T3	101052	97335	0	0
T4	48006	44406	0	0
T5	107613	104013	0	0
T13	4437	837	0	0
T14	6867	3267	0	0
T15	6363	2763	0	0
T16	3618	18	0	0
T17	3825	225	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181504293	4784	0	0
T1	135920	11	0	0
T2	6696	0	0	0
T3	101052	0	0	0
T4	5334	1	0	0
T5	95656	1	0	0
T6	227400	3	0	0
T7	0	1	0	0
T8	0	5	0	0
T12	63037	4	0	0
T13	3944	0	0	0
T14	6104	0	0	0
T15	5656	0	0	0
T16	3618	0	0	0
T17	3825	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T25	7704	2	0	0
T26	741	1	0	0
T27	5366	0	0	0
T32	1111	0	0	0
T33	0	15	0	0
T34	0	2	0	0
T37	0	4	0	0
T41	528	0	0	0
T47	0	24	0	0
T48	0	2	0	0
T49	0	1	0	0
T52	0	3	0	0
T61	429	0	0	0
T63	3020	0	0	0
T65	0	6	0	0
T74	0	29	0	0
T75	0	10	0	0
T84	0	7	0	0
T117	0	7	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23674473	2943918	0	0
T2	2511	240	0	0
T3	33684	0	0	0
T6	85275	604	0	0
T8	0	574	0	0
T11	0	221	0	0
T14	2289	0	0	0
T15	2121	0	0	0
T16	1206	0	0	0
T17	1275	0	0	0
T22	1491	0	0	0
T23	1575	0	0	0
T37	0	108	0	0
T61	1287	0	0	0
T67	0	1127	0	0
T68	0	503	0	0
T70	0	109	0	0
T116	0	173	0	0
T118	0	908	0	0
T119	0	692	0	0
T120	0	1348	0	0