Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T43,T42,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T43,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T43,T42,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T43,T42
1	0	Covered	T4,T1,T5
1	1	Covered	T12,T43,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T42,T45
0	1	Covered	T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T42,T45
0	1	Covered	T42,T150,T137
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T42,T45
1	-	Covered	T42,T150,T137

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T43,T42
DetectSt	168	Covered	T43,T42,T45
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T43,T42,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T42,T45
DebounceSt->IdleSt	163	Covered	T12,T69
DetectSt->IdleSt	186	Covered	T81
DetectSt->StableSt	191	Covered	T43,T42,T45
IdleSt->DebounceSt	148	Covered	T12,T43,T42
StableSt->IdleSt	206	Covered	T43,T42,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T43,T42,T45
0	1	Covered	T12,T43,T42
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T42,T45
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T43,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T42,T45
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T43,T42
DetectSt	-	-	-	-	1	-	-	Covered	T81
DetectSt	-	-	-	-	0	1	-	Covered	T43,T42,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T150,T137
StableSt	-	-	-	-	-	-	0	Covered	T43,T42,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	75	0	0
CntIncr_A	7891491	68869	0	0
CntNoWrap_A	7891491	7231311	0	0
DetectStDropOut_A	7891491	1	0	0
DetectedOut_A	7891491	2043	0	0
DetectedPulseOut_A	7891491	36	0	0
DisabledIdleSt_A	7891491	6933980	0	0
DisabledNoDetection_A	7891491	6936332	0	0
EnterDebounceSt_A	7891491	39	0	0
EnterDetectSt_A	7891491	37	0	0
EnterStableSt_A	7891491	36	0	0
PulseIsPulse_A	7891491	36	0	0
StayInStableSt	7891491	1986	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	75	0	0
T34	20072	0	0	0
T37	18200	0	0	0
T38	0	2	0	0
T40	0	2	0	0
T42	4214	4	0	0
T43	3042	2	0	0
T45	601	2	0	0
T65	7287	0	0	0
T69	0	1	0	0
T108	0	2	0	0
T137	0	4	0	0
T150	0	12	0	0
T170	0	2	0	0
T171	422	0	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	68869	0	0
T12	63037	2465	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	29	0	0
T40	0	84	0	0
T41	528	0	0	0
T42	0	108	0	0
T43	0	54	0	0
T45	0	62	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	26	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	55	0	0
T137	0	34	0	0
T150	0	479	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231311	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1	0	0
T81	942	1	0	0
T141	526	0	0	0
T142	6723	0	0	0
T143	1301	0	0	0
T144	402	0	0	0
T145	407	0	0	0
T146	728	0	0	0
T147	902	0	0	0
T148	738	0	0	0
T149	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2043	0	0
T34	20072	0	0	0
T37	18200	0	0	0
T38	0	40	0	0
T40	0	49	0	0
T42	4214	106	0	0
T43	3042	45	0	0
T45	601	64	0	0
T57	0	5	0	0
T65	7287	0	0	0
T108	0	108	0	0
T137	0	67	0	0
T150	0	248	0	0
T170	0	38	0	0
T171	422	0	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	36	0	0
T34	20072	0	0	0
T37	18200	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	4214	2	0	0
T43	3042	1	0	0
T45	601	1	0	0
T57	0	1	0	0
T65	7287	0	0	0
T108	0	1	0	0
T137	0	2	0	0
T150	0	6	0	0
T170	0	1	0	0
T171	422	0	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6933980	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6936332	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	39	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	528	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T108	0	1	0	0
T137	0	2	0	0
T150	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	37	0	0
T34	20072	0	0	0
T37	18200	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	4214	2	0	0
T43	3042	1	0	0
T45	601	1	0	0
T57	0	1	0	0
T65	7287	0	0	0
T108	0	1	0	0
T137	0	2	0	0
T150	0	6	0	0
T170	0	1	0	0
T171	422	0	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	36	0	0
T34	20072	0	0	0
T37	18200	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	4214	2	0	0
T43	3042	1	0	0
T45	601	1	0	0
T57	0	1	0	0
T65	7287	0	0	0
T108	0	1	0	0
T137	0	2	0	0
T150	0	6	0	0
T170	0	1	0	0
T171	422	0	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	36	0	0
T34	20072	0	0	0
T37	18200	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T42	4214	2	0	0
T43	3042	1	0	0
T45	601	1	0	0
T57	0	1	0	0
T65	7287	0	0	0
T108	0	1	0	0
T137	0	2	0	0
T150	0	6	0	0
T170	0	1	0	0
T171	422	0	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1986	0	0
T34	20072	0	0	0
T37	18200	0	0	0
T38	0	38	0	0
T40	0	47	0	0
T42	4214	103	0	0
T43	3042	43	0	0
T45	601	62	0	0
T57	0	4	0	0
T65	7287	0	0	0
T108	0	106	0	0
T137	0	65	0	0
T150	0	240	0	0
T170	0	36	0	0
T171	422	0	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	14	0	0
T34	20072	0	0	0
T37	18200	0	0	0
T42	4214	1	0	0
T45	601	0	0	0
T65	7287	0	0	0
T98	0	1	0	0
T99	0	1	0	0
T137	0	2	0	0
T138	0	1	0	0
T150	0	4	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	502	0	0	0
T180	38159	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T25,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T25,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T25,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T41
1	0	Covered	T1,T13,T14
1	1	Covered	T12,T25,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T41
0	1	Covered	T12,T25,T41
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T25,T41
1	-	Covered	T12,T25,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T25,T41
DetectSt	168	Covered	T12,T25,T41
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T25,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T25,T41
DebounceSt->IdleSt	163	Covered	T69,T40,T80
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T25,T41
IdleSt->DebounceSt	148	Covered	T12,T25,T41
StableSt->IdleSt	206	Covered	T12,T25,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T25,T41
0	1	Covered	T12,T25,T41
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T25,T41
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T25,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T25,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T80,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T25,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T25,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T25,T41
StableSt	-	-	-	-	-	-	0	Covered	T12,T25,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	106	0	0
CntIncr_A	7891491	82902	0	0
CntNoWrap_A	7891491	7231280	0	0
DetectStDropOut_A	7891491	0	0	0
DetectedOut_A	7891491	70893	0	0
DetectedPulseOut_A	7891491	51	0	0
DisabledIdleSt_A	7891491	6937750	0	0
DisabledNoDetection_A	7891491	6940099	0	0
EnterDebounceSt_A	7891491	55	0	0
EnterDetectSt_A	7891491	51	0	0
EnterStableSt_A	7891491	51	0	0
PulseIsPulse_A	7891491	51	0	0
StayInStableSt	7891491	70818	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7891491	3001	0	0
gen_low_level_sva.LowLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	106	0	0
T12	63037	2	0	0
T25	7704	2	0	0
T33	22365	0	0	0
T35	0	4	0	0
T40	0	1	0	0
T41	528	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	2	0	0
T130	0	2	0	0
T150	0	4	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	82902	0	0
T12	63037	15438	0	0
T25	7704	26	0	0
T33	22365	0	0	0
T35	0	86	0	0
T40	0	84	0	0
T41	528	28	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	24	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	94	0	0
T130	0	64	0	0
T150	0	135	0	0
T181	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231280	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	70893	0	0
T12	63037	1864	0	0
T25	7704	105	0	0
T33	22365	0	0	0
T35	0	158	0	0
T41	528	8	0	0
T51	5071	0	0	0
T57	0	4	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	357	0	0
T130	0	149	0	0
T150	0	304	0	0
T170	0	134	0	0
T181	0	152	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	51	0	0
T12	63037	1	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T35	0	2	0	0
T41	528	1	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T130	0	1	0	0
T150	0	2	0	0
T170	0	1	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6937750	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6940099	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	55	0	0
T12	63037	1	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T35	0	2	0	0
T40	0	1	0	0
T41	528	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T130	0	1	0	0
T150	0	2	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	51	0	0
T12	63037	1	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T35	0	2	0	0
T41	528	1	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T130	0	1	0	0
T150	0	2	0	0
T170	0	1	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	51	0	0
T12	63037	1	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T35	0	2	0	0
T41	528	1	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T130	0	1	0	0
T150	0	2	0	0
T170	0	1	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	51	0	0
T12	63037	1	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T35	0	2	0	0
T41	528	1	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T130	0	1	0	0
T150	0	2	0	0
T170	0	1	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	70818	0	0
T12	63037	1863	0	0
T25	7704	104	0	0
T33	22365	0	0	0
T35	0	155	0	0
T41	528	7	0	0
T51	5071	0	0	0
T57	0	3	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	356	0	0
T130	0	147	0	0
T150	0	301	0	0
T170	0	133	0	0
T181	0	150	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	3001	0	0
T2	837	0	0	0
T3	11228	0	0	0
T6	28425	17	0	0
T13	493	5	0	0
T14	763	2	0	0
T15	707	3	0	0
T16	402	0	0	0
T17	425	4	0	0
T22	497	5	0	0
T23	525	5	0	0
T24	0	6	0	0
T58	0	3	0	0
T61	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	26	0	0
T12	63037	1	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T35	0	1	0	0
T41	528	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T167	0	1	0	0
T170	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T13,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T13,T2
1	1	Covered	T1,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T8,T25,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T8,T25,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T8,T25,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T25,T41
1	0	Covered	T1,T13,T2
1	1	Covered	T8,T25,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T25,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T25,T41
0	1	Covered	T8,T25,T41
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T25,T41
1	-	Covered	T8,T25,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T25,T41
DetectSt	168	Covered	T8,T25,T41
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T8,T25,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T25,T41
DebounceSt->IdleSt	163	Covered	T69,T73,T150
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T25,T41
IdleSt->DebounceSt	148	Covered	T8,T25,T41
StableSt->IdleSt	206	Covered	T8,T25,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T25,T41
0	1	Covered	T8,T25,T41
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T25,T41
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T25,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T25,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T150,T80
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T25,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T25,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T25,T41
StableSt	-	-	-	-	-	-	0	Covered	T8,T25,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	106	0	0
CntIncr_A	7891491	42084	0	0
CntNoWrap_A	7891491	7231280	0	0
DetectStDropOut_A	7891491	0	0	0
DetectedOut_A	7891491	6576	0	0
DetectedPulseOut_A	7891491	50	0	0
DisabledIdleSt_A	7891491	7134306	0	0
DisabledNoDetection_A	7891491	7136651	0	0
EnterDebounceSt_A	7891491	57	0	0
EnterDetectSt_A	7891491	50	0	0
EnterStableSt_A	7891491	50	0	0
PulseIsPulse_A	7891491	50	0	0
StayInStableSt	7891491	6504	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	106	0	0
T8	39472	2	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	4	0	0
T37	0	2	0	0
T38	0	4	0	0
T41	0	2	0	0
T43	0	4	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T139	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	42084	0	0
T8	39472	13	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	52	0	0
T37	0	85	0	0
T38	0	58	0	0
T41	0	28	0	0
T43	0	108	0	0
T45	0	62	0	0
T46	0	17	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T139	0	35496	0	0
T157	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231280	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6576	0	0
T8	39472	58	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	13	0	0
T37	0	166	0	0
T38	0	83	0	0
T41	0	9	0	0
T43	0	143	0	0
T45	0	129	0	0
T46	0	65	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T139	0	2331	0	0
T157	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T139	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7134306	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7136651	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	57	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T139	0	1	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T139	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T139	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T139	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6504	0	0
T8	39472	57	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	11	0	0
T37	0	164	0	0
T38	0	80	0	0
T41	0	8	0	0
T43	0	141	0	0
T45	0	127	0	0
T46	0	64	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T139	0	2330	0	0
T157	0	78	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	27	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	0	0	0
T25	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T111	0	2	0	0
T139	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T2
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T2
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T41
1	0	Covered	T1,T13,T2
1	1	Covered	T12,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T42
0	1	Covered	T12,T42,T35
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T41,T42
1	-	Covered	T12,T42,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T41,T42
DetectSt	168	Covered	T12,T41,T42
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T41,T42
DebounceSt->IdleSt	163	Covered	T12,T69
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T41,T42
IdleSt->DebounceSt	148	Covered	T12,T41,T42
StableSt->IdleSt	206	Covered	T12,T42,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T41,T42
0	1	Covered	T12,T41,T42
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T41,T42
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T12
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T41,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T42,T35
StableSt	-	-	-	-	-	-	0	Covered	T12,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	82	0	0
CntIncr_A	7891491	66739	0	0
CntNoWrap_A	7891491	7231304	0	0
DetectStDropOut_A	7891491	0	0	0
DetectedOut_A	7891491	4028	0	0
DetectedPulseOut_A	7891491	40	0	0
DisabledIdleSt_A	7891491	6947121	0	0
DisabledNoDetection_A	7891491	6949460	0	0
EnterDebounceSt_A	7891491	42	0	0
EnterDetectSt_A	7891491	40	0	0
EnterStableSt_A	7891491	40	0	0
PulseIsPulse_A	7891491	40	0	0
StayInStableSt	7891491	3966	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7891491	6628	0	0
gen_low_level_sva.LowLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	82	0	0
T12	63037	3	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	2	0	0
T39	0	2	0	0
T41	528	2	0	0
T42	0	4	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T79	0	2	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	4	0	0
T150	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	66739	0	0
T12	63037	111	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	43	0	0
T39	0	68	0	0
T41	528	28	0	0
T42	0	108	0	0
T46	0	17	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	24	0	0
T79	0	43	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	188	0	0
T150	0	238	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231304	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	4028	0	0
T12	63037	299	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	117	0	0
T39	0	251	0	0
T41	528	52	0	0
T42	0	117	0	0
T46	0	65	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	38	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	82	0	0
T137	0	84	0	0
T150	0	543	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	40	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T41	528	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	2	0	0
T137	0	2	0	0
T150	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6947121	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6949460	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	42	0	0
T12	63037	2	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T41	528	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	2	0	0
T150	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	40	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T41	528	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	2	0	0
T137	0	2	0	0
T150	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	40	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T41	528	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	2	0	0
T137	0	2	0	0
T150	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	40	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T41	528	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	2	0	0
T137	0	2	0	0
T150	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	3966	0	0
T12	63037	298	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	116	0	0
T39	0	249	0	0
T41	528	50	0	0
T42	0	114	0	0
T46	0	63	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	36	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	79	0	0
T137	0	81	0	0
T150	0	538	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6628	0	0
T1	16990	28	0	0
T2	837	4	0	0
T3	11228	22	0	0
T5	11957	0	0	0
T6	28425	35	0	0
T13	493	11	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	1	0	0
T22	0	8	0	0
T23	0	3	0	0
T27	0	20	0	0
T61	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	17	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T41	528	0	0	0
T42	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T137	0	1	0	0
T150	0	1	0	0
T154	0	2	0	0
T170	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T13,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T13,T3
1	1	Covered	T1,T13,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T41,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T8,T12,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T41,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T41
1	0	Covered	T1,T13,T3
1	1	Covered	T8,T12,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T43
0	1	Covered	T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T43
0	1	Covered	T12,T41,T43
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T41,T43
1	-	Covered	T12,T41,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T12,T41
DetectSt	168	Covered	T12,T41,T43
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T41,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T41,T43
DebounceSt->IdleSt	163	Covered	T8,T69,T170
DetectSt->IdleSt	186	Covered	T79
DetectSt->StableSt	191	Covered	T12,T41,T43
IdleSt->DebounceSt	148	Covered	T8,T12,T41
StableSt->IdleSt	206	Covered	T12,T41,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T41,T43
0	1	Covered	T8,T12,T41
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T41,T43
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T12,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T41,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T170,T185
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T12,T41
DetectSt	-	-	-	-	1	-	-	Covered	T79
DetectSt	-	-	-	-	0	1	-	Covered	T12,T41,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T41,T43
StableSt	-	-	-	-	-	-	0	Covered	T12,T41,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	103	0	0
CntIncr_A	7891491	47945	0	0
CntNoWrap_A	7891491	7231283	0	0
DetectStDropOut_A	7891491	1	0	0
DetectedOut_A	7891491	41484	0	0
DetectedPulseOut_A	7891491	49	0	0
DisabledIdleSt_A	7891491	7114882	0	0
DisabledNoDetection_A	7891491	7117240	0	0
EnterDebounceSt_A	7891491	55	0	0
EnterDetectSt_A	7891491	50	0	0
EnterStableSt_A	7891491	49	0	0
PulseIsPulse_A	7891491	49	0	0
StayInStableSt	7891491	41414	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	103	0	0
T12	63037	6	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T39	0	4	0	0
T41	528	2	0	0
T43	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T79	0	4	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	2	0	0
T139	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	47945	0	0
T8	39472	6435	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	237	0	0
T35	0	86	0	0
T36	0	87	0	0
T39	0	136	0	0
T41	0	28	0	0
T43	0	54	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T69	0	25	0	0
T79	0	86	0	0
T139	0	35496	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231283	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1	0	0
T35	731	0	0	0
T40	2450	0	0	0
T70	1045	0	0	0
T79	681	1	0	0
T186	703	0	0	0
T187	502	0	0	0
T188	502	0	0	0
T189	9310	0	0	0
T190	8945	0	0	0
T191	409	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	41484	0	0
T12	63037	253	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	72	0	0
T36	0	38	0	0
T39	0	145	0	0
T41	528	9	0	0
T43	0	44	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	14	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	40	0	0
T139	0	37873	0	0
T158	0	141	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	49	0	0
T12	63037	3	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T139	0	1	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7114882	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7117240	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	55	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	3	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T69	0	1	0	0
T79	0	2	0	0
T139	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T12	63037	3	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	2	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T139	0	1	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	49	0	0
T12	63037	3	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T139	0	1	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	49	0	0
T12	63037	3	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	2	0	0
T36	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T139	0	1	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	41414	0	0
T12	63037	249	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	69	0	0
T36	0	36	0	0
T39	0	143	0	0
T41	528	8	0	0
T43	0	43	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	13	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	39	0	0
T139	0	37871	0	0
T158	0	140	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	27	0	0
T12	63037	2	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T152	0	1	0	0
T158	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T25,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T25,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T25,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T41
1	0	Covered	T1,T13,T3
1	1	Covered	T12,T25,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T41
0	1	Covered	T150,T183,T98
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T41
0	1	Covered	T12,T39,T79
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T25,T41
1	-	Covered	T12,T39,T79

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T25,T41
DetectSt	168	Covered	T12,T25,T41
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T25,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T25,T41
DebounceSt->IdleSt	163	Covered	T69,T192,T193
DetectSt->IdleSt	186	Covered	T150,T183,T98
DetectSt->StableSt	191	Covered	T12,T25,T41
IdleSt->DebounceSt	148	Covered	T12,T25,T41
StableSt->IdleSt	206	Covered	T12,T25,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T25,T41
0	1	Covered	T12,T25,T41
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T25,T41
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T25,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T25,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T192
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T25,T41
DetectSt	-	-	-	-	1	-	-	Covered	T150,T183,T98
DetectSt	-	-	-	-	0	1	-	Covered	T12,T25,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T39,T79
StableSt	-	-	-	-	-	-	0	Covered	T12,T25,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	96	0	0
CntIncr_A	7891491	2741	0	0
CntNoWrap_A	7891491	7231290	0	0
DetectStDropOut_A	7891491	3	0	0
DetectedOut_A	7891491	3498	0	0
DetectedPulseOut_A	7891491	44	0	0
DisabledIdleSt_A	7891491	7185022	0	0
DisabledNoDetection_A	7891491	7187360	0	0
EnterDebounceSt_A	7891491	50	0	0
EnterDetectSt_A	7891491	47	0	0
EnterStableSt_A	7891491	44	0	0
PulseIsPulse_A	7891491	44	0	0
StayInStableSt	7891491	3426	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7891491	6355	0	0
gen_low_level_sva.LowLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	96	0	0
T12	63037	4	0	0
T25	7704	2	0	0
T33	22365	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T41	528	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	2	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2741	0	0
T12	63037	64	0	0
T25	7704	26	0	0
T33	22365	0	0	0
T38	0	29	0	0
T39	0	136	0	0
T41	528	28	0	0
T42	0	54	0	0
T43	0	54	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	25	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	27	0	0
T194	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231290	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	3	0	0
T77	803	0	0	0
T98	0	1	0	0
T123	130652	0	0	0
T126	450	0	0	0
T127	20791	0	0	0
T128	8774	0	0	0
T129	625	0	0	0
T150	34147	1	0	0
T183	0	1	0	0
T195	542	0	0	0
T196	492	0	0	0
T197	11783	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	3498	0	0
T12	63037	95	0	0
T25	7704	40	0	0
T33	22365	0	0	0
T38	0	72	0	0
T39	0	78	0	0
T41	528	53	0	0
T42	0	173	0	0
T43	0	63	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	82	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	38	0	0
T194	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	44	0	0
T12	63037	2	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	2	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	1	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7185022	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7187360	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T12	63037	2	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	1	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	47	0	0
T12	63037	2	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	2	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	44	0	0
T12	63037	2	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	2	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	1	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	44	0	0
T12	63037	2	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	2	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	1	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	3426	0	0
T12	63037	92	0	0
T25	7704	38	0	0
T33	22365	0	0	0
T38	0	70	0	0
T39	0	75	0	0
T41	528	51	0	0
T42	0	171	0	0
T43	0	61	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	79	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	36	0	0
T194	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6355	0	0
T1	16990	27	0	0
T2	837	0	0	0
T3	11228	26	0	0
T5	11957	0	0	0
T6	28425	33	0	0
T13	493	8	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	2	0	0
T22	0	6	0	0
T23	0	5	0	0
T24	0	4	0	0
T27	0	24	0	0
T61	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	15	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T39	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T98	0	1	0	0
T137	0	2	0	0
T150	0	2	0	0
T154	0	1	0	0
T169	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0