Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T13,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T13,T3
1	1	Covered	T1,T13,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T25,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T25,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T25,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T41
1	0	Covered	T1,T13,T3
1	1	Covered	T12,T25,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T41
0	1	Covered	T200
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T25,T41
0	1	Covered	T12,T25,T43
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T25,T41
1	-	Covered	T12,T25,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T25,T41
DetectSt	168	Covered	T12,T25,T41
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T25,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T25,T41
DebounceSt->IdleSt	163	Covered	T44,T69,T137
DetectSt->IdleSt	186	Covered	T200
DetectSt->StableSt	191	Covered	T12,T25,T41
IdleSt->DebounceSt	148	Covered	T12,T25,T41
StableSt->IdleSt	206	Covered	T12,T25,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T25,T41
0	1	Covered	T12,T25,T41
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T25,T41
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T25,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T25,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T137
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T25,T41
DetectSt	-	-	-	-	1	-	-	Covered	T200
DetectSt	-	-	-	-	0	1	-	Covered	T12,T25,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T25,T43
StableSt	-	-	-	-	-	-	0	Covered	T12,T25,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	107	0	0
CntIncr_A	7891491	3119	0	0
CntNoWrap_A	7891491	7231279	0	0
DetectStDropOut_A	7891491	1	0	0
DetectedOut_A	7891491	5674	0	0
DetectedPulseOut_A	7891491	51	0	0
DisabledIdleSt_A	7891491	7214140	0	0
DisabledNoDetection_A	7891491	7216490	0	0
EnterDebounceSt_A	7891491	56	0	0
EnterDetectSt_A	7891491	52	0	0
EnterStableSt_A	7891491	51	0	0
PulseIsPulse_A	7891491	51	0	0
StayInStableSt	7891491	5603	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	107	0	0
T12	63037	4	0	0
T25	7704	4	0	0
T33	22365	0	0	0
T39	0	2	0	0
T41	528	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	2	0	0
T46	0	4	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	3119	0	0
T12	63037	111	0	0
T25	7704	52	0	0
T33	22365	0	0	0
T39	0	68	0	0
T41	528	28	0	0
T42	0	54	0	0
T43	0	54	0	0
T44	0	38	0	0
T45	0	62	0	0
T46	0	34	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	24	0	0
T85	568	0	0	0
T86	735	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231279	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1	0	0
T200	809	1	0	0
T201	731	0	0	0
T202	585	0	0	0
T203	430	0	0	0
T204	502	0	0	0
T205	502	0	0	0
T206	442	0	0	0
T207	12065	0	0	0
T208	504	0	0	0
T209	1375	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	5674	0	0
T12	63037	511	0	0
T25	7704	78	0	0
T33	22365	0	0	0
T35	0	203	0	0
T39	0	215	0	0
T40	0	39	0	0
T41	528	90	0	0
T42	0	254	0	0
T43	0	217	0	0
T45	0	130	0	0
T46	0	105	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	51	0	0
T12	63037	2	0	0
T25	7704	2	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7214140	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7216490	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	56	0	0
T12	63037	2	0	0
T25	7704	2	0	0
T33	22365	0	0	0
T39	0	1	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	52	0	0
T12	63037	2	0	0
T25	7704	2	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	51	0	0
T12	63037	2	0	0
T25	7704	2	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	51	0	0
T12	63037	2	0	0
T25	7704	2	0	0
T33	22365	0	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	528	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	5603	0	0
T12	63037	509	0	0
T25	7704	75	0	0
T33	22365	0	0	0
T35	0	201	0	0
T39	0	214	0	0
T40	0	38	0	0
T41	528	88	0	0
T42	0	253	0	0
T43	0	216	0	0
T45	0	128	0	0
T46	0	102	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	30	0	0
T12	63037	2	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	528	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T130	0	1	0	0
T137	0	2	0	0
T150	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T37,T39,T69

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T37,T39,T69

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T37,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T41
1	0	Covered	T1,T13,T3
1	1	Covered	T37,T39,T69

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T39,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T39,T40
0	1	Covered	T137,T182,T168
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T37,T39,T40
1	-	Covered	T137,T182,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T37,T39,T69
DetectSt	168	Covered	T37,T39,T40
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T37,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T37,T39,T40
DebounceSt->IdleSt	163	Covered	T69
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T37,T39,T40
IdleSt->DebounceSt	148	Covered	T37,T39,T69
StableSt->IdleSt	206	Covered	T37,T39,T150

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T37,T39,T69
0	1	Covered	T37,T39,T69
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T37,T39,T40
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T37,T39,T69
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T37,T39,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T37,T39,T69
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T37,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T137,T57,T182
StableSt	-	-	-	-	-	-	0	Covered	T37,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	63	0	0
CntIncr_A	7891491	1977	0	0
CntNoWrap_A	7891491	7231323	0	0
DetectStDropOut_A	7891491	0	0	0
DetectedOut_A	7891491	1793	0	0
DetectedPulseOut_A	7891491	31	0	0
DisabledIdleSt_A	7891491	7114798	0	0
DisabledNoDetection_A	7891491	7117152	0	0
EnterDebounceSt_A	7891491	32	0	0
EnterDetectSt_A	7891491	31	0	0
EnterStableSt_A	7891491	31	0	0
PulseIsPulse_A	7891491	31	0	0
StayInStableSt	7891491	1747	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7891491	6366	0	0
gen_low_level_sva.LowLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	63	0	0
T34	20072	0	0	0
T37	18200	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T45	601	0	0	0
T57	0	2	0	0
T65	7287	0	0	0
T69	0	1	0	0
T80	0	2	0	0
T137	0	4	0	0
T150	0	2	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T179	502	0	0	0
T180	38159	0	0	0
T181	0	2	0	0
T182	0	2	0	0
T210	500	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1977	0	0
T34	20072	0	0	0
T37	18200	85	0	0
T39	0	68	0	0
T40	0	84	0	0
T45	601	0	0	0
T57	0	32	0	0
T65	7287	0	0	0
T69	0	25	0	0
T80	0	90	0	0
T137	0	34	0	0
T150	0	47	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T179	502	0	0	0
T180	38159	0	0	0
T181	0	78	0	0
T182	0	41	0	0
T210	500	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231323	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1793	0	0
T34	20072	0	0	0
T37	18200	41	0	0
T39	0	37	0	0
T40	0	113	0	0
T45	601	0	0	0
T57	0	5	0	0
T65	7287	0	0	0
T80	0	44	0	0
T137	0	162	0	0
T150	0	90	0	0
T168	0	158	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T179	502	0	0	0
T180	38159	0	0	0
T181	0	40	0	0
T182	0	32	0	0
T210	500	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	31	0	0
T34	20072	0	0	0
T37	18200	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	601	0	0	0
T57	0	1	0	0
T65	7287	0	0	0
T80	0	1	0	0
T137	0	2	0	0
T150	0	1	0	0
T168	0	2	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T179	502	0	0	0
T180	38159	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T210	500	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7114798	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7117152	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	32	0	0
T34	20072	0	0	0
T37	18200	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	601	0	0	0
T57	0	1	0	0
T65	7287	0	0	0
T69	0	1	0	0
T80	0	1	0	0
T137	0	2	0	0
T150	0	1	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T179	502	0	0	0
T180	38159	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T210	500	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	31	0	0
T34	20072	0	0	0
T37	18200	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	601	0	0	0
T57	0	1	0	0
T65	7287	0	0	0
T80	0	1	0	0
T137	0	2	0	0
T150	0	1	0	0
T168	0	2	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T179	502	0	0	0
T180	38159	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T210	500	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	31	0	0
T34	20072	0	0	0
T37	18200	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	601	0	0	0
T57	0	1	0	0
T65	7287	0	0	0
T80	0	1	0	0
T137	0	2	0	0
T150	0	1	0	0
T168	0	2	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T179	502	0	0	0
T180	38159	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T210	500	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	31	0	0
T34	20072	0	0	0
T37	18200	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	601	0	0	0
T57	0	1	0	0
T65	7287	0	0	0
T80	0	1	0	0
T137	0	2	0	0
T150	0	1	0	0
T168	0	2	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T179	502	0	0	0
T180	38159	0	0	0
T181	0	1	0	0
T182	0	1	0	0
T210	500	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1747	0	0
T34	20072	0	0	0
T37	18200	39	0	0
T39	0	35	0	0
T40	0	111	0	0
T45	601	0	0	0
T57	0	4	0	0
T65	7287	0	0	0
T80	0	42	0	0
T137	0	159	0	0
T150	0	88	0	0
T168	0	155	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0
T179	502	0	0	0
T180	38159	0	0	0
T181	0	38	0	0
T182	0	31	0	0
T210	500	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6366	0	0
T1	16990	29	0	0
T2	837	0	0	0
T3	11228	28	0	0
T5	11957	0	0	0
T6	28425	34	0	0
T13	493	8	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	3	0	0
T22	0	5	0	0
T23	0	5	0	0
T24	0	3	0	0
T27	0	22	0	0
T61	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	15	0	0
T99	0	3	0	0
T137	12420	1	0	0
T138	0	1	0	0
T153	0	1	0	0
T168	0	1	0	0
T181	639	0	0	0
T182	0	1	0	0
T198	0	2	0	0
T199	0	1	0	0
T200	0	1	0	0
T211	0	1	0	0
T212	493	0	0	0
T213	17606	0	0	0
T214	502	0	0	0
T215	90636	0	0	0
T216	1370	0	0	0
T217	3950	0	0	0
T218	14867	0	0	0
T219	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T13,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T1,T13,T3
1	1	Covered	T1,T13,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T8,T12,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T8,T12,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T8,T12,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T25
1	0	Covered	T1,T13,T3
1	1	Covered	T8,T12,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T25
0	1	Covered	T99
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T25
0	1	Covered	T12,T25,T44
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T12,T25
1	-	Covered	T12,T25,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T12,T25
DetectSt	168	Covered	T8,T12,T25
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T8,T12,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T12,T25
DebounceSt->IdleSt	163	Covered	T69,T73,T220
DetectSt->IdleSt	186	Covered	T99
DetectSt->StableSt	191	Covered	T8,T12,T25
IdleSt->DebounceSt	148	Covered	T8,T12,T25
StableSt->IdleSt	206	Covered	T8,T12,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T12,T25
0	1	Covered	T8,T12,T25
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T12,T25
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T12,T25
IdleSt	0	-	-	-	-	-	-	Covered	T1,T13,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T12,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T220
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T12,T25
DetectSt	-	-	-	-	1	-	-	Covered	T99
DetectSt	-	-	-	-	0	1	-	Covered	T8,T12,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T25,T44
StableSt	-	-	-	-	-	-	0	Covered	T8,T12,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	123	0	0
CntIncr_A	7891491	131658	0	0
CntNoWrap_A	7891491	7231263	0	0
DetectStDropOut_A	7891491	1	0	0
DetectedOut_A	7891491	69725	0	0
DetectedPulseOut_A	7891491	59	0	0
DisabledIdleSt_A	7891491	6884635	0	0
DisabledNoDetection_A	7891491	6886985	0	0
EnterDebounceSt_A	7891491	63	0	0
EnterDetectSt_A	7891491	60	0	0
EnterStableSt_A	7891491	59	0	0
PulseIsPulse_A	7891491	59	0	0
StayInStableSt	7891491	69644	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	123	0	0
T8	39472	2	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	6	0	0
T25	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T69	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	131658	0	0
T8	39472	13	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	190	0	0
T25	0	26	0	0
T37	0	85	0	0
T38	0	58	0	0
T42	0	54	0	0
T43	0	54	0	0
T44	0	38	0	0
T46	0	17	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T69	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231263	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1	0	0
T99	87716	1	0	0
T100	20229	0	0	0
T221	492	0	0	0
T222	764	0	0	0
T223	1531	0	0	0
T224	760	0	0	0
T225	439	0	0	0
T226	696	0	0	0
T227	686	0	0	0
T228	25650	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	69725	0	0
T8	39472	61	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	474	0	0
T25	0	75	0	0
T37	0	39	0	0
T38	0	135	0	0
T42	0	174	0	0
T43	0	62	0	0
T44	0	79	0	0
T46	0	127	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T140	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	59	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	3	0	0
T25	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6884635	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6886985	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	63	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	3	0	0
T25	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	60	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	3	0	0
T25	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	59	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	3	0	0
T25	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	59	0	0
T8	39472	1	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	3	0	0
T25	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	69644	0	0
T8	39472	59	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	63037	470	0	0
T25	0	74	0	0
T37	0	38	0	0
T38	0	132	0	0
T42	0	172	0	0
T43	0	61	0	0
T44	0	78	0	0
T46	0	125	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T140	0	56	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	36	0	0
T12	63037	2	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T41	528	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	1	0	0
T140	0	1	0	0
T150	0	4	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T13,T3
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T3
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T25,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T25,T37,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T25,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T25,T37
1	0	Covered	T1,T13,T3
1	1	Covered	T25,T37,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T37,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T37,T38
0	1	Covered	T38,T150,T137
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T37,T38
1	-	Covered	T38,T150,T137

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T37,T38
DetectSt	168	Covered	T25,T37,T38
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T25,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T37,T38
DebounceSt->IdleSt	163	Covered	T69,T98
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T25,T37,T38
IdleSt->DebounceSt	148	Covered	T25,T37,T38
StableSt->IdleSt	206	Covered	T25,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T37,T38
0	1	Covered	T25,T37,T38
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T37,T38
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T37,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T98
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T37,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T25,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T150,T137
StableSt	-	-	-	-	-	-	0	Covered	T25,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	68	0	0
CntIncr_A	7891491	2364	0	0
CntNoWrap_A	7891491	7231318	0	0
DetectStDropOut_A	7891491	0	0	0
DetectedOut_A	7891491	2441	0	0
DetectedPulseOut_A	7891491	33	0	0
DisabledIdleSt_A	7891491	7132874	0	0
DisabledNoDetection_A	7891491	7135230	0	0
EnterDebounceSt_A	7891491	35	0	0
EnterDetectSt_A	7891491	33	0	0
EnterStableSt_A	7891491	33	0	0
PulseIsPulse_A	7891491	33	0	0
StayInStableSt	7891491	2389	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7891491	6294	0	0
gen_low_level_sva.LowLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	68	0	0
T25	7704	2	0	0
T33	22365	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	2	0	0
T41	528	0	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T73	0	2	0	0
T79	0	2	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	2	0	0
T150	0	8	0	0
T170	0	4	0	0
T229	417	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2364	0	0
T25	7704	26	0	0
T33	22365	0	0	0
T37	0	85	0	0
T38	0	29	0	0
T40	0	84	0	0
T41	528	0	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	26	0	0
T73	0	23	0	0
T79	0	43	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	17	0	0
T150	0	371	0	0
T170	0	188	0	0
T229	417	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231318	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2441	0	0
T25	7704	40	0	0
T33	22365	0	0	0
T37	0	41	0	0
T38	0	2	0	0
T40	0	49	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	4	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	126	0	0
T79	0	38	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	9	0	0
T150	0	708	0	0
T170	0	49	0	0
T229	417	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	33	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	1	0	0
T150	0	4	0	0
T170	0	2	0	0
T229	417	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7132874	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7135230	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	35	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T73	0	1	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	1	0	0
T150	0	4	0	0
T170	0	2	0	0
T229	417	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	33	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	1	0	0
T150	0	4	0	0
T170	0	2	0	0
T229	417	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	33	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	1	0	0
T150	0	4	0	0
T170	0	2	0	0
T229	417	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	33	0	0
T25	7704	1	0	0
T33	22365	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	1	0	0
T150	0	4	0	0
T170	0	2	0	0
T229	417	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2389	0	0
T25	7704	38	0	0
T33	22365	0	0	0
T37	0	39	0	0
T38	0	1	0	0
T40	0	47	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	3	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	124	0	0
T79	0	36	0	0
T85	568	0	0	0
T86	735	0	0	0
T137	0	8	0	0
T150	0	702	0	0
T170	0	46	0	0
T229	417	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6294	0	0
T1	16990	24	0	0
T2	837	0	0	0
T3	11228	32	0	0
T5	11957	0	0	0
T6	28425	31	0	0
T13	493	7	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	2	0	0
T22	0	7	0	0
T23	0	5	0	0
T24	0	5	0	0
T27	0	24	0	0
T61	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	13	0	0
T38	5298	1	0	0
T137	0	1	0	0
T150	0	2	0	0
T152	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T184	0	1	0	0
T198	0	1	0	0
T230	758	0	0	0
T231	16375	0	0	0
T232	21200	0	0	0
T233	3209	0	0	0
T234	2843	0	0	0
T235	4528	0	0	0
T236	2016	0	0	0
T237	523	0	0	0
T238	10431	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T44,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T44,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T44,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T44,T43
1	0	Covered	T4,T1,T5
1	1	Covered	T12,T44,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T44,T43
0	1	Covered	T80,T239
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T44,T43
0	1	Covered	T12,T44,T43
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T44,T43
1	-	Covered	T12,T44,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T44,T43
DetectSt	168	Covered	T12,T44,T43
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T44,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T44,T43
DebounceSt->IdleSt	163	Covered	T69
DetectSt->IdleSt	186	Covered	T80,T239
DetectSt->StableSt	191	Covered	T12,T44,T43
IdleSt->DebounceSt	148	Covered	T12,T44,T43
StableSt->IdleSt	206	Covered	T12,T44,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T44,T43
0	1	Covered	T12,T44,T43
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T44,T43
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T44,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T44,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T44,T43
DetectSt	-	-	-	-	1	-	-	Covered	T80,T239
DetectSt	-	-	-	-	0	1	-	Covered	T12,T44,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T44,T43
StableSt	-	-	-	-	-	-	0	Covered	T12,T44,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	115	0	0
CntIncr_A	7891491	67327	0	0
CntNoWrap_A	7891491	7231271	0	0
DetectStDropOut_A	7891491	2	0	0
DetectedOut_A	7891491	4632	0	0
DetectedPulseOut_A	7891491	55	0	0
DisabledIdleSt_A	7891491	6958486	0	0
DisabledNoDetection_A	7891491	6960839	0	0
EnterDebounceSt_A	7891491	58	0	0
EnterDetectSt_A	7891491	57	0	0
EnterStableSt_A	7891491	55	0	0
PulseIsPulse_A	7891491	55	0	0
StayInStableSt	7891491	4557	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	115	0	0
T12	63037	8	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	528	0	0	0
T42	0	2	0	0
T43	0	6	0	0
T44	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T79	0	2	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	67327	0	0
T12	63037	269	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	29	0	0
T39	0	136	0	0
T40	0	84	0	0
T41	528	0	0	0
T42	0	54	0	0
T43	0	162	0	0
T44	0	38	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	25	0	0
T79	0	43	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231271	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2	0	0
T80	941	1	0	0
T134	86682	0	0	0
T239	0	1	0	0
T240	6719	0	0	0
T241	402	0	0	0
T242	505	0	0	0
T243	916	0	0	0
T244	422	0	0	0
T245	402	0	0	0
T246	416	0	0	0
T247	24339	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	4632	0	0
T12	63037	241	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	95	0	0
T39	0	77	0	0
T40	0	125	0	0
T41	528	0	0	0
T42	0	173	0	0
T43	0	230	0	0
T44	0	98	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	38	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	184	0	0
T157	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	55	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	528	0	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6958486	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6960839	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	58	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	528	0	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	57	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	528	0	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	55	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	528	0	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	55	0	0
T12	63037	4	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	528	0	0	0
T42	0	1	0	0
T43	0	3	0	0
T44	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	4557	0	0
T12	63037	236	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	94	0	0
T39	0	75	0	0
T40	0	124	0	0
T41	528	0	0	0
T42	0	171	0	0
T43	0	226	0	0
T44	0	97	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T79	0	36	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	183	0	0
T157	0	78	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	34	0	0
T12	63037	3	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	528	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T137	0	2	0	0
T150	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T43,T69

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T12,T43,T69

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T12,T43,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T25,T43
1	0	Covered	T4,T1,T5
1	1	Covered	T12,T43,T69

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T35,T36
0	1	Covered	T43,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T35,T36
0	1	Covered	T35,T150,T170
1	0	Covered	T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T35,T36
1	-	Covered	T35,T150,T170

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T43,T69
DetectSt	168	Covered	T12,T43,T35
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T12,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T43,T35
DebounceSt->IdleSt	163	Covered	T43,T69,T137
DetectSt->IdleSt	186	Covered	T43,T73
DetectSt->StableSt	191	Covered	T12,T35,T36
IdleSt->DebounceSt	148	Covered	T12,T43,T69
StableSt->IdleSt	206	Covered	T12,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T43,T69
0	1	Covered	T12,T43,T69
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T43,T35
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T43,T69
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T43,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T137,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T43,T69
DetectSt	-	-	-	-	1	-	-	Covered	T43,T73
DetectSt	-	-	-	-	0	1	-	Covered	T12,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T150,T170
StableSt	-	-	-	-	-	-	0	Covered	T12,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	73	0	0
CntIncr_A	7891491	2276	0	0
CntNoWrap_A	7891491	7231313	0	0
DetectStDropOut_A	7891491	2	0	0
DetectedOut_A	7891491	2715	0	0
DetectedPulseOut_A	7891491	32	0	0
DisabledIdleSt_A	7891491	7118464	0	0
DisabledNoDetection_A	7891491	7120814	0	0
EnterDebounceSt_A	7891491	39	0	0
EnterDetectSt_A	7891491	34	0	0
EnterStableSt_A	7891491	32	0	0
PulseIsPulse_A	7891491	32	0	0
StayInStableSt	7891491	2666	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7891491	6892	0	0
gen_low_level_sva.LowLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	73	0	0
T12	63037	2	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T41	528	0	0	0
T43	0	3	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T73	0	2	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	2	0	0
T137	0	5	0	0
T150	0	8	0	0
T170	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2276	0	0
T12	63037	32	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	43	0	0
T36	0	87	0	0
T41	528	0	0	0
T43	0	108	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	26	0	0
T73	0	23	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	94	0	0
T137	0	121	0	0
T150	0	327	0	0
T170	0	188	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7231313	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2	0	0
T34	20072	0	0	0
T37	18200	0	0	0
T42	4214	0	0	0
T43	3042	1	0	0
T45	601	0	0	0
T65	7287	0	0	0
T73	0	1	0	0
T171	422	0	0	0
T172	776	0	0	0
T173	760	0	0	0
T174	518	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2715	0	0
T12	63037	161	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	34	0	0
T36	0	38	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	4	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T82	0	40	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	41	0	0
T137	0	209	0	0
T150	0	655	0	0
T170	0	187	0	0
T182	0	198	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	32	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T82	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T137	0	2	0	0
T150	0	4	0	0
T170	0	2	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7118464	0	0
T1	16990	16578	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7120814	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	39	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T41	528	0	0	0
T43	0	2	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T69	0	1	0	0
T73	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T137	0	3	0	0
T150	0	4	0	0
T170	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	34	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T41	528	0	0	0
T43	0	1	0	0
T51	5071	0	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T73	0	1	0	0
T82	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T137	0	2	0	0
T150	0	4	0	0
T170	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	32	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T82	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T137	0	2	0	0
T150	0	4	0	0
T170	0	2	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	32	0	0
T12	63037	1	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	1	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T82	0	1	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	1	0	0
T137	0	2	0	0
T150	0	4	0	0
T170	0	2	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2666	0	0
T12	63037	159	0	0
T25	7704	0	0	0
T33	22365	0	0	0
T35	0	33	0	0
T36	0	36	0	0
T41	528	0	0	0
T51	5071	0	0	0
T57	0	3	0	0
T59	2455	0	0	0
T63	3020	0	0	0
T64	526	0	0	0
T82	0	38	0	0
T85	568	0	0	0
T86	735	0	0	0
T111	0	39	0	0
T137	0	205	0	0
T150	0	649	0	0
T170	0	184	0	0
T182	0	196	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6892	0	0
T1	16990	27	0	0
T2	837	4	0	0
T3	11228	31	0	0
T4	5334	3	0	0
T5	11957	3	0	0
T6	0	28	0	0
T13	493	6	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	1	0	0
T22	0	6	0	0
T23	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	14	0	0
T35	731	1	0	0
T40	2450	0	0	0
T98	0	1	0	0
T118	1090	0	0	0
T150	0	2	0	0
T153	0	1	0	0
T156	0	2	0	0
T170	0	1	0	0
T185	0	1	0	0
T190	8945	0	0	0
T191	409	0	0	0
T224	0	1	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	523	0	0	0
T251	504	0	0	0
T252	6550	0	0	0
T253	411	0	0	0
T254	445	0	0	0