Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T27
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T27
0	1	Covered	T27,T9,T51
1	0	Covered	T3,T9,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T47,T33
0	1	Covered	T1,T47,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T47,T33
1	-	Covered	T1,T47,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T27
DetectSt	168	Covered	T1,T3,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T47,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T27
DebounceSt->IdleSt	163	Covered	T69,T255,T57
DetectSt->IdleSt	186	Covered	T3,T27,T9
DetectSt->StableSt	191	Covered	T1,T47,T33
IdleSt->DebounceSt	148	Covered	T1,T3,T27
StableSt->IdleSt	206	Covered	T1,T47,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T27
0	1	Covered	T1,T3,T27
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T255,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T27
DetectSt	-	-	-	-	1	-	-	Covered	T3,T27,T9
DetectSt	-	-	-	-	0	1	-	Covered	T1,T47,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T27
StableSt	-	-	-	-	-	-	1	Covered	T1,T47,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T47,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	3041	0	0
CntIncr_A	7891491	104137	0	0
CntNoWrap_A	7891491	7228345	0	0
DetectStDropOut_A	7891491	462	0	0
DetectedOut_A	7891491	71779	0	0
DetectedPulseOut_A	7891491	864	0	0
DisabledIdleSt_A	7891491	6790493	0	0
DisabledNoDetection_A	7891491	6792717	0	0
EnterDebounceSt_A	7891491	1534	0	0
EnterDetectSt_A	7891491	1509	0	0
EnterStableSt_A	7891491	864	0	0
PulseIsPulse_A	7891491	864	0	0
StayInStableSt	7891491	70831	0	0
gen_high_event_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	779	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	3041	0	0
T1	16990	22	0	0
T2	837	0	0	0
T3	11228	2	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	44	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	44	0	0
T33	0	30	0	0
T47	0	48	0	0
T51	0	60	0	0
T53	0	46	0	0
T65	0	12	0	0
T66	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	104137	0	0
T1	16990	847	0	0
T2	837	0	0	0
T3	11228	57	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	1729	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	1209	0	0
T33	0	1155	0	0
T47	0	1272	0	0
T51	0	1467	0	0
T53	0	1486	0	0
T65	0	306	0	0
T66	0	1601	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7228345	0	0
T1	16990	16556	0	0
T2	837	436	0	0
T3	11228	10810	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	462	0	0
T7	13230	0	0	0
T8	39472	0	0	0
T9	0	6	0	0
T24	502	0	0	0
T26	741	0	0	0
T27	5366	22	0	0
T32	1111	0	0	0
T48	1667	0	0	0
T49	654	0	0	0
T51	0	30	0	0
T53	0	7	0	0
T58	603	0	0	0
T62	496	0	0	0
T66	0	25	0	0
T87	0	13	0	0
T88	0	9	0	0
T256	0	7	0	0
T257	0	2	0	0
T258	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	71779	0	0
T1	16990	1010	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	1140	0	0
T47	0	1509	0	0
T65	0	110	0	0
T74	0	2047	0	0
T75	0	5063	0	0
T117	0	1261	0	0
T231	0	411	0	0
T238	0	96	0	0
T259	0	946	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	864	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	15	0	0
T47	0	24	0	0
T65	0	6	0	0
T74	0	29	0	0
T75	0	13	0	0
T117	0	7	0	0
T231	0	8	0	0
T238	0	5	0	0
T259	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6790493	0	0
T1	16990	9345	0	0
T2	837	436	0	0
T3	11228	7799	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6792717	0	0
T1	16990	9347	0	0
T2	837	437	0	0
T3	11228	7802	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1534	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	1	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	22	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	22	0	0
T33	0	15	0	0
T47	0	24	0	0
T51	0	30	0	0
T53	0	23	0	0
T65	0	6	0	0
T66	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1509	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	1	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	22	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	22	0	0
T33	0	15	0	0
T47	0	24	0	0
T51	0	30	0	0
T53	0	23	0	0
T65	0	6	0	0
T66	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	864	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	15	0	0
T47	0	24	0	0
T65	0	6	0	0
T74	0	29	0	0
T75	0	13	0	0
T117	0	7	0	0
T231	0	8	0	0
T238	0	5	0	0
T259	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	864	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	15	0	0
T47	0	24	0	0
T65	0	6	0	0
T74	0	29	0	0
T75	0	13	0	0
T117	0	7	0	0
T231	0	8	0	0
T238	0	5	0	0
T259	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	70831	0	0
T1	16990	998	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	1123	0	0
T47	0	1485	0	0
T65	0	104	0	0
T74	0	2018	0	0
T75	0	5047	0	0
T117	0	1254	0	0
T231	0	402	0	0
T238	0	91	0	0
T259	0	929	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	779	0	0
T1	16990	10	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	13	0	0
T47	0	24	0	0
T65	0	6	0	0
T74	0	29	0	0
T75	0	10	0	0
T117	0	7	0	0
T231	0	7	0	0
T238	0	5	0	0
T259	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T89,T90,T91
1	0	Covered	T69,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T7
1	-	Covered	T1,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T7
DetectSt	168	Covered	T1,T6,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T7
DebounceSt->IdleSt	163	Covered	T8,T12,T59
DetectSt->IdleSt	186	Covered	T69,T89,T90
DetectSt->StableSt	191	Covered	T1,T6,T7
IdleSt->DebounceSt	148	Covered	T1,T6,T7
StableSt->IdleSt	206	Covered	T1,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T12,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T69,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	947	0	0
CntIncr_A	7891491	53576	0	0
CntNoWrap_A	7891491	7230439	0	0
DetectStDropOut_A	7891491	49	0	0
DetectedOut_A	7891491	13527	0	0
DetectedPulseOut_A	7891491	382	0	0
DisabledIdleSt_A	7891491	6841267	0	0
DisabledNoDetection_A	7891491	6842920	0	0
EnterDebounceSt_A	7891491	514	0	0
EnterDetectSt_A	7891491	435	0	0
EnterStableSt_A	7891491	381	0	0
PulseIsPulse_A	7891491	381	0	0
StayInStableSt	7891491	13115	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	349	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	947	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	6	0	0
T7	0	2	0	0
T8	0	7	0	0
T12	0	7	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	2	0	0
T33	0	4	0	0
T52	0	1	0	0
T59	0	1	0	0
T84	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	53576	0	0
T1	16990	64	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	152	0	0
T7	0	74	0	0
T8	0	378	0	0
T12	0	362	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	25	0	0
T33	0	104	0	0
T52	0	20	0	0
T59	0	20	0	0
T84	0	880	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7230439	0	0
T1	16990	16576	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	49	0	0
T72	72847	0	0	0
T89	18364	2	0	0
T90	0	3	0	0
T91	0	2	0	0
T92	0	4	0	0
T94	0	7	0	0
T95	0	10	0	0
T98	0	1	0	0
T99	0	10	0	0
T100	0	6	0	0
T101	0	3	0	0
T102	525	0	0	0
T103	11132	0	0	0
T104	405	0	0	0
T105	680	0	0	0
T106	424	0	0	0
T107	402	0	0	0
T108	748	0	0	0
T109	658	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	13527	0	0
T1	16990	57	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	16	0	0
T7	0	13	0	0
T8	0	78	0	0
T12	0	26	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	3	0	0
T33	0	129	0	0
T34	0	64	0	0
T37	0	57	0	0
T84	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	382	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	1	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	4	0	0
T84	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6841267	0	0
T1	16990	15569	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6842920	0	0
T1	16990	15572	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	514	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	1	0	0
T8	0	5	0	0
T12	0	4	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T33	0	2	0	0
T52	0	1	0	0
T59	0	1	0	0
T84	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	435	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	1	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	4	0	0
T84	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	381	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	1	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	4	0	0
T84	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	381	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	1	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	4	0	0
T84	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	13115	0	0
T1	16990	56	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	13	0	0
T7	0	12	0	0
T8	0	76	0	0
T12	0	23	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	2	0	0
T33	0	127	0	0
T34	0	62	0	0
T37	0	53	0	0
T84	0	33	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	349	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	1	0	0
T8	0	2	0	0
T12	0	3	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T25	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	4	0	0
T84	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T27
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T27
0	1	Covered	T27,T47,T51
1	0	Covered	T47,T117,T259

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
1	0	Covered	T74,T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T27
DetectSt	168	Covered	T1,T3,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T27
DebounceSt->IdleSt	163	Covered	T69,T255,T57
DetectSt->IdleSt	186	Covered	T27,T47,T51
DetectSt->StableSt	191	Covered	T1,T3,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T27
StableSt->IdleSt	206	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T27
0	1	Covered	T1,T3,T27
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T255,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T27
DetectSt	-	-	-	-	1	-	-	Covered	T27,T47,T51
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T27
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	2690	0	0
CntIncr_A	7891491	88685	0	0
CntNoWrap_A	7891491	7228696	0	0
DetectStDropOut_A	7891491	357	0	0
DetectedOut_A	7891491	65924	0	0
DetectedPulseOut_A	7891491	763	0	0
DisabledIdleSt_A	7891491	6791189	0	0
DisabledNoDetection_A	7891491	6793420	0	0
EnterDebounceSt_A	7891491	1358	0	0
EnterDetectSt_A	7891491	1334	0	0
EnterStableSt_A	7891491	763	0	0
PulseIsPulse_A	7891491	763	0	0
StayInStableSt	7891491	65084	0	0
gen_high_event_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	656	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2690	0	0
T1	16990	24	0	0
T2	837	0	0	0
T3	11228	50	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	12	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	20	0	0
T33	0	60	0	0
T47	0	48	0	0
T51	0	24	0	0
T53	0	44	0	0
T65	0	32	0	0
T66	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	88685	0	0
T1	16990	900	0	0
T2	837	0	0	0
T3	11228	1050	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	420	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	545	0	0
T33	0	2130	0	0
T47	0	1450	0	0
T51	0	578	0	0
T53	0	924	0	0
T65	0	1072	0	0
T66	0	1663	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7228696	0	0
T1	16990	16554	0	0
T2	837	436	0	0
T3	11228	10762	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	357	0	0
T7	13230	0	0	0
T8	39472	0	0	0
T24	502	0	0	0
T26	741	0	0	0
T27	5366	10	0	0
T32	1111	0	0	0
T47	0	13	0	0
T48	1667	0	0	0
T49	654	0	0	0
T51	0	12	0	0
T58	603	0	0	0
T62	496	0	0	0
T66	0	26	0	0
T87	0	16	0	0
T88	0	6	0	0
T117	0	12	0	0
T256	0	10	0	0
T259	0	2	0	0
T260	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	65924	0	0
T1	16990	1726	0	0
T2	837	0	0	0
T3	11228	1647	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	60	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	2601	0	0
T53	0	2076	0	0
T65	0	43	0	0
T74	0	958	0	0
T75	0	4621	0	0
T231	0	222	0	0
T238	0	482	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	763	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	25	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	6	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	30	0	0
T53	0	22	0	0
T65	0	16	0	0
T74	0	29	0	0
T75	0	12	0	0
T231	0	12	0	0
T238	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6791189	0	0
T1	16990	8708	0	0
T2	837	436	0	0
T3	11228	6502	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6793420	0	0
T1	16990	8711	0	0
T2	837	437	0	0
T3	11228	6502	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1358	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	25	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	6	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	10	0	0
T33	0	30	0	0
T47	0	24	0	0
T51	0	12	0	0
T53	0	22	0	0
T65	0	16	0	0
T66	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1334	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	25	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	6	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	10	0	0
T33	0	30	0	0
T47	0	24	0	0
T51	0	12	0	0
T53	0	22	0	0
T65	0	16	0	0
T66	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	763	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	25	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	6	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	30	0	0
T53	0	22	0	0
T65	0	16	0	0
T74	0	29	0	0
T75	0	12	0	0
T231	0	12	0	0
T238	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	763	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	25	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	6	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	30	0	0
T53	0	22	0	0
T65	0	16	0	0
T74	0	29	0	0
T75	0	12	0	0
T231	0	12	0	0
T238	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	65084	0	0
T1	16990	1714	0	0
T2	837	0	0	0
T3	11228	1620	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	54	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	2567	0	0
T53	0	2048	0	0
T65	0	27	0	0
T74	0	929	0	0
T75	0	4607	0	0
T231	0	210	0	0
T238	0	472	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	656	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	23	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	6	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	26	0	0
T53	0	16	0	0
T65	0	16	0	0
T75	0	10	0	0
T76	0	9	0	0
T231	0	12	0	0
T238	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T7,T10,T261
1	0	Covered	T69,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
1	0	Covered	T69,T262

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T6
1	-	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T7,T33,T180
DetectSt->IdleSt	186	Covered	T7,T10,T261
DetectSt->StableSt	191	Covered	T1,T3,T6
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T33,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T7,T10,T261
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	923	0	0
CntIncr_A	7891491	52904	0	0
CntNoWrap_A	7891491	7230463	0	0
DetectStDropOut_A	7891491	50	0	0
DetectedOut_A	7891491	16777	0	0
DetectedPulseOut_A	7891491	374	0	0
DisabledIdleSt_A	7891491	6833250	0	0
DisabledNoDetection_A	7891491	6834924	0	0
EnterDebounceSt_A	7891491	496	0	0
EnterDetectSt_A	7891491	427	0	0
EnterStableSt_A	7891491	374	0	0
PulseIsPulse_A	7891491	374	0	0
StayInStableSt	7891491	16375	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	343	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	923	0	0
T1	16990	4	0	0
T2	837	0	0	0
T3	11228	2	0	0
T5	11957	0	0	0
T6	28425	16	0	0
T7	0	26	0	0
T8	0	2	0	0
T10	0	6	0	0
T12	0	10	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	9	0	0
T53	0	12	0	0
T84	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	52904	0	0
T1	16990	140	0	0
T2	837	0	0	0
T3	11228	71	0	0
T5	11957	0	0	0
T6	28425	624	0	0
T7	0	1144	0	0
T8	0	193	0	0
T10	0	478	0	0
T12	0	361	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	205	0	0
T53	0	192	0	0
T84	0	351	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7230463	0	0
T1	16990	16574	0	0
T2	837	436	0	0
T3	11228	10810	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	50	0	0
T7	13230	12	0	0
T8	39472	0	0	0
T9	18832	0	0	0
T10	8590	3	0	0
T11	1044	0	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T90	0	6	0	0
T98	0	1	0	0
T261	0	2	0	0
T263	0	4	0	0
T264	0	2	0	0
T265	0	7	0	0
T266	0	2	0	0
T267	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	16777	0	0
T1	16990	104	0	0
T2	837	0	0	0
T3	11228	61	0	0
T5	11957	0	0	0
T6	28425	272	0	0
T8	0	5	0	0
T12	0	236	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	293	0	0
T34	0	49	0	0
T53	0	384	0	0
T84	0	198	0	0
T180	0	308	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	374	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	1	0	0
T5	11957	0	0	0
T6	28425	8	0	0
T8	0	1	0	0
T12	0	5	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T53	0	6	0	0
T84	0	3	0	0
T180	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6833250	0	0
T1	16990	14852	0	0
T2	837	436	0	0
T3	11228	9167	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6834924	0	0
T1	16990	14856	0	0
T2	837	437	0	0
T3	11228	9168	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	496	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	1	0	0
T5	11957	0	0	0
T6	28425	8	0	0
T7	0	14	0	0
T8	0	1	0	0
T10	0	3	0	0
T12	0	5	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	5	0	0
T53	0	6	0	0
T84	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	427	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	1	0	0
T5	11957	0	0	0
T6	28425	8	0	0
T7	0	12	0	0
T8	0	1	0	0
T10	0	3	0	0
T12	0	5	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	4	0	0
T53	0	6	0	0
T84	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	374	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	1	0	0
T5	11957	0	0	0
T6	28425	8	0	0
T8	0	1	0	0
T12	0	5	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T53	0	6	0	0
T84	0	3	0	0
T180	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	374	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	1	0	0
T5	11957	0	0	0
T6	28425	8	0	0
T8	0	1	0	0
T12	0	5	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T53	0	6	0	0
T84	0	3	0	0
T180	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	16375	0	0
T1	16990	102	0	0
T2	837	0	0	0
T3	11228	60	0	0
T5	11957	0	0	0
T6	28425	264	0	0
T8	0	4	0	0
T12	0	231	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	289	0	0
T34	0	46	0	0
T53	0	378	0	0
T84	0	195	0	0
T180	0	299	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	343	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	1	0	0
T5	11957	0	0	0
T6	28425	8	0	0
T8	0	1	0	0
T12	0	5	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	4	0	0
T34	0	3	0	0
T53	0	6	0	0
T84	0	3	0	0
T180	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T27
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T27
0	1	Covered	T27,T47,T51
1	0	Covered	T3,T47,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T33
0	1	Covered	T1,T9,T33
1	0	Covered	T76,T268,T269

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T33
1	-	Covered	T1,T9,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T27
DetectSt	168	Covered	T1,T3,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T9,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T27
DebounceSt->IdleSt	163	Covered	T69,T255,T57
DetectSt->IdleSt	186	Covered	T3,T27,T47
DetectSt->StableSt	191	Covered	T1,T9,T33
IdleSt->DebounceSt	148	Covered	T1,T3,T27
StableSt->IdleSt	206	Covered	T1,T9,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T27
0	1	Covered	T1,T3,T27
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T255,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T27
DetectSt	-	-	-	-	1	-	-	Covered	T3,T27,T47
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T27
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	2983	0	0
CntIncr_A	7891491	98302	0	0
CntNoWrap_A	7891491	7228403	0	0
DetectStDropOut_A	7891491	410	0	0
DetectedOut_A	7891491	78265	0	0
DetectedPulseOut_A	7891491	851	0	0
DisabledIdleSt_A	7891491	6779406	0	0
DisabledNoDetection_A	7891491	6781613	0	0
EnterDebounceSt_A	7891491	1507	0	0
EnterDetectSt_A	7891491	1477	0	0
EnterStableSt_A	7891491	851	0	0
PulseIsPulse_A	7891491	851	0	0
StayInStableSt	7891491	77313	0	0
gen_high_event_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	729	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	2983	0	0
T1	16990	22	0	0
T2	837	0	0	0
T3	11228	50	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	28	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	8	0	0
T33	0	20	0	0
T47	0	56	0	0
T51	0	44	0	0
T53	0	12	0	0
T65	0	54	0	0
T66	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	98302	0	0
T1	16990	792	0	0
T2	837	0	0	0
T3	11228	1425	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	784	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	217	0	0
T33	0	720	0	0
T47	0	1698	0	0
T51	0	1077	0	0
T53	0	252	0	0
T65	0	1296	0	0
T66	0	1540	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7228403	0	0
T1	16990	16556	0	0
T2	837	436	0	0
T3	11228	10762	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	410	0	0
T7	13230	0	0	0
T8	39472	0	0	0
T24	502	0	0	0
T26	741	0	0	0
T27	5366	4	0	0
T32	1111	0	0	0
T47	0	12	0	0
T48	1667	0	0	0
T49	654	0	0	0
T51	0	22	0	0
T58	603	0	0	0
T62	496	0	0	0
T66	0	24	0	0
T74	0	10	0	0
T87	0	13	0	0
T88	0	25	0	0
T117	0	10	0	0
T256	0	25	0	0
T257	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	78265	0	0
T1	16990	1065	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	1728	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	404	0	0
T53	0	652	0	0
T65	0	1787	0	0
T75	0	6216	0	0
T76	0	924	0	0
T231	0	1040	0	0
T238	0	2151	0	0
T259	0	2088	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	851	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	14	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	10	0	0
T53	0	6	0	0
T65	0	27	0	0
T75	0	21	0	0
T76	0	9	0	0
T231	0	31	0	0
T238	0	23	0	0
T259	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6779406	0	0
T1	16990	9346	0	0
T2	837	436	0	0
T3	11228	7800	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6781613	0	0
T1	16990	9348	0	0
T2	837	437	0	0
T3	11228	7803	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1507	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	25	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	14	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	4	0	0
T33	0	10	0	0
T47	0	28	0	0
T51	0	22	0	0
T53	0	6	0	0
T65	0	27	0	0
T66	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1477	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	25	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	14	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	4	0	0
T33	0	10	0	0
T47	0	28	0	0
T51	0	22	0	0
T53	0	6	0	0
T65	0	27	0	0
T66	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	851	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	14	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	10	0	0
T53	0	6	0	0
T65	0	27	0	0
T75	0	21	0	0
T76	0	9	0	0
T231	0	31	0	0
T238	0	23	0	0
T259	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	851	0	0
T1	16990	11	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	14	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	10	0	0
T53	0	6	0	0
T65	0	27	0	0
T75	0	21	0	0
T76	0	9	0	0
T231	0	31	0	0
T238	0	23	0	0
T259	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	77313	0	0
T1	16990	1053	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	1711	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	394	0	0
T53	0	644	0	0
T65	0	1760	0	0
T75	0	6193	0	0
T76	0	915	0	0
T231	0	1006	0	0
T238	0	2127	0	0
T259	0	2056	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	729	0	0
T1	16990	10	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	11	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	10	0	0
T53	0	4	0	0
T65	0	27	0	0
T75	0	19	0	0
T231	0	28	0	0
T238	0	22	0	0
T259	0	16	0	0
T260	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T7
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T34,T270,T263
1	0	Covered	T69,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
1	0	Covered	T69,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T7
1	-	Covered	T1,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T7
DetectSt	168	Covered	T1,T6,T7
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T7
DebounceSt->IdleSt	163	Covered	T12,T53,T261
DetectSt->IdleSt	186	Covered	T34,T69,T270
DetectSt->StableSt	191	Covered	T1,T6,T7
IdleSt->DebounceSt	148	Covered	T1,T6,T7
StableSt->IdleSt	206	Covered	T1,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T7
0	1	Covered	T1,T6,T7
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T7
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T53,T261
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T34,T69,T270
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	901	0	0
CntIncr_A	7891491	49223	0	0
CntNoWrap_A	7891491	7230485	0	0
DetectStDropOut_A	7891491	30	0	0
DetectedOut_A	7891491	16891	0	0
DetectedPulseOut_A	7891491	384	0	0
DisabledIdleSt_A	7891491	6818154	0	0
DisabledNoDetection_A	7891491	6819804	0	0
EnterDebounceSt_A	7891491	483	0	0
EnterDetectSt_A	7891491	419	0	0
EnterStableSt_A	7891491	384	0	0
PulseIsPulse_A	7891491	384	0	0
StayInStableSt	7891491	16469	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	344	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	901	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	6	0	0
T7	0	8	0	0
T8	0	8	0	0
T9	0	6	0	0
T10	0	2	0	0
T12	0	15	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	5	0	0
T84	0	6	0	0
T271	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	49223	0	0
T1	16990	53	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	174	0	0
T7	0	288	0	0
T8	0	644	0	0
T9	0	231	0	0
T10	0	88	0	0
T12	0	656	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	136	0	0
T84	0	462	0	0
T271	0	543	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7230485	0	0
T1	16990	16576	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	30	0	0
T34	20072	2	0	0
T60	534	0	0	0
T66	5819	0	0	0
T92	0	8	0	0
T177	0	1	0	0
T179	502	0	0	0
T180	38159	0	0	0
T210	500	0	0	0
T263	0	1	0	0
T264	0	2	0	0
T265	0	3	0	0
T270	0	3	0	0
T272	0	2	0	0
T273	0	5	0	0
T274	0	2	0	0
T275	3183	0	0	0
T276	402	0	0	0
T277	423	0	0	0
T278	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	16891	0	0
T1	16990	70	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	160	0	0
T7	0	56	0	0
T8	0	149	0	0
T9	0	170	0	0
T10	0	72	0	0
T12	0	194	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	79	0	0
T84	0	87	0	0
T271	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	384	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	4	0	0
T8	0	4	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	0	7	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	2	0	0
T84	0	3	0	0
T271	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6818154	0	0
T1	16990	15514	0	0
T2	837	436	0	0
T3	11228	10812	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6819804	0	0
T1	16990	15517	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	483	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	4	0	0
T8	0	4	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	0	8	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	3	0	0
T84	0	3	0	0
T271	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	419	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	4	0	0
T8	0	4	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	0	7	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	2	0	0
T84	0	3	0	0
T271	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	384	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	4	0	0
T8	0	4	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	0	7	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	2	0	0
T84	0	3	0	0
T271	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	384	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	4	0	0
T8	0	4	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	0	7	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	2	0	0
T84	0	3	0	0
T271	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	16469	0	0
T1	16990	69	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	157	0	0
T7	0	52	0	0
T8	0	145	0	0
T9	0	167	0	0
T10	0	71	0	0
T12	0	187	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	77	0	0
T84	0	84	0	0
T271	0	9	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	344	0	0
T1	16990	1	0	0
T2	837	0	0	0
T3	11228	0	0	0
T5	11957	0	0	0
T6	28425	3	0	0
T7	0	4	0	0
T8	0	4	0	0
T9	0	3	0	0
T10	0	1	0	0
T12	0	7	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T53	0	2	0	0
T84	0	3	0	0
T271	0	3	0	0