Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T27
1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T27
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T3,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T27
0	1	Covered	T27,T47,T51
1	0	Covered	T47,T65,T259

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T27
DetectSt	168	Covered	T1,T3,T27
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T27
DebounceSt->IdleSt	163	Covered	T69,T255,T57
DetectSt->IdleSt	186	Covered	T27,T47,T51
DetectSt->StableSt	191	Covered	T1,T3,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T27
StableSt->IdleSt	206	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T27
0	1	Covered	T1,T3,T27
0	0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T27
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T69,T255,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T27
DetectSt	-	-	-	-	1	-	-	Covered	T27,T47,T51
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T27
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T9
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	3089	0	0
CntIncr_A	7891491	105922	0	0
CntNoWrap_A	7891491	7228297	0	0
DetectStDropOut_A	7891491	402	0	0
DetectedOut_A	7891491	69251	0	0
DetectedPulseOut_A	7891491	901	0	0
DisabledIdleSt_A	7891491	6791190	0	0
DisabledNoDetection_A	7891491	6793414	0	0
EnterDebounceSt_A	7891491	1557	0	0
EnterDetectSt_A	7891491	1533	0	0
EnterStableSt_A	7891491	901	0	0
PulseIsPulse_A	7891491	901	0	0
StayInStableSt	7891491	68267	0	0
gen_high_event_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	798	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	3089	0	0
T1	16990	24	0	0
T2	837	0	0	0
T3	11228	60	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	50	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	10	0	0
T33	0	20	0	0
T47	0	30	0	0
T51	0	44	0	0
T53	0	28	0	0
T65	0	38	0	0
T66	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	105922	0	0
T1	16990	828	0	0
T2	837	0	0	0
T3	11228	1440	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	1675	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	272	0	0
T33	0	780	0	0
T47	0	902	0	0
T51	0	1071	0	0
T53	0	882	0	0
T65	0	1290	0	0
T66	0	889	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7228297	0	0
T1	16990	16554	0	0
T2	837	436	0	0
T3	11228	10752	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	402	0	0
T7	13230	0	0	0
T8	39472	0	0	0
T24	502	0	0	0
T26	741	0	0	0
T27	5366	5	0	0
T32	1111	0	0	0
T47	0	7	0	0
T48	1667	0	0	0
T49	654	0	0	0
T51	0	22	0	0
T58	603	0	0	0
T62	496	0	0	0
T65	0	4	0	0
T66	0	14	0	0
T87	0	23	0	0
T88	0	16	0	0
T256	0	10	0	0
T259	0	5	0	0
T260	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	69251	0	0
T1	16990	1658	0	0
T2	837	0	0	0
T3	11228	1424	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	1054	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	344	0	0
T53	0	1161	0	0
T74	0	118	0	0
T75	0	5636	0	0
T76	0	3312	0	0
T117	0	1873	0	0
T231	0	2335	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	901	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	30	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	25	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	10	0	0
T53	0	14	0	0
T74	0	14	0	0
T75	0	30	0	0
T76	0	23	0	0
T117	0	15	0	0
T231	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6791190	0	0
T1	16990	8853	0	0
T2	837	436	0	0
T3	11228	6619	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6793414	0	0
T1	16990	8854	0	0
T2	837	437	0	0
T3	11228	6619	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1557	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	30	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	25	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	5	0	0
T33	0	10	0	0
T47	0	15	0	0
T51	0	22	0	0
T53	0	14	0	0
T65	0	19	0	0
T66	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	1533	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	30	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	25	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T27	0	5	0	0
T33	0	10	0	0
T47	0	15	0	0
T51	0	22	0	0
T53	0	14	0	0
T65	0	19	0	0
T66	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	901	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	30	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	25	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	10	0	0
T53	0	14	0	0
T74	0	14	0	0
T75	0	30	0	0
T76	0	23	0	0
T117	0	15	0	0
T231	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	901	0	0
T1	16990	12	0	0
T2	837	0	0	0
T3	11228	30	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	25	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	10	0	0
T53	0	14	0	0
T74	0	14	0	0
T75	0	30	0	0
T76	0	23	0	0
T117	0	15	0	0
T231	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	68267	0	0
T1	16990	1644	0	0
T2	837	0	0	0
T3	11228	1392	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	1027	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	334	0	0
T53	0	1143	0	0
T74	0	104	0	0
T75	0	5606	0	0
T76	0	3286	0	0
T117	0	1856	0	0
T231	0	2301	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	798	0	0
T1	16990	10	0	0
T2	837	0	0	0
T3	11228	28	0	0
T5	11957	0	0	0
T6	28425	0	0	0
T9	0	23	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T33	0	10	0	0
T53	0	10	0	0
T74	0	14	0	0
T75	0	10	0	0
T76	0	20	0	0
T117	0	13	0	0
T231	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T4,T1,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T4,T1,T5
1	1	Covered	T4,T1,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T5	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T5
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T7,T8,T12
1	0	Covered	T69,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T3,T6,T9
1	0	Covered	T71,T57

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T6
1	-	Covered	T3,T6,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T1,T5
StableSt	191	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T8,T34,T180
DetectSt->IdleSt	186	Covered	T7,T8,T12
DetectSt->StableSt	191	Covered	T1,T3,T6
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T1,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T69,T57
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T34,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T7,T8,T12
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T5
0	Covered	T4,T1,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7891491	919	0	0
CntIncr_A	7891491	52206	0	0
CntNoWrap_A	7891491	7230467	0	0
DetectStDropOut_A	7891491	73	0	0
DetectedOut_A	7891491	15060	0	0
DetectedPulseOut_A	7891491	354	0	0
DisabledIdleSt_A	7891491	6839852	0	0
DisabledNoDetection_A	7891491	6841539	0	0
EnterDebounceSt_A	7891491	488	0	0
EnterDetectSt_A	7891491	433	0	0
EnterStableSt_A	7891491	354	0	0
PulseIsPulse_A	7891491	354	0	0
StayInStableSt	7891491	14686	0	0
gen_high_level_sva.HighLevelEvent_A	7891491	7233785	0	0
gen_not_sticky_sva.StableStDropOut_A	7891491	331	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	919	0	0
T1	16990	4	0	0
T2	837	0	0	0
T3	11228	4	0	0
T5	11957	0	0	0
T6	28425	4	0	0
T7	0	8	0	0
T8	0	21	0	0
T9	0	4	0	0
T12	0	8	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T34	0	12	0	0
T53	0	4	0	0
T271	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	52206	0	0
T1	16990	132	0	0
T2	837	0	0	0
T3	11228	108	0	0
T5	11957	0	0	0
T6	28425	188	0	0
T7	0	344	0	0
T8	0	2099	0	0
T9	0	186	0	0
T12	0	352	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T34	0	608	0	0
T53	0	140	0	0
T271	0	101	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7230467	0	0
T1	16990	16574	0	0
T2	837	436	0	0
T3	11228	10808	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	73	0	0
T7	13230	4	0	0
T8	39472	10	0	0
T9	18832	0	0	0
T10	8590	0	0	0
T11	1044	0	0	0
T12	0	2	0	0
T47	6969	0	0	0
T50	650	0	0	0
T54	505	0	0	0
T55	492	0	0	0
T56	535	0	0	0
T228	0	11	0	0
T247	0	4	0	0
T279	0	10	0	0
T280	0	5	0	0
T281	0	6	0	0
T282	0	8	0	0
T283	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	15060	0	0
T1	16990	110	0	0
T2	837	0	0	0
T3	11228	155	0	0
T5	11957	0	0	0
T6	28425	35	0	0
T9	0	81	0	0
T12	0	99	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T34	0	194	0	0
T53	0	53	0	0
T117	0	169	0	0
T180	0	156	0	0
T271	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	354	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	2	0	0
T5	11957	0	0	0
T6	28425	2	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T34	0	5	0	0
T53	0	2	0	0
T117	0	2	0	0
T180	0	5	0	0
T271	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6839852	0	0
T1	16990	14922	0	0
T2	837	436	0	0
T3	11228	9390	0	0
T4	5334	4933	0	0
T5	11957	11556	0	0
T13	493	92	0	0
T14	763	362	0	0
T15	707	306	0	0
T16	402	1	0	0
T17	425	24	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	6841539	0	0
T1	16990	14924	0	0
T2	837	437	0	0
T3	11228	9391	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	488	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	2	0	0
T5	11957	0	0	0
T6	28425	2	0	0
T7	0	4	0	0
T8	0	11	0	0
T9	0	2	0	0
T12	0	4	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T34	0	7	0	0
T53	0	2	0	0
T271	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	433	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	2	0	0
T5	11957	0	0	0
T6	28425	2	0	0
T7	0	4	0	0
T8	0	10	0	0
T9	0	2	0	0
T12	0	4	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T34	0	5	0	0
T53	0	2	0	0
T271	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	354	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	2	0	0
T5	11957	0	0	0
T6	28425	2	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T34	0	5	0	0
T53	0	2	0	0
T117	0	2	0	0
T180	0	5	0	0
T271	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	354	0	0
T1	16990	2	0	0
T2	837	0	0	0
T3	11228	2	0	0
T5	11957	0	0	0
T6	28425	2	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T34	0	5	0	0
T53	0	2	0	0
T117	0	2	0	0
T180	0	5	0	0
T271	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	14686	0	0
T1	16990	106	0	0
T2	837	0	0	0
T3	11228	153	0	0
T5	11957	0	0	0
T6	28425	33	0	0
T9	0	79	0	0
T12	0	97	0	0
T13	493	0	0	0
T14	763	0	0	0
T15	707	0	0	0
T16	402	0	0	0
T17	425	0	0	0
T34	0	189	0	0
T53	0	51	0	0
T117	0	165	0	0
T180	0	151	0	0
T271	0	83	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	7233785	0	0
T1	16990	16582	0	0
T2	837	437	0	0
T3	11228	10815	0	0
T4	5334	4934	0	0
T5	11957	11557	0	0
T13	493	93	0	0
T14	763	363	0	0
T15	707	307	0	0
T16	402	2	0	0
T17	425	25	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7891491	331	0	0
T3	11228	2	0	0
T6	28425	2	0	0
T9	0	2	0	0
T12	0	2	0	0
T16	402	0	0	0
T17	425	0	0	0
T22	497	0	0	0
T23	525	0	0	0
T26	741	0	0	0
T27	5366	0	0	0
T32	1111	0	0	0
T34	0	5	0	0
T53	0	2	0	0
T61	429	0	0	0
T180	0	5	0	0
T261	0	5	0	0
T271	0	1	0	0
T284	0	3	0	0