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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.89 99.37 96.71 100.00 96.79 98.85 99.42 94.05


Total test records in report: 908
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T77 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.156363194 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:41 PM PDT 24 2027956167 ps
T78 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.686873158 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:40 PM PDT 24 2026464672 ps
T88 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.658218062 Apr 02 12:30:30 PM PDT 24 Apr 02 12:30:33 PM PDT 24 2353969451 ps
T87 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2270174280 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:40 PM PDT 24 2050891620 ps
T793 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3799700838 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:36 PM PDT 24 2021255442 ps
T82 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3371952678 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:51 PM PDT 24 22466103407 ps
T83 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3192939854 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:49 PM PDT 24 22485467632 ps
T90 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.860317173 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:38 PM PDT 24 2171115538 ps
T295 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.808950805 Apr 02 12:30:37 PM PDT 24 Apr 02 12:32:17 PM PDT 24 37816864238 ps
T21 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3011650713 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:48 PM PDT 24 2049509939 ps
T86 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2406653084 Apr 02 12:31:26 PM PDT 24 Apr 02 12:31:34 PM PDT 24 2155369164 ps
T292 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2693595993 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:36 PM PDT 24 2071038739 ps
T293 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3806738920 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2038198201 ps
T794 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2427706286 Apr 02 12:30:38 PM PDT 24 Apr 02 12:30:41 PM PDT 24 2025653658 ps
T795 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.852632608 Apr 02 12:31:12 PM PDT 24 Apr 02 12:31:15 PM PDT 24 2025988836 ps
T796 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.481882763 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:35 PM PDT 24 2056060453 ps
T89 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2716655627 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:35 PM PDT 24 2722413432 ps
T22 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.67229018 Apr 02 12:30:28 PM PDT 24 Apr 02 12:31:07 PM PDT 24 9631473196 ps
T91 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3932912237 Apr 02 12:30:28 PM PDT 24 Apr 02 12:30:34 PM PDT 24 2167626323 ps
T278 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2970906508 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:35 PM PDT 24 2067078661 ps
T331 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2350502352 Apr 02 12:30:32 PM PDT 24 Apr 02 12:31:05 PM PDT 24 22231298772 ps
T23 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.443881738 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:45 PM PDT 24 4703686701 ps
T279 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3898247113 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2042454204 ps
T797 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.448288306 Apr 02 12:30:28 PM PDT 24 Apr 02 12:30:30 PM PDT 24 2030590476 ps
T280 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1086099692 Apr 02 12:30:39 PM PDT 24 Apr 02 12:30:40 PM PDT 24 2083677936 ps
T294 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.648857299 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:47 PM PDT 24 9273469041 ps
T798 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3692054334 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:42 PM PDT 24 2011717014 ps
T281 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3587347321 Apr 02 12:30:29 PM PDT 24 Apr 02 12:30:32 PM PDT 24 4048554386 ps
T799 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2376349872 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:37 PM PDT 24 2155021525 ps
T800 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2316411597 Apr 02 12:30:42 PM PDT 24 Apr 02 12:30:51 PM PDT 24 2017905297 ps
T801 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3760559015 Apr 02 12:30:27 PM PDT 24 Apr 02 12:30:29 PM PDT 24 2034717829 ps
T802 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1858786362 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:54 PM PDT 24 8429741040 ps
T803 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1773461334 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2190562356 ps
T282 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.163224990 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:43 PM PDT 24 2766170445 ps
T804 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1545375806 Apr 02 12:30:38 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2046412605 ps
T341 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2933016894 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:42 PM PDT 24 2081445682 ps
T805 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3171287923 Apr 02 12:30:41 PM PDT 24 Apr 02 12:30:43 PM PDT 24 2062905431 ps
T283 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.86529269 Apr 02 12:30:27 PM PDT 24 Apr 02 12:30:32 PM PDT 24 2022291775 ps
T92 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2170936126 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:36 PM PDT 24 2119728790 ps
T340 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.551022111 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:43 PM PDT 24 2675877831 ps
T806 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3271938399 Apr 02 12:30:28 PM PDT 24 Apr 02 12:30:30 PM PDT 24 2123156120 ps
T332 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1947398132 Apr 02 12:30:35 PM PDT 24 Apr 02 12:31:37 PM PDT 24 22241512073 ps
T334 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1590971083 Apr 02 12:30:36 PM PDT 24 Apr 02 12:31:07 PM PDT 24 22207846138 ps
T807 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1076427743 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:38 PM PDT 24 2273662140 ps
T808 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3403896094 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:42 PM PDT 24 2009586877 ps
T809 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1113080835 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:35 PM PDT 24 2048353971 ps
T810 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3356103675 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2849793494 ps
T811 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3026287847 Apr 02 12:30:25 PM PDT 24 Apr 02 12:30:30 PM PDT 24 2137394317 ps
T812 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.933863143 Apr 02 12:30:58 PM PDT 24 Apr 02 12:31:00 PM PDT 24 2038731401 ps
T335 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.137589404 Apr 02 12:30:33 PM PDT 24 Apr 02 12:31:31 PM PDT 24 22217242981 ps
T813 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3795568200 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2054535711 ps
T814 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1760936318 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:40 PM PDT 24 2156921573 ps
T815 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1562639252 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:38 PM PDT 24 2089432359 ps
T816 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3934615458 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2032960316 ps
T817 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3872305075 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:42 PM PDT 24 2070908733 ps
T818 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3534658492 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:43 PM PDT 24 2057671291 ps
T819 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1507585064 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:34 PM PDT 24 2048395968 ps
T820 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.232480243 Apr 02 12:31:26 PM PDT 24 Apr 02 12:31:32 PM PDT 24 2012492253 ps
T821 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.529282236 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:47 PM PDT 24 2067289212 ps
T822 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3722714822 Apr 02 12:30:39 PM PDT 24 Apr 02 12:30:46 PM PDT 24 2065877343 ps
T823 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2989883678 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:43 PM PDT 24 2012167485 ps
T824 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2398411731 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:34 PM PDT 24 4475305875 ps
T825 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2748371198 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:35 PM PDT 24 2200354117 ps
T826 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3565154845 Apr 02 12:30:27 PM PDT 24 Apr 02 12:31:00 PM PDT 24 7623471994 ps
T827 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4050757789 Apr 02 12:30:41 PM PDT 24 Apr 02 12:30:46 PM PDT 24 2012782375 ps
T828 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.233697366 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:41 PM PDT 24 2022295144 ps
T829 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.60479595 Apr 02 12:31:23 PM PDT 24 Apr 02 12:31:27 PM PDT 24 2141325500 ps
T284 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2631911993 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2034884020 ps
T285 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2983430264 Apr 02 12:30:28 PM PDT 24 Apr 02 12:31:02 PM PDT 24 40964097458 ps
T830 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.400307921 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2046521071 ps
T831 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.4120482739 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:39 PM PDT 24 7921315373 ps
T286 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3510413283 Apr 02 12:30:16 PM PDT 24 Apr 02 12:30:18 PM PDT 24 6297064185 ps
T832 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1419497156 Apr 02 12:30:39 PM PDT 24 Apr 02 12:30:45 PM PDT 24 2039069724 ps
T287 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.312859312 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2068591437 ps
T833 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4111808756 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2167306437 ps
T834 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.402841503 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:37 PM PDT 24 2014555829 ps
T835 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.358418724 Apr 02 12:30:37 PM PDT 24 Apr 02 12:31:05 PM PDT 24 6858512887 ps
T836 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1734347283 Apr 02 12:30:29 PM PDT 24 Apr 02 12:30:33 PM PDT 24 2098076853 ps
T837 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2288572757 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:38 PM PDT 24 2149249058 ps
T838 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3462853094 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2036372755 ps
T839 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1984924825 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:47 PM PDT 24 6048467544 ps
T840 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3383321723 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:47 PM PDT 24 4591672690 ps
T841 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.4266958174 Apr 02 12:30:31 PM PDT 24 Apr 02 12:32:20 PM PDT 24 42407446396 ps
T842 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2695193246 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:36 PM PDT 24 2339975751 ps
T843 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.335053987 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:38 PM PDT 24 2029425882 ps
T844 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2257148664 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:34 PM PDT 24 2058612163 ps
T845 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3639197064 Apr 02 12:30:34 PM PDT 24 Apr 02 12:31:34 PM PDT 24 22185592486 ps
T846 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.875787545 Apr 02 12:30:38 PM PDT 24 Apr 02 12:30:45 PM PDT 24 2057390284 ps
T847 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2206671800 Apr 02 12:30:29 PM PDT 24 Apr 02 12:30:35 PM PDT 24 2067073462 ps
T848 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1243325199 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2079454383 ps
T849 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4062164539 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:48 PM PDT 24 4658381237 ps
T850 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.569931306 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:34 PM PDT 24 2083607914 ps
T851 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1173130408 Apr 02 12:30:30 PM PDT 24 Apr 02 12:30:34 PM PDT 24 4972736852 ps
T852 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2091186604 Apr 02 12:30:29 PM PDT 24 Apr 02 12:30:31 PM PDT 24 4072555050 ps
T853 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2497303030 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2011161662 ps
T291 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.4263915300 Apr 02 12:30:30 PM PDT 24 Apr 02 12:30:34 PM PDT 24 2056880533 ps
T288 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1916453785 Apr 02 12:30:29 PM PDT 24 Apr 02 12:30:32 PM PDT 24 2067065649 ps
T854 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1803385289 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:43 PM PDT 24 2013779728 ps
T855 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2503852315 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:37 PM PDT 24 2031370796 ps
T336 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2095527871 Apr 02 12:30:33 PM PDT 24 Apr 02 12:32:25 PM PDT 24 42385663503 ps
T856 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.886770705 Apr 02 12:30:40 PM PDT 24 Apr 02 12:30:41 PM PDT 24 2277508313 ps
T857 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.96901609 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:36 PM PDT 24 2115841170 ps
T858 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2663028475 Apr 02 12:30:28 PM PDT 24 Apr 02 12:30:34 PM PDT 24 2009488350 ps
T859 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3294296257 Apr 02 12:30:37 PM PDT 24 Apr 02 12:31:08 PM PDT 24 42500914952 ps
T860 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3197088124 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:42 PM PDT 24 4024105854 ps
T861 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2081657114 Apr 02 12:30:39 PM PDT 24 Apr 02 12:30:45 PM PDT 24 2012514346 ps
T862 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2318129754 Apr 02 12:30:30 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2674899596 ps
T863 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3953533807 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:44 PM PDT 24 4521143235 ps
T864 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3381590184 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:35 PM PDT 24 10581992958 ps
T865 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3085475740 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:42 PM PDT 24 2013863072 ps
T866 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2135714818 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:42 PM PDT 24 2061289903 ps
T289 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.4156899342 Apr 02 12:30:25 PM PDT 24 Apr 02 12:31:21 PM PDT 24 39246177845 ps
T867 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1603288624 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:58 PM PDT 24 9190443295 ps
T290 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.846073598 Apr 02 12:30:30 PM PDT 24 Apr 02 12:33:25 PM PDT 24 46760851434 ps
T868 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.518896687 Apr 02 12:30:32 PM PDT 24 Apr 02 12:31:02 PM PDT 24 22287175598 ps
T869 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.4176524613 Apr 02 12:30:36 PM PDT 24 Apr 02 12:31:35 PM PDT 24 22237336012 ps
T870 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.710662394 Apr 02 12:30:25 PM PDT 24 Apr 02 12:31:10 PM PDT 24 38824265994 ps
T871 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1809361263 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:46 PM PDT 24 8689983497 ps
T872 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1700314833 Apr 02 12:30:33 PM PDT 24 Apr 02 12:31:30 PM PDT 24 22227766685 ps
T337 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1667873809 Apr 02 12:30:35 PM PDT 24 Apr 02 12:31:04 PM PDT 24 22267230825 ps
T873 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1179894970 Apr 02 12:30:28 PM PDT 24 Apr 02 12:30:34 PM PDT 24 2009681878 ps
T874 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.578542237 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:42 PM PDT 24 2510232863 ps
T875 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.987384086 Apr 02 12:30:29 PM PDT 24 Apr 02 12:30:32 PM PDT 24 2021309358 ps
T876 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1837804137 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:36 PM PDT 24 4779323891 ps
T333 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2737210129 Apr 02 12:30:32 PM PDT 24 Apr 02 12:31:31 PM PDT 24 42542747601 ps
T877 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.733744309 Apr 02 12:31:02 PM PDT 24 Apr 02 12:31:07 PM PDT 24 2018567876 ps
T878 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1419283366 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2038352718 ps
T879 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1343740225 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:38 PM PDT 24 2281292553 ps
T880 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3988919954 Apr 02 12:30:38 PM PDT 24 Apr 02 12:30:40 PM PDT 24 2044057906 ps
T881 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.683555476 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:38 PM PDT 24 2048215526 ps
T882 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2986191451 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:41 PM PDT 24 2519768229 ps
T883 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.928749617 Apr 02 12:30:30 PM PDT 24 Apr 02 12:30:33 PM PDT 24 2258892882 ps
T884 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3359518455 Apr 02 12:30:38 PM PDT 24 Apr 02 12:30:41 PM PDT 24 2095429082 ps
T885 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2676299791 Apr 02 12:30:30 PM PDT 24 Apr 02 12:30:36 PM PDT 24 2014984776 ps
T886 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2567695981 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:41 PM PDT 24 2013322003 ps
T338 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3092068181 Apr 02 12:30:30 PM PDT 24 Apr 02 12:30:56 PM PDT 24 42589990486 ps
T887 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1568484220 Apr 02 12:30:32 PM PDT 24 Apr 02 12:30:39 PM PDT 24 2108822779 ps
T888 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3646115580 Apr 02 12:30:31 PM PDT 24 Apr 02 12:30:37 PM PDT 24 2014583254 ps
T889 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3418199787 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:38 PM PDT 24 2040345712 ps
T890 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2866972551 Apr 02 12:30:27 PM PDT 24 Apr 02 12:30:30 PM PDT 24 2020997999 ps
T891 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2754349763 Apr 02 12:30:41 PM PDT 24 Apr 02 12:30:48 PM PDT 24 2127345466 ps
T892 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3708716665 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:38 PM PDT 24 2032016527 ps
T893 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.218842467 Apr 02 12:30:38 PM PDT 24 Apr 02 12:30:55 PM PDT 24 4776099561 ps
T894 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3957881257 Apr 02 12:30:32 PM PDT 24 Apr 02 12:31:01 PM PDT 24 42822566194 ps
T895 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2650431665 Apr 02 12:30:37 PM PDT 24 Apr 02 12:30:43 PM PDT 24 5151011362 ps
T896 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1921419836 Apr 02 12:30:43 PM PDT 24 Apr 02 12:30:49 PM PDT 24 2010443977 ps
T897 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1500748962 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:37 PM PDT 24 2318374977 ps
T898 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4060480102 Apr 02 12:31:25 PM PDT 24 Apr 02 12:31:28 PM PDT 24 2042205906 ps
T899 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4177685108 Apr 02 12:30:42 PM PDT 24 Apr 02 12:30:44 PM PDT 24 2032533398 ps
T900 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3547102229 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:45 PM PDT 24 4487223063 ps
T901 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1999909887 Apr 02 12:30:31 PM PDT 24 Apr 02 12:31:32 PM PDT 24 22236776228 ps
T902 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2358786724 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:43 PM PDT 24 2048995930 ps
T903 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3543177361 Apr 02 12:30:21 PM PDT 24 Apr 02 12:31:18 PM PDT 24 42460283432 ps
T904 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.863082055 Apr 02 12:30:36 PM PDT 24 Apr 02 12:30:42 PM PDT 24 2015072774 ps
T905 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.425504580 Apr 02 12:30:35 PM PDT 24 Apr 02 12:30:46 PM PDT 24 9491232229 ps
T906 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1785121041 Apr 02 12:30:33 PM PDT 24 Apr 02 12:30:35 PM PDT 24 2372175092 ps
T907 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.104984888 Apr 02 12:30:34 PM PDT 24 Apr 02 12:30:41 PM PDT 24 2028723778 ps
T908 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1978918179 Apr 02 12:30:48 PM PDT 24 Apr 02 12:30:54 PM PDT 24 2117918528 ps

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.471335777
Short name T1
Test name
Test status
Simulation time 87049469633 ps
CPU time 221.29 seconds
Started Apr 02 01:03:52 PM PDT 24
Finished Apr 02 01:07:34 PM PDT 24
Peak memory 210596 kb
Host smart-01a56889-d2a9-4122-b87d-f119d8e576f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471335777 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.471335777
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.64057311
Short name T8
Test name
Test status
Simulation time 136919410656 ps
CPU time 92.35 seconds
Started Apr 02 01:04:09 PM PDT 24
Finished Apr 02 01:05:44 PM PDT 24
Peak memory 202128 kb
Host smart-d21af8dc-c640-4d14-8daf-6d7b7e11cda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64057311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_wit
h_pre_cond.64057311
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1211214908
Short name T75
Test name
Test status
Simulation time 41843878643 ps
CPU time 6.31 seconds
Started Apr 02 01:02:31 PM PDT 24
Finished Apr 02 01:02:38 PM PDT 24
Peak memory 201956 kb
Host smart-3c0a6b88-faf2-4232-b96f-863c2527325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211214908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.1211214908
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.801464072
Short name T103
Test name
Test status
Simulation time 99903352007 ps
CPU time 57.82 seconds
Started Apr 02 01:05:22 PM PDT 24
Finished Apr 02 01:06:20 PM PDT 24
Peak memory 218668 kb
Host smart-213c142a-30c0-40aa-9c72-aee369cc71c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801464072 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.801464072
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1140216598
Short name T41
Test name
Test status
Simulation time 84802051303 ps
CPU time 60.5 seconds
Started Apr 02 01:03:06 PM PDT 24
Finished Apr 02 01:04:07 PM PDT 24
Peak memory 212572 kb
Host smart-eafe4d9e-3146-452f-b74a-776d4cdd5fff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140216598 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.1140216598
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.73160168
Short name T33
Test name
Test status
Simulation time 98112467191 ps
CPU time 58.72 seconds
Started Apr 02 01:05:43 PM PDT 24
Finished Apr 02 01:06:43 PM PDT 24
Peak memory 202148 kb
Host smart-696b6d05-cb49-46b1-9862-c6e55a0747fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73160168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_str
ess_all.73160168
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.458597528
Short name T56
Test name
Test status
Simulation time 3881373248967 ps
CPU time 311.55 seconds
Started Apr 02 01:05:25 PM PDT 24
Finished Apr 02 01:10:36 PM PDT 24
Peak memory 201948 kb
Host smart-a65ada29-d649-4d45-8024-c9a9e0c7778e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458597528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ultra_low_pwr.458597528
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1703315679
Short name T110
Test name
Test status
Simulation time 969996216514 ps
CPU time 63.72 seconds
Started Apr 02 01:03:13 PM PDT 24
Finished Apr 02 01:04:16 PM PDT 24
Peak memory 210440 kb
Host smart-3334d79a-359a-474e-8fc4-dd6caf260e8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703315679 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.1703315679
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3371952678
Short name T82
Test name
Test status
Simulation time 22466103407 ps
CPU time 17.15 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:51 PM PDT 24
Peak memory 201404 kb
Host smart-8943c7bd-cb91-41a8-95fe-90e2ead7981a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371952678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3371952678
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1767205274
Short name T3
Test name
Test status
Simulation time 208566788872 ps
CPU time 156.24 seconds
Started Apr 02 01:04:22 PM PDT 24
Finished Apr 02 01:06:59 PM PDT 24
Peak memory 210612 kb
Host smart-d6106ef0-f89d-444c-a758-dd68f8b49928
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767205274 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.1767205274
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2526566762
Short name T55
Test name
Test status
Simulation time 37927207838 ps
CPU time 108.67 seconds
Started Apr 02 01:02:34 PM PDT 24
Finished Apr 02 01:04:23 PM PDT 24
Peak memory 201908 kb
Host smart-51b0067d-b89f-4aaf-aa3d-e975d3b81dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526566762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.2526566762
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.1600323077
Short name T95
Test name
Test status
Simulation time 151724224956 ps
CPU time 419.66 seconds
Started Apr 02 01:04:21 PM PDT 24
Finished Apr 02 01:11:21 PM PDT 24
Peak memory 202148 kb
Host smart-55da2a25-3b18-4e59-8972-6149220735d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600323077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.1600323077
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.1122076697
Short name T203
Test name
Test status
Simulation time 128711396170 ps
CPU time 94.38 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:04:50 PM PDT 24
Peak memory 202168 kb
Host smart-5ddc2295-19d9-4897-886b-a357c70a9beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122076697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.1122076697
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.2104986566
Short name T364
Test name
Test status
Simulation time 2025560775 ps
CPU time 3.19 seconds
Started Apr 02 01:02:36 PM PDT 24
Finished Apr 02 01:02:40 PM PDT 24
Peak memory 201876 kb
Host smart-25756037-10b2-447d-a109-4abdb2c2abc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104986566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.2104986566
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2402919289
Short name T138
Test name
Test status
Simulation time 177460095154 ps
CPU time 108.57 seconds
Started Apr 02 01:05:17 PM PDT 24
Finished Apr 02 01:07:06 PM PDT 24
Peak memory 218692 kb
Host smart-ddfd24ea-6d5f-446f-b473-d75ce1ffeb0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402919289 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.2402919289
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2406653084
Short name T86
Test name
Test status
Simulation time 2155369164 ps
CPU time 8.48 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 201388 kb
Host smart-10265054-6d7b-4130-8327-a33fe8c7a48b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406653084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.2406653084
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3596411857
Short name T102
Test name
Test status
Simulation time 1024442080784 ps
CPU time 242.6 seconds
Started Apr 02 01:05:40 PM PDT 24
Finished Apr 02 01:09:43 PM PDT 24
Peak memory 218644 kb
Host smart-0b5e5306-918e-438d-b068-5a8f2ace82f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596411857 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3596411857
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1402870906
Short name T185
Test name
Test status
Simulation time 77522662733 ps
CPU time 57.42 seconds
Started Apr 02 01:02:33 PM PDT 24
Finished Apr 02 01:03:31 PM PDT 24
Peak memory 210456 kb
Host smart-0e8ea81e-4853-457e-beff-9c5b04b82f10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402870906 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.1402870906
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1086099692
Short name T280
Test name
Test status
Simulation time 2083677936 ps
CPU time 1.4 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 201288 kb
Host smart-10300800-3bd2-4261-8956-6cc25f449a51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086099692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.1086099692
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4106613967
Short name T13
Test name
Test status
Simulation time 85653546365 ps
CPU time 50.64 seconds
Started Apr 02 01:04:51 PM PDT 24
Finished Apr 02 01:05:43 PM PDT 24
Peak memory 202212 kb
Host smart-50d25057-954f-46a1-bb5e-e6e5932f7e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106613967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.4106613967
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1016431201
Short name T346
Test name
Test status
Simulation time 84677393636 ps
CPU time 75.31 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:06:27 PM PDT 24
Peak memory 215836 kb
Host smart-db087434-963f-4c37-aa10-559b238e573a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016431201 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1016431201
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.2301997309
Short name T257
Test name
Test status
Simulation time 22015449475 ps
CPU time 31.09 seconds
Started Apr 02 01:02:31 PM PDT 24
Finished Apr 02 01:03:03 PM PDT 24
Peak memory 221428 kb
Host smart-a37797b9-e459-4d19-be65-cf8fee7f4965
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301997309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.2301997309
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3589452543
Short name T42
Test name
Test status
Simulation time 135086806286 ps
CPU time 36.87 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:58 PM PDT 24
Peak memory 202192 kb
Host smart-a7e43b02-baf4-443a-979d-c1909e9b4846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589452543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.3589452543
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.849240044
Short name T34
Test name
Test status
Simulation time 69577669715 ps
CPU time 44.66 seconds
Started Apr 02 01:03:42 PM PDT 24
Finished Apr 02 01:04:27 PM PDT 24
Peak memory 210524 kb
Host smart-893afdad-4df9-465d-9dcd-5d5f1c0714ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849240044 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.849240044
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3192939854
Short name T83
Test name
Test status
Simulation time 22485467632 ps
CPU time 14.85 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:49 PM PDT 24
Peak memory 201432 kb
Host smart-69f41ebb-7417-4dc0-9656-fdf8a49ab863
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192939854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.3192939854
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3011650713
Short name T21
Test name
Test status
Simulation time 2049509939 ps
CPU time 6.68 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:48 PM PDT 24
Peak memory 201332 kb
Host smart-7b58b3da-a5df-4533-9ade-3bdce23076c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011650713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3011650713
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.4017957660
Short name T304
Test name
Test status
Simulation time 208698514139 ps
CPU time 558.34 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:14:30 PM PDT 24
Peak memory 202212 kb
Host smart-4b8f8277-2db7-4a64-89ce-50c2d8133e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017957660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.4017957660
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.1726819374
Short name T305
Test name
Test status
Simulation time 92078635391 ps
CPU time 69.58 seconds
Started Apr 02 01:03:55 PM PDT 24
Finished Apr 02 01:05:07 PM PDT 24
Peak memory 202136 kb
Host smart-a7097d4b-f252-4670-95c9-2ac24ac7c551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726819374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.1726819374
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.3200996148
Short name T123
Test name
Test status
Simulation time 104266820583 ps
CPU time 251.14 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:07:27 PM PDT 24
Peak memory 202180 kb
Host smart-bc764342-413e-407d-9602-1aab9d746963
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200996148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.3200996148
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.3387025169
Short name T298
Test name
Test status
Simulation time 47612734343 ps
CPU time 91.93 seconds
Started Apr 02 01:02:36 PM PDT 24
Finished Apr 02 01:04:08 PM PDT 24
Peak memory 202252 kb
Host smart-8c300b0d-3e7b-4dd6-829d-3e9b22d0898a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387025169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.3387025169
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2881914668
Short name T277
Test name
Test status
Simulation time 222054377052 ps
CPU time 121.99 seconds
Started Apr 02 01:02:48 PM PDT 24
Finished Apr 02 01:04:51 PM PDT 24
Peak memory 210520 kb
Host smart-d99d4100-1a36-4ae5-86bc-a7dbfba89937
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881914668 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2881914668
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.3190939582
Short name T116
Test name
Test status
Simulation time 2516335938 ps
CPU time 3.98 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:04:40 PM PDT 24
Peak memory 201924 kb
Host smart-8cd6a3b4-2ebe-450d-8fb5-0e773162a39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190939582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3190939582
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.777105239
Short name T306
Test name
Test status
Simulation time 121753748583 ps
CPU time 320.43 seconds
Started Apr 02 01:05:04 PM PDT 24
Finished Apr 02 01:10:25 PM PDT 24
Peak memory 202168 kb
Host smart-58ca6334-aadf-4a1f-85e4-64f58df49f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777105239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi
th_pre_cond.777105239
Directory /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.915477604
Short name T307
Test name
Test status
Simulation time 123097277476 ps
CPU time 82.73 seconds
Started Apr 02 01:05:45 PM PDT 24
Finished Apr 02 01:07:08 PM PDT 24
Peak memory 202204 kb
Host smart-f60192e6-fdcc-4bc4-b881-74bad055f745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915477604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_wi
th_pre_cond.915477604
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.2782630760
Short name T165
Test name
Test status
Simulation time 2391584377 ps
CPU time 3.64 seconds
Started Apr 02 01:05:29 PM PDT 24
Finished Apr 02 01:05:33 PM PDT 24
Peak memory 201948 kb
Host smart-ebd7e394-290b-44dd-b7c4-513efd8c5df0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782630760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.2782630760
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3250871370
Short name T96
Test name
Test status
Simulation time 4037253847 ps
CPU time 2.28 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:03:17 PM PDT 24
Peak memory 201896 kb
Host smart-a395a4ae-5dee-4257-a2a1-b2515a93e2d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250871370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3250871370
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2091608289
Short name T222
Test name
Test status
Simulation time 525307757500 ps
CPU time 101.3 seconds
Started Apr 02 01:05:13 PM PDT 24
Finished Apr 02 01:06:55 PM PDT 24
Peak memory 202396 kb
Host smart-543db186-cdf7-415e-988e-c83ae22dc92a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091608289 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2091608289
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.710456806
Short name T148
Test name
Test status
Simulation time 45737833180 ps
CPU time 131.35 seconds
Started Apr 02 01:05:19 PM PDT 24
Finished Apr 02 01:07:30 PM PDT 24
Peak memory 218516 kb
Host smart-52d8ef32-cc09-4448-b14c-c59a02423d0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710456806 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.710456806
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2095527871
Short name T336
Test name
Test status
Simulation time 42385663503 ps
CPU time 111.95 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:32:25 PM PDT 24
Peak memory 201460 kb
Host smart-c6c49627-cf66-4da0-bd30-9bdf7ab708c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095527871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.2095527871
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1008739222
Short name T319
Test name
Test status
Simulation time 69275621416 ps
CPU time 46.95 seconds
Started Apr 02 01:05:31 PM PDT 24
Finished Apr 02 01:06:19 PM PDT 24
Peak memory 202088 kb
Host smart-d2d7677c-2455-40d7-9278-3275ec72f60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008739222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.1008739222
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1796673980
Short name T323
Test name
Test status
Simulation time 102194460510 ps
CPU time 95.83 seconds
Started Apr 02 01:05:44 PM PDT 24
Finished Apr 02 01:07:20 PM PDT 24
Peak memory 202144 kb
Host smart-25158dd1-7e4f-493a-a542-bc97f43d7499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796673980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w
ith_pre_cond.1796673980
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3932912237
Short name T91
Test name
Test status
Simulation time 2167626323 ps
CPU time 5.54 seconds
Started Apr 02 12:30:28 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 201504 kb
Host smart-5d9f8001-0b92-4631-ab36-98c64894f991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932912237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.3932912237
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.1512832220
Short name T193
Test name
Test status
Simulation time 14526934025 ps
CPU time 20.08 seconds
Started Apr 02 01:03:33 PM PDT 24
Finished Apr 02 01:03:53 PM PDT 24
Peak memory 201940 kb
Host smart-1d6b12cb-9445-4223-8781-69d745892afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512832220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.1512832220
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.3325104460
Short name T220
Test name
Test status
Simulation time 4854445101 ps
CPU time 5.94 seconds
Started Apr 02 01:04:07 PM PDT 24
Finished Apr 02 01:04:13 PM PDT 24
Peak memory 201912 kb
Host smart-d9eb63df-b284-49fd-9e03-490f3a83b06d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325104460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_edge_detect.3325104460
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.1778590504
Short name T166
Test name
Test status
Simulation time 3730673369 ps
CPU time 10.16 seconds
Started Apr 02 01:05:20 PM PDT 24
Finished Apr 02 01:05:30 PM PDT 24
Peak memory 201964 kb
Host smart-13b0ff84-1acf-4b5f-a2a0-afe58884dd51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778590504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.1778590504
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2977822842
Short name T156
Test name
Test status
Simulation time 244974596817 ps
CPU time 304.78 seconds
Started Apr 02 01:05:25 PM PDT 24
Finished Apr 02 01:10:30 PM PDT 24
Peak memory 201848 kb
Host smart-ef817bae-3a10-449e-b798-cc6a7fde81ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977822842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.2977822842
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.1226898963
Short name T256
Test name
Test status
Simulation time 105434379690 ps
CPU time 41.6 seconds
Started Apr 02 01:03:28 PM PDT 24
Finished Apr 02 01:04:10 PM PDT 24
Peak memory 202236 kb
Host smart-67934aa2-da2a-43da-a77f-d6f226e20add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226898963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s
tress_all.1226898963
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3468024186
Short name T312
Test name
Test status
Simulation time 30515556138 ps
CPU time 65.88 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:05:30 PM PDT 24
Peak memory 202160 kb
Host smart-ab04638d-5a49-4029-bc81-70596bdd9129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468024186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.3468024186
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2939788441
Short name T94
Test name
Test status
Simulation time 44432599428 ps
CPU time 32.99 seconds
Started Apr 02 01:04:31 PM PDT 24
Finished Apr 02 01:05:06 PM PDT 24
Peak memory 202180 kb
Host smart-d90994cf-45e8-40b6-a64e-5b418bad64ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939788441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.2939788441
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1997628306
Short name T321
Test name
Test status
Simulation time 193054970774 ps
CPU time 263.17 seconds
Started Apr 02 01:05:04 PM PDT 24
Finished Apr 02 01:09:27 PM PDT 24
Peak memory 202096 kb
Host smart-f5005c18-8783-43a3-bfd1-5847cb6aad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997628306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.1997628306
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.558933232
Short name T316
Test name
Test status
Simulation time 55384356454 ps
CPU time 155 seconds
Started Apr 02 01:05:44 PM PDT 24
Finished Apr 02 01:08:20 PM PDT 24
Peak memory 202124 kb
Host smart-3e0a41cd-6ea0-4868-9659-e19d16deb198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558933232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_wi
th_pre_cond.558933232
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1250954466
Short name T314
Test name
Test status
Simulation time 145405176628 ps
CPU time 96.15 seconds
Started Apr 02 01:05:45 PM PDT 24
Finished Apr 02 01:07:21 PM PDT 24
Peak memory 202184 kb
Host smart-3a51b6c7-7adc-45c1-bd18-dd6bbfea088d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250954466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.1250954466
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2524946930
Short name T344
Test name
Test status
Simulation time 61364243393 ps
CPU time 39.24 seconds
Started Apr 02 01:05:49 PM PDT 24
Finished Apr 02 01:06:28 PM PDT 24
Peak memory 202096 kb
Host smart-b329cf47-0f0a-4d8a-92ed-fb2929adf55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524946930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.2524946930
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.5322290
Short name T30
Test name
Test status
Simulation time 35067159186 ps
CPU time 94.05 seconds
Started Apr 02 01:05:41 PM PDT 24
Finished Apr 02 01:07:15 PM PDT 24
Peak memory 202224 kb
Host smart-68902475-7a4e-4b21-88c0-d03ea50a8841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5322290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_with
_pre_cond.5322290
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4201025688
Short name T97
Test name
Test status
Simulation time 102801165935 ps
CPU time 29.23 seconds
Started Apr 02 01:05:44 PM PDT 24
Finished Apr 02 01:06:14 PM PDT 24
Peak memory 202128 kb
Host smart-01c96e4e-0bb3-49e6-a7f6-74afb565bb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201025688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.4201025688
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1516368370
Short name T98
Test name
Test status
Simulation time 108389314739 ps
CPU time 283.46 seconds
Started Apr 02 01:05:49 PM PDT 24
Finished Apr 02 01:10:32 PM PDT 24
Peak memory 202176 kb
Host smart-744335ff-e7d5-410e-acd5-11acaa9bc8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516368370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.1516368370
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.163224990
Short name T282
Test name
Test status
Simulation time 2766170445 ps
CPU time 10.79 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 201476 kb
Host smart-741347a2-acc1-4136-83a3-8930c57a0d10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163224990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_aliasing.163224990
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2983430264
Short name T285
Test name
Test status
Simulation time 40964097458 ps
CPU time 34.07 seconds
Started Apr 02 12:30:28 PM PDT 24
Finished Apr 02 12:31:02 PM PDT 24
Peak memory 201440 kb
Host smart-5b12c8e3-a46c-47a3-871b-bf568f82498d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983430264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.2983430264
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3587347321
Short name T281
Test name
Test status
Simulation time 4048554386 ps
CPU time 2.82 seconds
Started Apr 02 12:30:29 PM PDT 24
Finished Apr 02 12:30:32 PM PDT 24
Peak memory 201396 kb
Host smart-4d5fec05-8f14-473c-84e0-5537468b1205
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587347321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.3587347321
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2206671800
Short name T847
Test name
Test status
Simulation time 2067073462 ps
CPU time 6.49 seconds
Started Apr 02 12:30:29 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 201240 kb
Host smart-49801339-770d-4efa-8c8e-5617176a1350
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206671800 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2206671800
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2970906508
Short name T278
Test name
Test status
Simulation time 2067078661 ps
CPU time 1.98 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 201216 kb
Host smart-cb837bea-fbfe-4f5f-ab99-1a024b093d11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970906508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.2970906508
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1803385289
Short name T854
Test name
Test status
Simulation time 2013779728 ps
CPU time 5.98 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 200784 kb
Host smart-3f3f5f28-ca15-4730-b4a4-dc627239a98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803385289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.1803385289
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.425504580
Short name T905
Test name
Test status
Simulation time 9491232229 ps
CPU time 11.02 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:46 PM PDT 24
Peak memory 201464 kb
Host smart-0579ce12-a84f-4422-a606-74616d776b32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425504580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
sysrst_ctrl_same_csr_outstanding.425504580
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2135714818
Short name T866
Test name
Test status
Simulation time 2061289903 ps
CPU time 6.62 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 201328 kb
Host smart-acd16961-f06a-493a-b736-ede1cf21ee91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135714818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.2135714818
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.168402852
Short name T28
Test name
Test status
Simulation time 22468170785 ps
CPU time 16.18 seconds
Started Apr 02 12:30:27 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 201428 kb
Host smart-f766b574-7b55-43b4-8e8b-cfbe56ef5958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168402852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_tl_intg_err.168402852
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2986191451
Short name T882
Test name
Test status
Simulation time 2519768229 ps
CPU time 4.46 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 201404 kb
Host smart-8afbf5a4-8788-4d14-bb32-8c9785f90fcf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986191451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.2986191451
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.846073598
Short name T290
Test name
Test status
Simulation time 46760851434 ps
CPU time 175.09 seconds
Started Apr 02 12:30:30 PM PDT 24
Finished Apr 02 12:33:25 PM PDT 24
Peak memory 201428 kb
Host smart-6a4ee20d-7335-4e19-858e-010885195039
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846073598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_bit_bash.846073598
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2091186604
Short name T852
Test name
Test status
Simulation time 4072555050 ps
CPU time 1.92 seconds
Started Apr 02 12:30:29 PM PDT 24
Finished Apr 02 12:30:31 PM PDT 24
Peak memory 201268 kb
Host smart-1218938c-1d8a-4b3a-a475-519300e28361
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091186604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.2091186604
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1866546914
Short name T29
Test name
Test status
Simulation time 2088368492 ps
CPU time 2.47 seconds
Started Apr 02 12:30:29 PM PDT 24
Finished Apr 02 12:30:31 PM PDT 24
Peak memory 201292 kb
Host smart-0440ee7c-5878-4e44-81e9-f30c48a594f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866546914 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1866546914
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2631911993
Short name T284
Test name
Test status
Simulation time 2034884020 ps
CPU time 5.85 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201228 kb
Host smart-784e4517-c6bb-4e06-bfe4-bdea3d48f9aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631911993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2631911993
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.987384086
Short name T875
Test name
Test status
Simulation time 2021309358 ps
CPU time 2.36 seconds
Started Apr 02 12:30:29 PM PDT 24
Finished Apr 02 12:30:32 PM PDT 24
Peak memory 200888 kb
Host smart-ca862433-a6e4-410c-9124-3f131b3ab962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987384086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test
.987384086
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2650431665
Short name T895
Test name
Test status
Simulation time 5151011362 ps
CPU time 5.9 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 201308 kb
Host smart-fc8b7397-6246-44f5-b544-495ef52bf93d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650431665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.2650431665
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.4266958174
Short name T841
Test name
Test status
Simulation time 42407446396 ps
CPU time 108.36 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:32:20 PM PDT 24
Peak memory 201476 kb
Host smart-0796f310-8616-4988-9ee2-a26c20325f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266958174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.4266958174
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2288572757
Short name T837
Test name
Test status
Simulation time 2149249058 ps
CPU time 3.86 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 201536 kb
Host smart-96f3ddb4-3bd2-41bd-b639-91e048dacd5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288572757 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2288572757
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3799700838
Short name T793
Test name
Test status
Simulation time 2021255442 ps
CPU time 3.07 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 200860 kb
Host smart-180304d7-0ed2-49cf-a0f1-ca8fcbe34e0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799700838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.3799700838
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.3381590184
Short name T864
Test name
Test status
Simulation time 10581992958 ps
CPU time 3.39 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 201448 kb
Host smart-33c90030-9537-46c5-ab90-d7235ae911ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381590184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
0.sysrst_ctrl_same_csr_outstanding.3381590184
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2716655627
Short name T89
Test name
Test status
Simulation time 2722413432 ps
CPU time 2.14 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 201448 kb
Host smart-48f1d78e-87b2-4241-a66a-b31ec239196d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716655627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.2716655627
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2350502352
Short name T331
Test name
Test status
Simulation time 22231298772 ps
CPU time 32.61 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:31:05 PM PDT 24
Peak memory 201468 kb
Host smart-e91e10fc-9d2e-46f4-8ca7-098463f354a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350502352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.2350502352
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1978918179
Short name T908
Test name
Test status
Simulation time 2117918528 ps
CPU time 6.27 seconds
Started Apr 02 12:30:48 PM PDT 24
Finished Apr 02 12:30:54 PM PDT 24
Peak memory 201384 kb
Host smart-b345fe10-927e-40a2-8640-0b7444fe1183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978918179 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1978918179
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1419497156
Short name T832
Test name
Test status
Simulation time 2039069724 ps
CPU time 5.98 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 201196 kb
Host smart-73df37d7-47ab-4720-9300-133ce48fd085
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419497156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.1419497156
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.402841503
Short name T834
Test name
Test status
Simulation time 2014555829 ps
CPU time 5.83 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 200732 kb
Host smart-ffbae239-d38e-4533-9852-70a8cd9d18f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402841503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.402841503
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.443881738
Short name T23
Test name
Test status
Simulation time 4703686701 ps
CPU time 6.81 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 201404 kb
Host smart-5b802e0b-ad39-44bd-8f76-f4eb0870c698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443881738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_same_csr_outstanding.443881738
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2695193246
Short name T842
Test name
Test status
Simulation time 2339975751 ps
CPU time 3.16 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 201364 kb
Host smart-58a703e6-0a97-47a1-ad1e-b28aee8c80d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695193246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2695193246
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.137589404
Short name T335
Test name
Test status
Simulation time 22217242981 ps
CPU time 57.09 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 201488 kb
Host smart-3d87d06f-555e-4123-9300-f5705a9a1dce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137589404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_tl_intg_err.137589404
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.96901609
Short name T857
Test name
Test status
Simulation time 2115841170 ps
CPU time 2.23 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 201228 kb
Host smart-39de1927-1dc0-4778-944d-f29c4145824a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96901609 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.96901609
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2358786724
Short name T902
Test name
Test status
Simulation time 2048995930 ps
CPU time 3.29 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 201212 kb
Host smart-709a16bd-1bfd-420e-8ce2-36e502f878c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358786724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.2358786724
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2081657114
Short name T861
Test name
Test status
Simulation time 2012514346 ps
CPU time 5.83 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 200800 kb
Host smart-909e4d7e-65f7-4509-9f26-e0584e095145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081657114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.2081657114
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1837804137
Short name T876
Test name
Test status
Simulation time 4779323891 ps
CPU time 1.95 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 201428 kb
Host smart-57c47a9f-dab7-4c21-9a1e-818cba5e93b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837804137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.1837804137
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4111808756
Short name T833
Test name
Test status
Simulation time 2167306437 ps
CPU time 2.61 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201344 kb
Host smart-b02d36be-4504-4b7d-bf37-48a5c202b302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111808756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.4111808756
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1947398132
Short name T332
Test name
Test status
Simulation time 22241512073 ps
CPU time 60.69 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:31:37 PM PDT 24
Peak memory 201476 kb
Host smart-f2a5c3ef-621d-4e09-a813-a32bc8861bac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947398132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.1947398132
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.529282236
Short name T821
Test name
Test status
Simulation time 2067289212 ps
CPU time 5.9 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 201232 kb
Host smart-90fc249d-ad30-466c-930a-62ee34054e03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529282236 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.529282236
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2693595993
Short name T292
Test name
Test status
Simulation time 2071038739 ps
CPU time 1.44 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 201156 kb
Host smart-0ef28ed9-ed46-46ac-abe6-5c0ef3f0440c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693595993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.2693595993
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2748371198
Short name T825
Test name
Test status
Simulation time 2200354117 ps
CPU time 0.94 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 200764 kb
Host smart-c82bf581-a562-4dd5-9642-ca8fd653ddcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748371198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.2748371198
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1603288624
Short name T867
Test name
Test status
Simulation time 9190443295 ps
CPU time 24.3 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:58 PM PDT 24
Peak memory 201596 kb
Host smart-8f773310-3009-4bf7-9f54-8942b24bcdf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603288624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.1603288624
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.928749617
Short name T883
Test name
Test status
Simulation time 2258892882 ps
CPU time 2.92 seconds
Started Apr 02 12:30:30 PM PDT 24
Finished Apr 02 12:30:33 PM PDT 24
Peak memory 201448 kb
Host smart-78416343-f635-4f1f-bb16-076081d1cfa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928749617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_error
s.928749617
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1999909887
Short name T901
Test name
Test status
Simulation time 22236776228 ps
CPU time 55.84 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 201452 kb
Host smart-cbab8e71-cd41-4b83-8a87-9ca206e0b270
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999909887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.1999909887
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1568484220
Short name T887
Test name
Test status
Simulation time 2108822779 ps
CPU time 6.77 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201392 kb
Host smart-20901acb-605a-461f-9d91-1d2ac8124923
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568484220 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1568484220
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2270174280
Short name T87
Test name
Test status
Simulation time 2050891620 ps
CPU time 3.25 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 201360 kb
Host smart-68a1d410-8dbe-4123-b4ac-0bcdf2c25813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270174280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.2270174280
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.232480243
Short name T820
Test name
Test status
Simulation time 2012492253 ps
CPU time 5.9 seconds
Started Apr 02 12:31:26 PM PDT 24
Finished Apr 02 12:31:32 PM PDT 24
Peak memory 200692 kb
Host smart-e3e38eca-9fde-47df-8152-ee6851b34763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232480243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_tes
t.232480243
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3383321723
Short name T840
Test name
Test status
Simulation time 4591672690 ps
CPU time 9.82 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 201324 kb
Host smart-03340616-5e90-417a-a3df-67998d9ed39c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383321723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.3383321723
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3534658492
Short name T818
Test name
Test status
Simulation time 2057671291 ps
CPU time 6.77 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 201404 kb
Host smart-dbf86895-a334-444c-9203-d07b772d7d86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534658492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.3534658492
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3639197064
Short name T845
Test name
Test status
Simulation time 22185592486 ps
CPU time 59.58 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:31:34 PM PDT 24
Peak memory 201496 kb
Host smart-3314c009-8e07-4e24-bfd3-cb235f2fcacc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639197064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.3639197064
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.60479595
Short name T829
Test name
Test status
Simulation time 2141325500 ps
CPU time 3.5 seconds
Started Apr 02 12:31:23 PM PDT 24
Finished Apr 02 12:31:27 PM PDT 24
Peak memory 201256 kb
Host smart-f3e40724-2ba1-4e44-8bf6-35e0d90d9cb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60479595 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.60479595
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.312859312
Short name T287
Test name
Test status
Simulation time 2068591437 ps
CPU time 2.22 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201336 kb
Host smart-7e949491-ea49-4c68-8779-31d184e259d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312859312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_r
w.312859312
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3988919954
Short name T880
Test name
Test status
Simulation time 2044057906 ps
CPU time 1.91 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 200732 kb
Host smart-2f173e5a-b036-4967-abb2-1c598c4471d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988919954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.3988919954
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4062164539
Short name T849
Test name
Test status
Simulation time 4658381237 ps
CPU time 16.04 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:48 PM PDT 24
Peak memory 201464 kb
Host smart-3f5b30d2-1889-4f06-9ff5-b214cd355f90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062164539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.4062164539
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3356103675
Short name T810
Test name
Test status
Simulation time 2849793494 ps
CPU time 2.63 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201344 kb
Host smart-0fcd4398-f966-4e62-bfbe-2df5164bfec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356103675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.3356103675
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3294296257
Short name T859
Test name
Test status
Simulation time 42500914952 ps
CPU time 30.87 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:31:08 PM PDT 24
Peak memory 201484 kb
Host smart-aefaf5aa-8879-44fb-87ab-6e9d6affb067
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294296257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.3294296257
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1785121041
Short name T906
Test name
Test status
Simulation time 2372175092 ps
CPU time 1.8 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 201308 kb
Host smart-b2c943ce-b4ec-44b6-a61c-08183e3119b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785121041 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1785121041
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3418199787
Short name T889
Test name
Test status
Simulation time 2040345712 ps
CPU time 3.36 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 201160 kb
Host smart-9265e8f9-da03-4ee7-ae1b-398ebce6c607
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418199787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.3418199787
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.683555476
Short name T881
Test name
Test status
Simulation time 2048215526 ps
CPU time 1.76 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 200732 kb
Host smart-1a111f57-d59b-4b50-9cfe-fd37488ed369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683555476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_tes
t.683555476
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.358418724
Short name T835
Test name
Test status
Simulation time 6858512887 ps
CPU time 28.01 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:31:05 PM PDT 24
Peak memory 201432 kb
Host smart-8fc4b28d-e429-4402-b15b-bf8cc671ba00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358418724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.sysrst_ctrl_same_csr_outstanding.358418724
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2170936126
Short name T92
Test name
Test status
Simulation time 2119728790 ps
CPU time 3.97 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 201428 kb
Host smart-36993aff-b3c7-4a9a-a613-c1445169bd95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170936126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.2170936126
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.875787545
Short name T846
Test name
Test status
Simulation time 2057390284 ps
CPU time 6.13 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 201256 kb
Host smart-04ba093f-f8dd-4acb-b7cc-5c3ae96217b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875787545 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.875787545
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3795568200
Short name T813
Test name
Test status
Simulation time 2054535711 ps
CPU time 2.27 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201272 kb
Host smart-2591a121-5ed6-477d-8629-41fdee389721
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795568200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.3795568200
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3156399612
Short name T790
Test name
Test status
Simulation time 2018202112 ps
CPU time 3.12 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 200668 kb
Host smart-65dc04f8-dec0-4b20-ad85-6458ae6f2f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156399612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3156399612
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.218842467
Short name T893
Test name
Test status
Simulation time 4776099561 ps
CPU time 16.98 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:55 PM PDT 24
Peak memory 201440 kb
Host smart-f94192f9-8f12-4160-bbd2-b98def699232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218842467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_same_csr_outstanding.218842467
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3722714822
Short name T822
Test name
Test status
Simulation time 2065877343 ps
CPU time 6.75 seconds
Started Apr 02 12:30:39 PM PDT 24
Finished Apr 02 12:30:46 PM PDT 24
Peak memory 201344 kb
Host smart-36281c17-c722-4dc1-993b-69fabf7a40ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722714822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.3722714822
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2933016894
Short name T341
Test name
Test status
Simulation time 2081445682 ps
CPU time 5.82 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 201288 kb
Host smart-92fb5e3c-c3c8-48b2-a132-d8648499c9f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933016894 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2933016894
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2663028475
Short name T858
Test name
Test status
Simulation time 2009488350 ps
CPU time 5.86 seconds
Started Apr 02 12:30:28 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 200784 kb
Host smart-2be962cc-79f2-40ee-b77b-cc49ac6e7ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663028475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te
st.2663028475
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3547102229
Short name T900
Test name
Test status
Simulation time 4487223063 ps
CPU time 3.15 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:45 PM PDT 24
Peak memory 201332 kb
Host smart-6295b003-dee9-4de4-8698-6de0c25c9592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547102229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.3547102229
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.518896687
Short name T868
Test name
Test status
Simulation time 22287175598 ps
CPU time 29.49 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:31:02 PM PDT 24
Peak memory 201404 kb
Host smart-2d266f58-6994-4c41-970a-9317ab0078f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518896687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_tl_intg_err.518896687
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.860317173
Short name T90
Test name
Test status
Simulation time 2171115538 ps
CPU time 2.63 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 201296 kb
Host smart-c2ab4852-f33e-4551-aea0-88f4d7a67e02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860317173 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.860317173
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.4263915300
Short name T291
Test name
Test status
Simulation time 2056880533 ps
CPU time 3.64 seconds
Started Apr 02 12:30:30 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 201216 kb
Host smart-69f6728c-3e09-4d50-bd03-7b34904be379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263915300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.4263915300
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4060480102
Short name T898
Test name
Test status
Simulation time 2042205906 ps
CPU time 1.9 seconds
Started Apr 02 12:31:25 PM PDT 24
Finished Apr 02 12:31:28 PM PDT 24
Peak memory 200688 kb
Host smart-96f913f3-ea61-48ba-889b-46a25f44b8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060480102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.4060480102
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1809361263
Short name T871
Test name
Test status
Simulation time 8689983497 ps
CPU time 12.78 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:46 PM PDT 24
Peak memory 201436 kb
Host smart-c30f61f9-8f76-480d-aa13-20c0acb4da9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809361263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.1809361263
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1773461334
Short name T803
Test name
Test status
Simulation time 2190562356 ps
CPU time 4.69 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201756 kb
Host smart-6a18f72c-25e3-4096-8261-f315c052b92c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773461334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.1773461334
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.1590971083
Short name T334
Test name
Test status
Simulation time 22207846138 ps
CPU time 29.97 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:31:07 PM PDT 24
Peak memory 201496 kb
Host smart-fcd18521-6adf-48e3-aa62-129e381061bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590971083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.1590971083
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2318129754
Short name T862
Test name
Test status
Simulation time 2674899596 ps
CPU time 8.74 seconds
Started Apr 02 12:30:30 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201388 kb
Host smart-557576db-8926-45e2-a4fe-8e1e0eaa7ba8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318129754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.2318129754
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.710662394
Short name T870
Test name
Test status
Simulation time 38824265994 ps
CPU time 44.99 seconds
Started Apr 02 12:30:25 PM PDT 24
Finished Apr 02 12:31:10 PM PDT 24
Peak memory 201428 kb
Host smart-24f31a43-e353-43e1-b3bb-5eb84930d3ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710662394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_
csr_bit_bash.710662394
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3197088124
Short name T860
Test name
Test status
Simulation time 4024105854 ps
CPU time 5.58 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 201264 kb
Host smart-f79d2ace-53e8-47b5-9100-844c0f18fd86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197088124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.3197088124
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1243325199
Short name T848
Test name
Test status
Simulation time 2079454383 ps
CPU time 4.44 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201244 kb
Host smart-33bec71a-413c-43c0-9e38-9d4c0674ff4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243325199 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1243325199
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1916453785
Short name T288
Test name
Test status
Simulation time 2067065649 ps
CPU time 2.27 seconds
Started Apr 02 12:30:29 PM PDT 24
Finished Apr 02 12:30:32 PM PDT 24
Peak memory 201332 kb
Host smart-3bb7f3cc-c8b5-4721-920f-2c6d56e9a713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916453785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.1916453785
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3760559015
Short name T801
Test name
Test status
Simulation time 2034717829 ps
CPU time 1.84 seconds
Started Apr 02 12:30:27 PM PDT 24
Finished Apr 02 12:30:29 PM PDT 24
Peak memory 200772 kb
Host smart-f3ecca97-6c51-49f7-a041-e45103f39de0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760559015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.3760559015
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.67229018
Short name T22
Test name
Test status
Simulation time 9631473196 ps
CPU time 38.88 seconds
Started Apr 02 12:30:28 PM PDT 24
Finished Apr 02 12:31:07 PM PDT 24
Peak memory 201416 kb
Host smart-d14ce095-879a-4f5d-bfb1-39778e5ddcbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67229018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=
sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
ysrst_ctrl_same_csr_outstanding.67229018
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.686873158
Short name T78
Test name
Test status
Simulation time 2026464672 ps
CPU time 5.91 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 201312 kb
Host smart-66f93b47-b9fe-4c3d-b2fc-e49f1fd14f22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686873158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors
.686873158
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.4176524613
Short name T869
Test name
Test status
Simulation time 22237336012 ps
CPU time 57.36 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:31:35 PM PDT 24
Peak memory 201500 kb
Host smart-a6858af7-69d4-4f50-8b9c-30ff130d79e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176524613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.4176524613
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1545375806
Short name T804
Test name
Test status
Simulation time 2046412605 ps
CPU time 1.54 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 200780 kb
Host smart-d97d8010-bd65-4c6f-9670-469c5a0d92d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545375806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.1545375806
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3708716665
Short name T892
Test name
Test status
Simulation time 2032016527 ps
CPU time 2.89 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 200824 kb
Host smart-ed82db15-8422-4e59-8305-73c802a2453d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708716665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.3708716665
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4050757789
Short name T827
Test name
Test status
Simulation time 2012782375 ps
CPU time 5.67 seconds
Started Apr 02 12:30:41 PM PDT 24
Finished Apr 02 12:30:46 PM PDT 24
Peak memory 200668 kb
Host smart-bdb242de-239d-4963-a973-f00681bd3755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050757789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.4050757789
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3462853094
Short name T838
Test name
Test status
Simulation time 2036372755 ps
CPU time 1.65 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 200576 kb
Host smart-408c7cc2-4df8-48fb-b64a-6ecbc95a59fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462853094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.3462853094
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3719001060
Short name T789
Test name
Test status
Simulation time 2011729844 ps
CPU time 5.54 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 200808 kb
Host smart-2cc552f4-c421-4a0b-b4cb-4b7318dc8bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719001060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.3719001060
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.3692054334
Short name T798
Test name
Test status
Simulation time 2011717014 ps
CPU time 5.6 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 200732 kb
Host smart-3636a639-6f37-401a-bab8-19773888f34a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692054334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.3692054334
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3085475740
Short name T865
Test name
Test status
Simulation time 2013863072 ps
CPU time 5.75 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 200912 kb
Host smart-c8d4adc2-77db-4823-97db-d5205a186af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085475740 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.3085475740
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.481882763
Short name T796
Test name
Test status
Simulation time 2056060453 ps
CPU time 1.46 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 200788 kb
Host smart-8d2e6ec5-884d-4b77-b13f-079ee8f65ed0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481882763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_tes
t.481882763
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1921419836
Short name T896
Test name
Test status
Simulation time 2010443977 ps
CPU time 5.88 seconds
Started Apr 02 12:30:43 PM PDT 24
Finished Apr 02 12:30:49 PM PDT 24
Peak memory 200732 kb
Host smart-86130884-9547-4257-b505-5765c3d82a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921419836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.1921419836
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.714099173
Short name T791
Test name
Test status
Simulation time 2042547207 ps
CPU time 1.39 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:44 PM PDT 24
Peak memory 200932 kb
Host smart-79790264-fa70-48ef-ac62-e3c9cb2e5520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714099173 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_tes
t.714099173
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.551022111
Short name T340
Test name
Test status
Simulation time 2675877831 ps
CPU time 9.68 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 201368 kb
Host smart-7344a782-ec48-4bf6-9dd7-801b29cf94b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551022111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.551022111
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.4156899342
Short name T289
Test name
Test status
Simulation time 39246177845 ps
CPU time 55.98 seconds
Started Apr 02 12:30:25 PM PDT 24
Finished Apr 02 12:31:21 PM PDT 24
Peak memory 201448 kb
Host smart-bd92b827-9977-4b9f-a146-b8a36f70cf22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156899342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_bit_bash.4156899342
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3510413283
Short name T286
Test name
Test status
Simulation time 6297064185 ps
CPU time 1.77 seconds
Started Apr 02 12:30:16 PM PDT 24
Finished Apr 02 12:30:18 PM PDT 24
Peak memory 201360 kb
Host smart-31e0af5d-fe1d-425b-bbb1-61cca2d22712
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510413283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.3510413283
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1734347283
Short name T836
Test name
Test status
Simulation time 2098076853 ps
CPU time 3.89 seconds
Started Apr 02 12:30:29 PM PDT 24
Finished Apr 02 12:30:33 PM PDT 24
Peak memory 201444 kb
Host smart-86448eb9-ec70-48c0-aaf3-7a0693d07c21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734347283 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1734347283
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.569931306
Short name T850
Test name
Test status
Simulation time 2083607914 ps
CPU time 2.08 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 201264 kb
Host smart-577de3fb-56c3-4400-a4b8-d9259cec1a7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569931306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw
.569931306
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3934615458
Short name T816
Test name
Test status
Simulation time 2032960316 ps
CPU time 1.95 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 200760 kb
Host smart-87325e29-b63d-46ee-b76f-446e8bd4b4fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934615458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.3934615458
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3953533807
Short name T863
Test name
Test status
Simulation time 4521143235 ps
CPU time 6.42 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:44 PM PDT 24
Peak memory 201264 kb
Host smart-843f786f-6d4e-4c9c-be46-43cb78374a2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953533807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_same_csr_outstanding.3953533807
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1760936318
Short name T814
Test name
Test status
Simulation time 2156921573 ps
CPU time 7.5 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:40 PM PDT 24
Peak memory 201172 kb
Host smart-eab6a615-6566-4a4b-996d-bc259025fdbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760936318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.1760936318
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3543177361
Short name T903
Test name
Test status
Simulation time 42460283432 ps
CPU time 56.99 seconds
Started Apr 02 12:30:21 PM PDT 24
Finished Apr 02 12:31:18 PM PDT 24
Peak memory 201512 kb
Host smart-f54017ff-201d-4da9-854b-7f6b6361fb46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543177361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.3543177361
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3403896094
Short name T808
Test name
Test status
Simulation time 2009586877 ps
CPU time 5.46 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 200684 kb
Host smart-d057b044-8a8e-4670-800f-606d915e2bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403896094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.3403896094
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2257148664
Short name T844
Test name
Test status
Simulation time 2058612163 ps
CPU time 1.46 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 200564 kb
Host smart-c189bec4-854a-42c8-a7ee-e8e47bcd4986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257148664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2257148664
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3675450710
Short name T792
Test name
Test status
Simulation time 2019540956 ps
CPU time 2.91 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 200780 kb
Host smart-0cd2bdb2-f612-47d4-a667-7e42470c0d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675450710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.3675450710
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.4177685108
Short name T899
Test name
Test status
Simulation time 2032533398 ps
CPU time 2.02 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:44 PM PDT 24
Peak memory 200720 kb
Host smart-3719d2b8-08dc-4857-a903-2b865ab770bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177685108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.4177685108
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.335053987
Short name T843
Test name
Test status
Simulation time 2029425882 ps
CPU time 1.8 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 200660 kb
Host smart-977c30ee-20fb-40c5-a768-390528bf934a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335053987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_tes
t.335053987
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1507585064
Short name T819
Test name
Test status
Simulation time 2048395968 ps
CPU time 2.1 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 200780 kb
Host smart-1f3a275e-75e6-406e-8bcc-c6104b2539e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507585064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.1507585064
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.400307921
Short name T830
Test name
Test status
Simulation time 2046521071 ps
CPU time 1.98 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 200568 kb
Host smart-3092de1d-561c-4870-8002-300b466daf6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400307921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_tes
t.400307921
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2676299791
Short name T885
Test name
Test status
Simulation time 2014984776 ps
CPU time 5.99 seconds
Started Apr 02 12:30:30 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 200848 kb
Host smart-0007113f-ef69-47e0-bc44-654cdad45e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676299791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.2676299791
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.852632608
Short name T795
Test name
Test status
Simulation time 2025988836 ps
CPU time 2.57 seconds
Started Apr 02 12:31:12 PM PDT 24
Finished Apr 02 12:31:15 PM PDT 24
Peak memory 200700 kb
Host smart-0c29b25f-c402-48d9-84b1-f4f2a8fbc06a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852632608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_tes
t.852632608
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2497303030
Short name T853
Test name
Test status
Simulation time 2011161662 ps
CPU time 5.66 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 200856 kb
Host smart-8a4310a4-d56b-4940-ad5f-691022dac034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497303030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.2497303030
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.578542237
Short name T874
Test name
Test status
Simulation time 2510232863 ps
CPU time 7.15 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 201448 kb
Host smart-09ebd52e-ae4c-4f5f-9653-276c994dcfa2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578542237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_aliasing.578542237
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.808950805
Short name T295
Test name
Test status
Simulation time 37816864238 ps
CPU time 100.04 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:32:17 PM PDT 24
Peak memory 201412 kb
Host smart-d813e229-73f4-41ed-9c75-ca42f12cddbd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808950805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_bit_bash.808950805
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1984924825
Short name T839
Test name
Test status
Simulation time 6048467544 ps
CPU time 15.5 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 201344 kb
Host smart-f0702060-698f-4879-bb77-2ca1b52e82f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984924825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.1984924825
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.446952703
Short name T27
Test name
Test status
Simulation time 2165081683 ps
CPU time 3.69 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:36 PM PDT 24
Peak memory 201356 kb
Host smart-9172b5b0-11b8-4dd3-a328-9bfc9d40f3ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446952703 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.446952703
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3359518455
Short name T884
Test name
Test status
Simulation time 2095429082 ps
CPU time 2.18 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 201172 kb
Host smart-f8fc1d62-bcd7-46a7-b76c-7562ae676697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359518455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.3359518455
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3646115580
Short name T888
Test name
Test status
Simulation time 2014583254 ps
CPU time 5.75 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 200744 kb
Host smart-91c1c749-0718-4d8f-b265-7cc28d25b148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646115580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.3646115580
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.648857299
Short name T294
Test name
Test status
Simulation time 9273469041 ps
CPU time 14.83 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:47 PM PDT 24
Peak memory 201512 kb
Host smart-6a608ace-7599-4c84-82cb-7addb35e5560
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648857299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
sysrst_ctrl_same_csr_outstanding.648857299
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1562639252
Short name T815
Test name
Test status
Simulation time 2089432359 ps
CPU time 6.82 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 201264 kb
Host smart-02960b2e-3af9-42d6-9e92-6e3fc8e6369e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562639252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.1562639252
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3092068181
Short name T338
Test name
Test status
Simulation time 42589990486 ps
CPU time 26.58 seconds
Started Apr 02 12:30:30 PM PDT 24
Finished Apr 02 12:30:56 PM PDT 24
Peak memory 201464 kb
Host smart-c1d54193-4c3f-41ef-bc25-a54298bc3f15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092068181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_tl_intg_err.3092068181
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1179894970
Short name T873
Test name
Test status
Simulation time 2009681878 ps
CPU time 5.29 seconds
Started Apr 02 12:30:28 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 200872 kb
Host smart-eb70cd37-616b-45c8-a00a-ca275035912d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179894970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.1179894970
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2989883678
Short name T823
Test name
Test status
Simulation time 2012167485 ps
CPU time 5.59 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 200720 kb
Host smart-6f9c8169-6e28-4ead-88f7-f5e1d8e97544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989883678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.2989883678
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2427706286
Short name T794
Test name
Test status
Simulation time 2025653658 ps
CPU time 2.47 seconds
Started Apr 02 12:30:38 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 200796 kb
Host smart-8cacf3c9-7409-4630-99b1-f9e2a8d95e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427706286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.2427706286
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.1113080835
Short name T809
Test name
Test status
Simulation time 2048353971 ps
CPU time 2.22 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:30:35 PM PDT 24
Peak memory 200784 kb
Host smart-706257d4-14f0-401c-8183-171b9d4e7308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113080835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.1113080835
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.933863143
Short name T812
Test name
Test status
Simulation time 2038731401 ps
CPU time 2.02 seconds
Started Apr 02 12:30:58 PM PDT 24
Finished Apr 02 12:31:00 PM PDT 24
Peak memory 200696 kb
Host smart-bf845058-3713-4c4a-8c5e-89159fe5e2a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933863143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_tes
t.933863143
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.233697366
Short name T828
Test name
Test status
Simulation time 2022295144 ps
CPU time 3.3 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 200656 kb
Host smart-17a21e2d-c577-47b2-ade3-aae7990279dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233697366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_tes
t.233697366
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2503852315
Short name T855
Test name
Test status
Simulation time 2031370796 ps
CPU time 2.15 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 200772 kb
Host smart-01fa21e8-abd1-4c20-9bf9-143de1a41f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503852315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.2503852315
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.733744309
Short name T877
Test name
Test status
Simulation time 2018567876 ps
CPU time 4.18 seconds
Started Apr 02 12:31:02 PM PDT 24
Finished Apr 02 12:31:07 PM PDT 24
Peak memory 200828 kb
Host smart-d8818bcc-4f9b-450f-aa4a-facc0c84146a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733744309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_tes
t.733744309
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2316411597
Short name T800
Test name
Test status
Simulation time 2017905297 ps
CPU time 3.45 seconds
Started Apr 02 12:30:42 PM PDT 24
Finished Apr 02 12:30:51 PM PDT 24
Peak memory 200792 kb
Host smart-538bac56-ce92-4dc7-8d71-017094e5db5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316411597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te
st.2316411597
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1419283366
Short name T878
Test name
Test status
Simulation time 2038352718 ps
CPU time 2.06 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 200748 kb
Host smart-9bf9def4-4a63-416e-9f23-1e560b4ca148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419283366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.1419283366
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3026287847
Short name T811
Test name
Test status
Simulation time 2137394317 ps
CPU time 4.53 seconds
Started Apr 02 12:30:25 PM PDT 24
Finished Apr 02 12:30:30 PM PDT 24
Peak memory 201256 kb
Host smart-61be41dd-cd09-477b-8a66-4cfdc228f161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026287847 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3026287847
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.104984888
Short name T907
Test name
Test status
Simulation time 2028723778 ps
CPU time 5.92 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 201216 kb
Host smart-539faf09-a109-4f7b-86f9-4ae7a0b529d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104984888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw
.104984888
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2866972551
Short name T890
Test name
Test status
Simulation time 2020997999 ps
CPU time 3.15 seconds
Started Apr 02 12:30:27 PM PDT 24
Finished Apr 02 12:30:30 PM PDT 24
Peak memory 200792 kb
Host smart-a3c45595-b739-499f-9cbc-97cc5ea67d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866972551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.2866972551
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1173130408
Short name T851
Test name
Test status
Simulation time 4972736852 ps
CPU time 4.04 seconds
Started Apr 02 12:30:30 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 201472 kb
Host smart-fc613368-3e89-4417-8aa9-5f49cc8fc5ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173130408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.1173130408
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.156363194
Short name T77
Test name
Test status
Simulation time 2027956167 ps
CPU time 6.77 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 201392 kb
Host smart-26bfc788-901d-47e5-99a1-807c00711c04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156363194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors
.156363194
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2737210129
Short name T333
Test name
Test status
Simulation time 42542747601 ps
CPU time 58.75 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:31:31 PM PDT 24
Peak memory 201424 kb
Host smart-46f6ea04-8049-416f-81c5-58b57a90048f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737210129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.2737210129
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2376349872
Short name T799
Test name
Test status
Simulation time 2155021525 ps
CPU time 2.46 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 210416 kb
Host smart-1fe7f6bc-d8db-4ab0-90a2-11aef2aeef02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376349872 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2376349872
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3898247113
Short name T279
Test name
Test status
Simulation time 2042454204 ps
CPU time 2.82 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201216 kb
Host smart-24b3b46c-0788-4eb3-a773-b218c4216f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898247113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.3898247113
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.448288306
Short name T797
Test name
Test status
Simulation time 2030590476 ps
CPU time 2.12 seconds
Started Apr 02 12:30:28 PM PDT 24
Finished Apr 02 12:30:30 PM PDT 24
Peak memory 200724 kb
Host smart-87d93df9-6c61-4965-9fdc-115a57c565fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448288306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test
.448288306
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3565154845
Short name T826
Test name
Test status
Simulation time 7623471994 ps
CPU time 28.29 seconds
Started Apr 02 12:30:27 PM PDT 24
Finished Apr 02 12:31:00 PM PDT 24
Peak memory 201424 kb
Host smart-f5b53d52-f7a1-4553-b4a6-7eef3a04c812
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565154845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.3565154845
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.658218062
Short name T88
Test name
Test status
Simulation time 2353969451 ps
CPU time 2.25 seconds
Started Apr 02 12:30:30 PM PDT 24
Finished Apr 02 12:30:33 PM PDT 24
Peak memory 201416 kb
Host smart-e83be236-8de9-4cbd-a642-e8287acc4fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658218062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors
.658218062
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3957881257
Short name T894
Test name
Test status
Simulation time 42822566194 ps
CPU time 28.97 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:31:01 PM PDT 24
Peak memory 201436 kb
Host smart-9a453414-c1ff-4453-ba52-ca6d8cc28830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957881257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3957881257
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3271938399
Short name T806
Test name
Test status
Simulation time 2123156120 ps
CPU time 2.33 seconds
Started Apr 02 12:30:28 PM PDT 24
Finished Apr 02 12:30:30 PM PDT 24
Peak memory 201284 kb
Host smart-d49b99ad-087d-4e09-b6a3-dd4640bb560f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271938399 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3271938399
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.86529269
Short name T283
Test name
Test status
Simulation time 2022291775 ps
CPU time 4.79 seconds
Started Apr 02 12:30:27 PM PDT 24
Finished Apr 02 12:30:32 PM PDT 24
Peak memory 201192 kb
Host smart-ce0de81a-d2ab-473b-98b6-04d953a3786b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86529269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.86529269
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2567695981
Short name T886
Test name
Test status
Simulation time 2013322003 ps
CPU time 5.98 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 200680 kb
Host smart-01ecee3e-a7dc-445d-b12b-d445fb2f7be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567695981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.2567695981
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2398411731
Short name T824
Test name
Test status
Simulation time 4475305875 ps
CPU time 2.45 seconds
Started Apr 02 12:30:31 PM PDT 24
Finished Apr 02 12:30:34 PM PDT 24
Peak memory 201500 kb
Host smart-12f96fb1-b002-4d0c-9b9f-f3cfdf4adc6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398411731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2398411731
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1500748962
Short name T897
Test name
Test status
Simulation time 2318374977 ps
CPU time 2.93 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:37 PM PDT 24
Peak memory 201420 kb
Host smart-ac2a46c0-4712-40ab-af5a-1d2adccf9a79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500748962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.1500748962
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1700314833
Short name T872
Test name
Test status
Simulation time 22227766685 ps
CPU time 56.77 seconds
Started Apr 02 12:30:33 PM PDT 24
Finished Apr 02 12:31:30 PM PDT 24
Peak memory 201500 kb
Host smart-7fa55465-3477-4937-9758-17dae65b795a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700314833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.1700314833
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3872305075
Short name T817
Test name
Test status
Simulation time 2070908733 ps
CPU time 5.96 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 201324 kb
Host smart-26fd9539-2bbc-4c98-810f-0517361ce987
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872305075 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3872305075
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3806738920
Short name T293
Test name
Test status
Simulation time 2038198201 ps
CPU time 5.69 seconds
Started Apr 02 12:30:34 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201332 kb
Host smart-80c99a68-f009-4699-a00a-40a2fbfb375b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806738920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3806738920
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.863082055
Short name T904
Test name
Test status
Simulation time 2015072774 ps
CPU time 5.69 seconds
Started Apr 02 12:30:36 PM PDT 24
Finished Apr 02 12:30:42 PM PDT 24
Peak memory 200836 kb
Host smart-cddb4b69-c266-4c4b-aa53-2136acd11bf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863082055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test
.863082055
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1858786362
Short name T802
Test name
Test status
Simulation time 8429741040 ps
CPU time 16.67 seconds
Started Apr 02 12:30:37 PM PDT 24
Finished Apr 02 12:30:54 PM PDT 24
Peak memory 201500 kb
Host smart-8b4e1af8-133f-4e13-a3c8-6c1295583204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858786362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.1858786362
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1343740225
Short name T879
Test name
Test status
Simulation time 2281292553 ps
CPU time 5.28 seconds
Started Apr 02 12:30:32 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 201432 kb
Host smart-3d1f0929-6490-4fc1-b77d-f4cc0c15689a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343740225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.1343740225
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1667873809
Short name T337
Test name
Test status
Simulation time 22267230825 ps
CPU time 28.64 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:31:04 PM PDT 24
Peak memory 201464 kb
Host smart-a8e7d135-74ff-4e58-99ab-fa50f94b7877
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667873809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1667873809
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2754349763
Short name T891
Test name
Test status
Simulation time 2127345466 ps
CPU time 7.06 seconds
Started Apr 02 12:30:41 PM PDT 24
Finished Apr 02 12:30:48 PM PDT 24
Peak memory 201328 kb
Host smart-d4a956e8-0c9e-48c9-af36-fdc2052a31c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754349763 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2754349763
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.886770705
Short name T856
Test name
Test status
Simulation time 2277508313 ps
CPU time 1 seconds
Started Apr 02 12:30:40 PM PDT 24
Finished Apr 02 12:30:41 PM PDT 24
Peak memory 201376 kb
Host smart-7a8292dc-76a0-41fc-9833-af984a5dec6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886770705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw
.886770705
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3171287923
Short name T805
Test name
Test status
Simulation time 2062905431 ps
CPU time 1.52 seconds
Started Apr 02 12:30:41 PM PDT 24
Finished Apr 02 12:30:43 PM PDT 24
Peak memory 200716 kb
Host smart-9bb8d328-49c2-42d6-a907-c7e491845e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171287923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.3171287923
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.4120482739
Short name T831
Test name
Test status
Simulation time 7921315373 ps
CPU time 3.94 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:39 PM PDT 24
Peak memory 201416 kb
Host smart-b87b2ba3-c880-488f-ae43-00323d41812a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120482739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.4120482739
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1076427743
Short name T807
Test name
Test status
Simulation time 2273662140 ps
CPU time 3.25 seconds
Started Apr 02 12:30:35 PM PDT 24
Finished Apr 02 12:30:38 PM PDT 24
Peak memory 201416 kb
Host smart-5366c3e9-758f-4696-8ce0-713f8c624bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076427743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.1076427743
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.2168903574
Short name T469
Test name
Test status
Simulation time 2009797237 ps
CPU time 6.03 seconds
Started Apr 02 01:02:31 PM PDT 24
Finished Apr 02 01:02:37 PM PDT 24
Peak memory 201864 kb
Host smart-2654afdf-d245-43bb-978e-dffc6592093f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168903574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.2168903574
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3894836759
Short name T459
Test name
Test status
Simulation time 260599950958 ps
CPU time 47.78 seconds
Started Apr 02 01:02:28 PM PDT 24
Finished Apr 02 01:03:17 PM PDT 24
Peak memory 201900 kb
Host smart-323130da-d95c-4af8-9327-f95dad594149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894836759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.3894836759
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.627822988
Short name T680
Test name
Test status
Simulation time 144251674074 ps
CPU time 390.3 seconds
Started Apr 02 01:02:27 PM PDT 24
Finished Apr 02 01:08:58 PM PDT 24
Peak memory 202072 kb
Host smart-19fc5b4a-9f97-4e1c-b9ae-dd6700ceb5ea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627822988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_combo_detect.627822988
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.896273544
Short name T754
Test name
Test status
Simulation time 2402863736 ps
CPU time 3.79 seconds
Started Apr 02 01:02:34 PM PDT 24
Finished Apr 02 01:02:38 PM PDT 24
Peak memory 201812 kb
Host smart-716da07d-9688-4076-9c2b-44498a6c948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896273544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.896273544
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.117336621
Short name T381
Test name
Test status
Simulation time 2558281841 ps
CPU time 1.96 seconds
Started Apr 02 01:02:29 PM PDT 24
Finished Apr 02 01:02:31 PM PDT 24
Peak memory 201776 kb
Host smart-1a539397-4604-4e3e-8eed-e3082e2d988d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117336621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.117336621
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1231325132
Short name T774
Test name
Test status
Simulation time 26359481263 ps
CPU time 19.37 seconds
Started Apr 02 01:02:30 PM PDT 24
Finished Apr 02 01:02:50 PM PDT 24
Peak memory 202192 kb
Host smart-fbabbfac-a33c-446d-8baa-46b92d83687e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231325132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.1231325132
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2975570425
Short name T442
Test name
Test status
Simulation time 4907519651 ps
CPU time 14.79 seconds
Started Apr 02 01:02:34 PM PDT 24
Finished Apr 02 01:02:49 PM PDT 24
Peak memory 201828 kb
Host smart-da66e96a-ca7e-43d4-b7c1-a9abec7c38f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975570425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.2975570425
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.101543289
Short name T179
Test name
Test status
Simulation time 4443526768 ps
CPU time 9.92 seconds
Started Apr 02 01:02:29 PM PDT 24
Finished Apr 02 01:02:40 PM PDT 24
Peak memory 201876 kb
Host smart-06a355af-6faf-437e-8e60-59aca219d026
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101543289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_edge_detect.101543289
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1090265615
Short name T117
Test name
Test status
Simulation time 2798694071 ps
CPU time 1 seconds
Started Apr 02 01:02:31 PM PDT 24
Finished Apr 02 01:02:32 PM PDT 24
Peak memory 201784 kb
Host smart-ad82659b-3cba-40bd-a35f-a310015be6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090265615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1090265615
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.3238897373
Short name T392
Test name
Test status
Simulation time 2482203432 ps
CPU time 2.45 seconds
Started Apr 02 01:02:25 PM PDT 24
Finished Apr 02 01:02:28 PM PDT 24
Peak memory 201940 kb
Host smart-baf86a62-ea8c-4f5b-9ece-b7dd47567d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238897373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.3238897373
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1838862054
Short name T678
Test name
Test status
Simulation time 2095517192 ps
CPU time 1.97 seconds
Started Apr 02 01:02:28 PM PDT 24
Finished Apr 02 01:02:30 PM PDT 24
Peak memory 201820 kb
Host smart-29ba767a-7080-42f0-abbc-589f99d7ee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838862054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1838862054
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3014977320
Short name T509
Test name
Test status
Simulation time 2511174622 ps
CPU time 7.25 seconds
Started Apr 02 01:02:34 PM PDT 24
Finished Apr 02 01:02:42 PM PDT 24
Peak memory 201808 kb
Host smart-3361e5dc-b784-4031-9dd0-474b7c2d1e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014977320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3014977320
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.4121714623
Short name T228
Test name
Test status
Simulation time 2132721770 ps
CPU time 1.93 seconds
Started Apr 02 01:02:28 PM PDT 24
Finished Apr 02 01:02:30 PM PDT 24
Peak memory 201852 kb
Host smart-cbf4fe51-2370-4692-9b1e-154c697d703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121714623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.4121714623
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.1289239933
Short name T247
Test name
Test status
Simulation time 89838271145 ps
CPU time 122.69 seconds
Started Apr 02 01:02:32 PM PDT 24
Finished Apr 02 01:04:35 PM PDT 24
Peak memory 201964 kb
Host smart-f8783727-04c4-45e5-abd7-5ae703443cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289239933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.1289239933
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1521274601
Short name T62
Test name
Test status
Simulation time 4732455567 ps
CPU time 4.1 seconds
Started Apr 02 01:02:41 PM PDT 24
Finished Apr 02 01:02:45 PM PDT 24
Peak memory 201824 kb
Host smart-574c2963-beae-493b-9a43-17e12654f4c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521274601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.1521274601
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1552561028
Short name T44
Test name
Test status
Simulation time 3136464893 ps
CPU time 8.4 seconds
Started Apr 02 01:02:37 PM PDT 24
Finished Apr 02 01:02:46 PM PDT 24
Peak memory 202228 kb
Host smart-933303b3-a82e-4c5f-b6b9-fd5d0fa4ab39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552561028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1552561028
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2875332880
Short name T474
Test name
Test status
Simulation time 2424356653 ps
CPU time 6.94 seconds
Started Apr 02 01:02:34 PM PDT 24
Finished Apr 02 01:02:41 PM PDT 24
Peak memory 201944 kb
Host smart-5e88764e-d3c8-456e-8843-42242dd3d690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875332880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2875332880
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3883725678
Short name T583
Test name
Test status
Simulation time 2283560404 ps
CPU time 1.98 seconds
Started Apr 02 01:02:31 PM PDT 24
Finished Apr 02 01:02:33 PM PDT 24
Peak memory 201912 kb
Host smart-77203de2-1192-4989-81f4-78c9e5047c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883725678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3883725678
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3697322781
Short name T121
Test name
Test status
Simulation time 79909942770 ps
CPU time 231.2 seconds
Started Apr 02 01:02:34 PM PDT 24
Finished Apr 02 01:06:26 PM PDT 24
Peak memory 202212 kb
Host smart-72d95bec-b1f5-4de0-b897-979fb2c0c29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697322781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.3697322781
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.425608634
Short name T585
Test name
Test status
Simulation time 2962812772 ps
CPU time 1.2 seconds
Started Apr 02 01:02:31 PM PDT 24
Finished Apr 02 01:02:33 PM PDT 24
Peak memory 201920 kb
Host smart-2f128ddb-1480-478f-ab51-d94817d89ff9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425608634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_ec_pwr_on_rst.425608634
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.1948093108
Short name T171
Test name
Test status
Simulation time 2920511972 ps
CPU time 7.65 seconds
Started Apr 02 01:02:33 PM PDT 24
Finished Apr 02 01:02:41 PM PDT 24
Peak memory 201944 kb
Host smart-12007d7c-dc52-42df-8c3c-805be17e3283
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948093108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.1948093108
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.46478402
Short name T621
Test name
Test status
Simulation time 2609098795 ps
CPU time 7.25 seconds
Started Apr 02 01:02:32 PM PDT 24
Finished Apr 02 01:02:39 PM PDT 24
Peak memory 201904 kb
Host smart-127ec2a5-4105-484a-ba49-4695f709255d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46478402 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.46478402
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2394017342
Short name T66
Test name
Test status
Simulation time 2460559089 ps
CPU time 7.54 seconds
Started Apr 02 01:02:33 PM PDT 24
Finished Apr 02 01:02:41 PM PDT 24
Peak memory 201928 kb
Host smart-30c1ddb5-d0f6-46ba-9fa2-45540198a82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394017342 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2394017342
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1165210265
Short name T687
Test name
Test status
Simulation time 2109221818 ps
CPU time 1.21 seconds
Started Apr 02 01:02:31 PM PDT 24
Finished Apr 02 01:02:32 PM PDT 24
Peak memory 201828 kb
Host smart-0f8937cd-c44e-4a72-81b7-ff218cbf1722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165210265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.1165210265
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3312783837
Short name T602
Test name
Test status
Simulation time 2510159715 ps
CPU time 6.88 seconds
Started Apr 02 01:02:31 PM PDT 24
Finished Apr 02 01:02:38 PM PDT 24
Peak memory 201924 kb
Host smart-c40d09db-fcc6-4f31-86eb-fe774234faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312783837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.3312783837
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2839060900
Short name T81
Test name
Test status
Simulation time 22021616644 ps
CPU time 28.93 seconds
Started Apr 02 01:02:36 PM PDT 24
Finished Apr 02 01:03:05 PM PDT 24
Peak memory 221832 kb
Host smart-43609b85-0ddc-4c3b-abba-27e6511ad7a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839060900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.2839060900
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.996418472
Short name T607
Test name
Test status
Simulation time 2124471918 ps
CPU time 2.68 seconds
Started Apr 02 01:02:36 PM PDT 24
Finished Apr 02 01:02:39 PM PDT 24
Peak memory 201920 kb
Host smart-f78f837a-efa9-453c-b233-6e398f2d4751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996418472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.996418472
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.2223067391
Short name T221
Test name
Test status
Simulation time 18682477034 ps
CPU time 36.01 seconds
Started Apr 02 01:02:36 PM PDT 24
Finished Apr 02 01:03:12 PM PDT 24
Peak memory 201960 kb
Host smart-39f2e00d-ea59-410f-9a67-15a29d19a474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223067391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.2223067391
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1399276825
Short name T85
Test name
Test status
Simulation time 993422549789 ps
CPU time 154.43 seconds
Started Apr 02 01:02:35 PM PDT 24
Finished Apr 02 01:05:10 PM PDT 24
Peak memory 210600 kb
Host smart-7c4382f9-74df-4dfb-ab0c-6e57bce0b97e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399276825 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.1399276825
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3759002496
Short name T140
Test name
Test status
Simulation time 3541172973472 ps
CPU time 915.22 seconds
Started Apr 02 01:02:46 PM PDT 24
Finished Apr 02 01:18:03 PM PDT 24
Peak memory 201948 kb
Host smart-c89189f4-de73-4385-a3f2-bf55a1769959
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759002496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.3759002496
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.1444451210
Short name T390
Test name
Test status
Simulation time 2024471037 ps
CPU time 3.02 seconds
Started Apr 02 01:03:26 PM PDT 24
Finished Apr 02 01:03:29 PM PDT 24
Peak memory 201960 kb
Host smart-afcebcb9-cbfa-4416-b11d-419c8401105f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444451210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.1444451210
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.856455989
Short name T559
Test name
Test status
Simulation time 3392912125 ps
CPU time 4.99 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:03:20 PM PDT 24
Peak memory 201920 kb
Host smart-5fdd3293-028e-4301-b0ae-06c4df861b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856455989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.856455989
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.2174355601
Short name T329
Test name
Test status
Simulation time 46385920386 ps
CPU time 123.6 seconds
Started Apr 02 01:03:14 PM PDT 24
Finished Apr 02 01:05:18 PM PDT 24
Peak memory 202188 kb
Host smart-8fc46c29-0656-4675-856b-a62058d054e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174355601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.2174355601
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3268763802
Short name T170
Test name
Test status
Simulation time 43717471316 ps
CPU time 110.38 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:05:06 PM PDT 24
Peak memory 202152 kb
Host smart-3c2db3c5-2552-4027-9094-303944b2475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268763802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.3268763802
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3748685871
Short name T784
Test name
Test status
Simulation time 3336019683 ps
CPU time 1.5 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:03:17 PM PDT 24
Peak memory 201868 kb
Host smart-c4786737-87b9-4b77-bb52-118e44c0e244
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748685871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.3748685871
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.3630601765
Short name T674
Test name
Test status
Simulation time 5011742339 ps
CPU time 12.11 seconds
Started Apr 02 01:03:17 PM PDT 24
Finished Apr 02 01:03:29 PM PDT 24
Peak memory 201932 kb
Host smart-04232ea6-eff0-4738-9544-13932d108df4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630601765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.3630601765
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3331023008
Short name T491
Test name
Test status
Simulation time 2626434041 ps
CPU time 2.44 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:03:18 PM PDT 24
Peak memory 201956 kb
Host smart-f3ed266d-762c-442f-a759-7a6be8d4f9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331023008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.3331023008
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.3630434203
Short name T551
Test name
Test status
Simulation time 2486573957 ps
CPU time 2.79 seconds
Started Apr 02 01:03:27 PM PDT 24
Finished Apr 02 01:03:29 PM PDT 24
Peak memory 201880 kb
Host smart-74309271-a82b-4034-bab1-554fb4d69c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630434203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.3630434203
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.1495208362
Short name T370
Test name
Test status
Simulation time 2184882966 ps
CPU time 1.29 seconds
Started Apr 02 01:03:14 PM PDT 24
Finished Apr 02 01:03:16 PM PDT 24
Peak memory 201916 kb
Host smart-3835c953-687c-4ded-95ef-1b88253bac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495208362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.1495208362
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2969513298
Short name T582
Test name
Test status
Simulation time 2511996937 ps
CPU time 7.66 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:03:24 PM PDT 24
Peak memory 201888 kb
Host smart-782a1851-ae0e-4a48-95db-bad82ecd60bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969513298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.2969513298
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.2174990184
Short name T359
Test name
Test status
Simulation time 2112535458 ps
CPU time 5.99 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:03:22 PM PDT 24
Peak memory 201848 kb
Host smart-bf4ac8ec-62b0-478f-95b7-aa7470d400a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174990184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.2174990184
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.3621416395
Short name T521
Test name
Test status
Simulation time 7167676938 ps
CPU time 5.09 seconds
Started Apr 02 01:03:26 PM PDT 24
Finished Apr 02 01:03:32 PM PDT 24
Peak memory 201952 kb
Host smart-850da6e7-3057-4038-85b0-cb87d7444089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621416395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.3621416395
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3703206894
Short name T109
Test name
Test status
Simulation time 91773643809 ps
CPU time 40.8 seconds
Started Apr 02 01:03:18 PM PDT 24
Finished Apr 02 01:03:59 PM PDT 24
Peak memory 210488 kb
Host smart-f460e8c7-f5f8-44e4-bc57-323aea05e802
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703206894 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.3703206894
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1455901725
Short name T388
Test name
Test status
Simulation time 6522336357 ps
CPU time 6.62 seconds
Started Apr 02 01:03:14 PM PDT 24
Finished Apr 02 01:03:21 PM PDT 24
Peak memory 201928 kb
Host smart-cdb56227-f6b6-4cff-a3b8-1b67a03a8eed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455901725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.1455901725
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.4040743026
Short name T153
Test name
Test status
Simulation time 2010125708 ps
CPU time 4.83 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:03:20 PM PDT 24
Peak memory 201968 kb
Host smart-bb4e59fe-3c66-4528-9b54-21bf8f6043de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040743026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.4040743026
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3899427311
Short name T174
Test name
Test status
Simulation time 3245541839 ps
CPU time 4.87 seconds
Started Apr 02 01:03:26 PM PDT 24
Finished Apr 02 01:03:31 PM PDT 24
Peak memory 201952 kb
Host smart-ccf70ef4-4770-4d31-b256-b2bcdc287ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899427311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.3
899427311
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.708340538
Short name T672
Test name
Test status
Simulation time 191491930389 ps
CPU time 228.68 seconds
Started Apr 02 01:03:18 PM PDT 24
Finished Apr 02 01:07:07 PM PDT 24
Peak memory 202168 kb
Host smart-60ece94b-3347-4025-b840-d0627eeeb9c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708340538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_combo_detect.708340538
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2369158785
Short name T432
Test name
Test status
Simulation time 381799920878 ps
CPU time 920.14 seconds
Started Apr 02 01:03:17 PM PDT 24
Finished Apr 02 01:18:37 PM PDT 24
Peak memory 201924 kb
Host smart-5d164047-d85d-4cd2-ab79-b830232e1713
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369158785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.2369158785
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.297675739
Short name T713
Test name
Test status
Simulation time 2970029879 ps
CPU time 1.61 seconds
Started Apr 02 01:03:18 PM PDT 24
Finished Apr 02 01:03:19 PM PDT 24
Peak memory 201944 kb
Host smart-00e70bba-4e30-4d89-9078-7ee15b2c8d20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297675739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctr
l_edge_detect.297675739
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3659071255
Short name T422
Test name
Test status
Simulation time 2636474261 ps
CPU time 2.02 seconds
Started Apr 02 01:03:18 PM PDT 24
Finished Apr 02 01:03:20 PM PDT 24
Peak memory 201904 kb
Host smart-0f2813bf-e975-406c-9e02-fe06c87c334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659071255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.3659071255
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.2666401489
Short name T589
Test name
Test status
Simulation time 2478847378 ps
CPU time 4.21 seconds
Started Apr 02 01:03:25 PM PDT 24
Finished Apr 02 01:03:30 PM PDT 24
Peak memory 201880 kb
Host smart-6282db01-2711-4ee5-84a3-a33aceb8853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666401489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.2666401489
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.3210851667
Short name T353
Test name
Test status
Simulation time 2071112161 ps
CPU time 6.2 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:03:22 PM PDT 24
Peak memory 201828 kb
Host smart-eda13167-36ce-4f64-856a-ecd2a05fb517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210851667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.3210851667
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.876308986
Short name T616
Test name
Test status
Simulation time 2508230128 ps
CPU time 7.16 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:03:22 PM PDT 24
Peak memory 201948 kb
Host smart-c2068371-5a51-4fc7-921c-bacf4392eadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876308986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.876308986
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.2664647505
Short name T424
Test name
Test status
Simulation time 2112678254 ps
CPU time 6.17 seconds
Started Apr 02 01:03:27 PM PDT 24
Finished Apr 02 01:03:33 PM PDT 24
Peak memory 201816 kb
Host smart-46f8ac34-c7dd-4221-9e3e-dfe8afad9f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664647505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2664647505
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.1507198849
Short name T667
Test name
Test status
Simulation time 249356759767 ps
CPU time 163.14 seconds
Started Apr 02 01:03:18 PM PDT 24
Finished Apr 02 01:06:02 PM PDT 24
Peak memory 202000 kb
Host smart-992daf7b-5e03-4754-b58b-bc43bded3487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507198849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.1507198849
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2952259606
Short name T36
Test name
Test status
Simulation time 36367154400 ps
CPU time 22.77 seconds
Started Apr 02 01:03:26 PM PDT 24
Finished Apr 02 01:03:49 PM PDT 24
Peak memory 210488 kb
Host smart-e1211053-364d-4aba-a5df-e958be8920f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952259606 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2952259606
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1248468029
Short name T73
Test name
Test status
Simulation time 4728027239 ps
CPU time 2.39 seconds
Started Apr 02 01:03:18 PM PDT 24
Finished Apr 02 01:03:20 PM PDT 24
Peak memory 201960 kb
Host smart-e7aa4e19-9489-4e9a-8989-6ab988092b54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248468029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1248468029
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.3262260362
Short name T788
Test name
Test status
Simulation time 2023663125 ps
CPU time 2.09 seconds
Started Apr 02 01:03:24 PM PDT 24
Finished Apr 02 01:03:26 PM PDT 24
Peak memory 202000 kb
Host smart-24e03bd3-925e-4e0e-98c5-681bf46e69b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262260362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.3262260362
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3992453207
Short name T603
Test name
Test status
Simulation time 3644254091 ps
CPU time 2.96 seconds
Started Apr 02 01:03:21 PM PDT 24
Finished Apr 02 01:03:25 PM PDT 24
Peak memory 201948 kb
Host smart-0a0a7e32-cfbb-4057-a035-27af44b8395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992453207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.3
992453207
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.2016207768
Short name T300
Test name
Test status
Simulation time 55930923582 ps
CPU time 68.02 seconds
Started Apr 02 01:03:21 PM PDT 24
Finished Apr 02 01:04:29 PM PDT 24
Peak memory 202100 kb
Host smart-e1c8900a-598f-4009-87b1-5b6550d421ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016207768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.2016207768
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.1708621060
Short name T343
Test name
Test status
Simulation time 45570954726 ps
CPU time 28.77 seconds
Started Apr 02 01:03:24 PM PDT 24
Finished Apr 02 01:03:53 PM PDT 24
Peak memory 202216 kb
Host smart-cb90895f-8adf-4748-9afb-fcde51ab73d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708621060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.1708621060
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2290565650
Short name T747
Test name
Test status
Simulation time 3917715657 ps
CPU time 3.04 seconds
Started Apr 02 01:03:21 PM PDT 24
Finished Apr 02 01:03:24 PM PDT 24
Peak memory 201904 kb
Host smart-9385b87d-58f4-4ed6-9143-c75d530c75d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290565650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.2290565650
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.1772644888
Short name T178
Test name
Test status
Simulation time 5623389652 ps
CPU time 3.47 seconds
Started Apr 02 01:03:25 PM PDT 24
Finished Apr 02 01:03:28 PM PDT 24
Peak memory 201936 kb
Host smart-2c7c0b2d-d25d-413f-aa2d-344b40a2f619
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772644888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.1772644888
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3463750591
Short name T473
Test name
Test status
Simulation time 2648581925 ps
CPU time 1.85 seconds
Started Apr 02 01:03:21 PM PDT 24
Finished Apr 02 01:03:23 PM PDT 24
Peak memory 201976 kb
Host smart-84f350c9-37fa-418e-b638-f781f517505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463750591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.3463750591
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3369286470
Short name T513
Test name
Test status
Simulation time 2447560054 ps
CPU time 4.27 seconds
Started Apr 02 01:03:22 PM PDT 24
Finished Apr 02 01:03:27 PM PDT 24
Peak memory 201944 kb
Host smart-7c4996b7-ca6e-40a7-a219-1a5312db6cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369286470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.3369286470
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.1653438582
Short name T412
Test name
Test status
Simulation time 2167608052 ps
CPU time 3.66 seconds
Started Apr 02 01:03:23 PM PDT 24
Finished Apr 02 01:03:27 PM PDT 24
Peak memory 201912 kb
Host smart-c5c8c932-b3bf-4acf-ad9b-a108c402a5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653438582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.1653438582
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1688728387
Short name T699
Test name
Test status
Simulation time 2509789893 ps
CPU time 7.53 seconds
Started Apr 02 01:03:20 PM PDT 24
Finished Apr 02 01:03:28 PM PDT 24
Peak memory 201944 kb
Host smart-3049a03d-430e-4bb2-83b3-8a9b05ba8f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688728387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.1688728387
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.1400700630
Short name T464
Test name
Test status
Simulation time 2114327128 ps
CPU time 3.4 seconds
Started Apr 02 01:03:18 PM PDT 24
Finished Apr 02 01:03:21 PM PDT 24
Peak memory 201832 kb
Host smart-cf2b6bab-485e-4b07-ab4c-63bca232f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400700630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.1400700630
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3297597050
Short name T601
Test name
Test status
Simulation time 70941078060 ps
CPU time 34.48 seconds
Started Apr 02 01:03:31 PM PDT 24
Finished Apr 02 01:04:05 PM PDT 24
Peak memory 210564 kb
Host smart-8bfaddc7-f70c-4a4b-b66d-9616ffb17adc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297597050 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3297597050
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.2201937857
Short name T7
Test name
Test status
Simulation time 7744058903 ps
CPU time 2.45 seconds
Started Apr 02 01:03:22 PM PDT 24
Finished Apr 02 01:03:24 PM PDT 24
Peak memory 201932 kb
Host smart-6f9022a8-97af-4d4a-8bec-21d5c62d1e26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201937857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.2201937857
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.4180679624
Short name T15
Test name
Test status
Simulation time 2027785885 ps
CPU time 1.91 seconds
Started Apr 02 01:03:32 PM PDT 24
Finished Apr 02 01:03:34 PM PDT 24
Peak memory 202004 kb
Host smart-a56f6e06-689e-4848-bccb-8e7901141afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180679624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.4180679624
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3228256075
Short name T460
Test name
Test status
Simulation time 3281815158 ps
CPU time 1.39 seconds
Started Apr 02 01:03:25 PM PDT 24
Finished Apr 02 01:03:27 PM PDT 24
Peak memory 201984 kb
Host smart-230ed38f-a736-45a9-a94e-be68a804897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228256075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.3
228256075
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.2419857426
Short name T653
Test name
Test status
Simulation time 114192761005 ps
CPU time 266.13 seconds
Started Apr 02 01:03:36 PM PDT 24
Finished Apr 02 01:08:02 PM PDT 24
Peak memory 202160 kb
Host smart-907a7ace-f6c7-4cd9-bd90-98d8e914f1db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419857426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.2419857426
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.345081695
Short name T538
Test name
Test status
Simulation time 47148926866 ps
CPU time 127.93 seconds
Started Apr 02 01:03:27 PM PDT 24
Finished Apr 02 01:05:35 PM PDT 24
Peak memory 202160 kb
Host smart-22d7407a-ddf6-464c-a291-34a3c8f7bbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345081695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_wi
th_pre_cond.345081695
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3804813003
Short name T613
Test name
Test status
Simulation time 3848050667 ps
CPU time 11.2 seconds
Started Apr 02 01:03:23 PM PDT 24
Finished Apr 02 01:03:35 PM PDT 24
Peak memory 201924 kb
Host smart-35e37d60-a661-48a6-b04b-a418b69d1a43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804813003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.3804813003
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.51238360
Short name T627
Test name
Test status
Simulation time 5049908324 ps
CPU time 1.52 seconds
Started Apr 02 01:03:33 PM PDT 24
Finished Apr 02 01:03:35 PM PDT 24
Peak memory 201952 kb
Host smart-da8b858d-33e5-4813-9bcf-fbd8920194d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51238360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl
_edge_detect.51238360
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1330484564
Short name T54
Test name
Test status
Simulation time 2612634927 ps
CPU time 7.48 seconds
Started Apr 02 01:03:26 PM PDT 24
Finished Apr 02 01:03:33 PM PDT 24
Peak memory 201832 kb
Host smart-9b8ee4ba-7f39-40e3-b306-c2be5dabe9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330484564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.1330484564
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.3068175098
Short name T378
Test name
Test status
Simulation time 2453364900 ps
CPU time 7.46 seconds
Started Apr 02 01:03:27 PM PDT 24
Finished Apr 02 01:03:35 PM PDT 24
Peak memory 201968 kb
Host smart-f58cab65-860c-44b3-a542-db132e96e93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068175098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.3068175098
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.988824443
Short name T404
Test name
Test status
Simulation time 2145740181 ps
CPU time 3.26 seconds
Started Apr 02 01:03:24 PM PDT 24
Finished Apr 02 01:03:28 PM PDT 24
Peak memory 201764 kb
Host smart-85d56175-745f-4a96-a796-b0733e1fceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988824443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.988824443
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3984894427
Short name T777
Test name
Test status
Simulation time 2536789987 ps
CPU time 1.68 seconds
Started Apr 02 01:03:26 PM PDT 24
Finished Apr 02 01:03:27 PM PDT 24
Peak memory 201996 kb
Host smart-b1615689-8505-42a4-a0c8-fa9502e5d86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984894427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.3984894427
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.699053485
Short name T665
Test name
Test status
Simulation time 2112517361 ps
CPU time 6.08 seconds
Started Apr 02 01:03:25 PM PDT 24
Finished Apr 02 01:03:31 PM PDT 24
Peak memory 201832 kb
Host smart-09e43da1-3600-426f-8999-8363f79c0ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699053485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.699053485
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.50626839
Short name T414
Test name
Test status
Simulation time 13229240699 ps
CPU time 10.16 seconds
Started Apr 02 01:03:32 PM PDT 24
Finished Apr 02 01:03:42 PM PDT 24
Peak memory 201960 kb
Host smart-1cd20300-2fb6-490e-9334-e12741b2be0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50626839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_str
ess_all.50626839
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3138462812
Short name T141
Test name
Test status
Simulation time 63943866834 ps
CPU time 39.68 seconds
Started Apr 02 01:03:29 PM PDT 24
Finished Apr 02 01:04:09 PM PDT 24
Peak memory 210492 kb
Host smart-7ad54eac-a41e-4e67-ab05-ee46e28495fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138462812 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3138462812
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.558881274
Short name T703
Test name
Test status
Simulation time 7448985844 ps
CPU time 6.59 seconds
Started Apr 02 01:03:26 PM PDT 24
Finished Apr 02 01:03:33 PM PDT 24
Peak memory 201976 kb
Host smart-8e61d8a8-667a-445a-bb38-53ca03ce198e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558881274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_ultra_low_pwr.558881274
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.2095041548
Short name T495
Test name
Test status
Simulation time 2046455793 ps
CPU time 1.69 seconds
Started Apr 02 01:03:33 PM PDT 24
Finished Apr 02 01:03:35 PM PDT 24
Peak memory 202008 kb
Host smart-00d68099-f187-408a-90f9-bda9dca9978c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095041548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.2095041548
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.760788420
Short name T752
Test name
Test status
Simulation time 3336047986 ps
CPU time 1.8 seconds
Started Apr 02 01:03:35 PM PDT 24
Finished Apr 02 01:03:38 PM PDT 24
Peak memory 202008 kb
Host smart-4f798019-7328-4192-a947-79c9ad3d4863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760788420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.760788420
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.640257113
Short name T500
Test name
Test status
Simulation time 43743850619 ps
CPU time 12.13 seconds
Started Apr 02 01:03:32 PM PDT 24
Finished Apr 02 01:03:44 PM PDT 24
Peak memory 202168 kb
Host smart-85384d0b-21d7-409a-ac53-996b300a59a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640257113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_combo_detect.640257113
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3258952395
Short name T619
Test name
Test status
Simulation time 39841023048 ps
CPU time 49.55 seconds
Started Apr 02 01:03:35 PM PDT 24
Finished Apr 02 01:04:24 PM PDT 24
Peak memory 202180 kb
Host smart-cd0e4361-c135-4680-8d26-e3bc669e1fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258952395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.3258952395
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3241864934
Short name T765
Test name
Test status
Simulation time 3493192120 ps
CPU time 2.78 seconds
Started Apr 02 01:03:28 PM PDT 24
Finished Apr 02 01:03:31 PM PDT 24
Peak memory 201924 kb
Host smart-2f3af9ae-7cc7-4095-aed5-9358f32eb3c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241864934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.3241864934
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2994507941
Short name T159
Test name
Test status
Simulation time 3192644138 ps
CPU time 2.06 seconds
Started Apr 02 01:03:32 PM PDT 24
Finished Apr 02 01:03:35 PM PDT 24
Peak memory 201920 kb
Host smart-a2f4d31d-8d70-4df8-8f0b-3e1296f090ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994507941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2994507941
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3253706570
Short name T701
Test name
Test status
Simulation time 2613071165 ps
CPU time 7.79 seconds
Started Apr 02 01:03:34 PM PDT 24
Finished Apr 02 01:03:42 PM PDT 24
Peak memory 201936 kb
Host smart-ea7383b4-fd07-4b00-9bbe-59b93f979ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253706570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.3253706570
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.4207356569
Short name T579
Test name
Test status
Simulation time 2464902404 ps
CPU time 7.05 seconds
Started Apr 02 01:03:31 PM PDT 24
Finished Apr 02 01:03:38 PM PDT 24
Peak memory 201904 kb
Host smart-6d7c3d37-4926-4798-9879-0d5ae96da5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207356569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.4207356569
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.544748470
Short name T588
Test name
Test status
Simulation time 2191575074 ps
CPU time 3.81 seconds
Started Apr 02 01:03:31 PM PDT 24
Finished Apr 02 01:03:35 PM PDT 24
Peak memory 201916 kb
Host smart-ca0d52f0-0525-4089-93ed-c567e4582359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544748470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.544748470
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1147177208
Short name T385
Test name
Test status
Simulation time 2528336429 ps
CPU time 2.46 seconds
Started Apr 02 01:03:30 PM PDT 24
Finished Apr 02 01:03:33 PM PDT 24
Peak memory 201932 kb
Host smart-04ab24f1-b79c-48f2-be7e-72742f1a902b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147177208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1147177208
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.3500940545
Short name T232
Test name
Test status
Simulation time 2131846206 ps
CPU time 1.9 seconds
Started Apr 02 01:03:32 PM PDT 24
Finished Apr 02 01:03:34 PM PDT 24
Peak memory 201908 kb
Host smart-22d9945c-9076-48f6-81f6-e0e581a55659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500940545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3500940545
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.1879543059
Short name T426
Test name
Test status
Simulation time 10250934727 ps
CPU time 28.8 seconds
Started Apr 02 01:03:33 PM PDT 24
Finished Apr 02 01:04:02 PM PDT 24
Peak memory 201972 kb
Host smart-fde8e4bd-98a8-473d-9071-094bfd1331e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879543059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.1879543059
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.263905240
Short name T267
Test name
Test status
Simulation time 30574800577 ps
CPU time 18.12 seconds
Started Apr 02 01:03:29 PM PDT 24
Finished Apr 02 01:03:47 PM PDT 24
Peak memory 210596 kb
Host smart-162fbfac-61a0-41bb-be13-d2694b95d1c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263905240 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.263905240
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.4241606797
Short name T60
Test name
Test status
Simulation time 6543092212 ps
CPU time 2.5 seconds
Started Apr 02 01:03:29 PM PDT 24
Finished Apr 02 01:03:31 PM PDT 24
Peak memory 201836 kb
Host smart-ba943ba5-67c3-4839-9812-039f60d28634
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241606797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.4241606797
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.1267899073
Short name T573
Test name
Test status
Simulation time 2038683872 ps
CPU time 1.94 seconds
Started Apr 02 01:03:34 PM PDT 24
Finished Apr 02 01:03:36 PM PDT 24
Peak memory 201948 kb
Host smart-acd09518-9f35-45e8-bd46-49bdd6c7ffa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267899073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.1267899073
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2999254423
Short name T761
Test name
Test status
Simulation time 83664769042 ps
CPU time 238.03 seconds
Started Apr 02 01:03:40 PM PDT 24
Finished Apr 02 01:07:39 PM PDT 24
Peak memory 201992 kb
Host smart-72733180-4447-40b0-b750-abefa25d8361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999254423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
999254423
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2938457455
Short name T696
Test name
Test status
Simulation time 176447116950 ps
CPU time 119.11 seconds
Started Apr 02 01:03:34 PM PDT 24
Finished Apr 02 01:05:34 PM PDT 24
Peak memory 202168 kb
Host smart-d96bf500-ca0f-44c5-bb29-598f167dd9dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938457455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.2938457455
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1898663187
Short name T652
Test name
Test status
Simulation time 43872179536 ps
CPU time 107.32 seconds
Started Apr 02 01:03:33 PM PDT 24
Finished Apr 02 01:05:21 PM PDT 24
Peak memory 202184 kb
Host smart-26352ad5-a132-4490-9404-2d36a5675d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898663187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.1898663187
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.1844362002
Short name T533
Test name
Test status
Simulation time 3730081500 ps
CPU time 10.72 seconds
Started Apr 02 01:03:33 PM PDT 24
Finished Apr 02 01:03:44 PM PDT 24
Peak memory 201956 kb
Host smart-6567d4e9-0a8c-46d1-b8df-f7ed9f9c8de5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844362002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.1844362002
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.3922256922
Short name T227
Test name
Test status
Simulation time 2397959619 ps
CPU time 6.48 seconds
Started Apr 02 01:03:33 PM PDT 24
Finished Apr 02 01:03:39 PM PDT 24
Peak memory 201916 kb
Host smart-ccd0ef95-750f-4d2e-a3a3-c174683543fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922256922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.3922256922
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1929666093
Short name T730
Test name
Test status
Simulation time 2645839372 ps
CPU time 1.86 seconds
Started Apr 02 01:03:33 PM PDT 24
Finished Apr 02 01:03:35 PM PDT 24
Peak memory 201932 kb
Host smart-08dbde03-3f58-4165-9154-5a002c40a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929666093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.1929666093
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2207738062
Short name T397
Test name
Test status
Simulation time 2472001568 ps
CPU time 7.38 seconds
Started Apr 02 01:03:34 PM PDT 24
Finished Apr 02 01:03:42 PM PDT 24
Peak memory 201804 kb
Host smart-c24c60e8-be7a-4779-ab1b-d16c3d5d6e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207738062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.2207738062
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.4048528819
Short name T454
Test name
Test status
Simulation time 2115806390 ps
CPU time 2.14 seconds
Started Apr 02 01:03:34 PM PDT 24
Finished Apr 02 01:03:37 PM PDT 24
Peak memory 201864 kb
Host smart-b29ed928-7212-400f-8562-4ef81166605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048528819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.4048528819
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2213060602
Short name T692
Test name
Test status
Simulation time 2542661047 ps
CPU time 1.52 seconds
Started Apr 02 01:03:35 PM PDT 24
Finished Apr 02 01:03:36 PM PDT 24
Peak memory 201948 kb
Host smart-2c3f9ac8-2fb3-4549-b9c0-8efe6c27f413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213060602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2213060602
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.64267495
Short name T383
Test name
Test status
Simulation time 2120829855 ps
CPU time 3.38 seconds
Started Apr 02 01:03:33 PM PDT 24
Finished Apr 02 01:03:37 PM PDT 24
Peak memory 201836 kb
Host smart-deb2685e-320d-4481-adb2-d9e1c92a68c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64267495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.64267495
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.854583524
Short name T251
Test name
Test status
Simulation time 1652443114448 ps
CPU time 253.75 seconds
Started Apr 02 01:03:35 PM PDT 24
Finished Apr 02 01:07:50 PM PDT 24
Peak memory 218088 kb
Host smart-cf266b9e-479e-4193-81e6-ea730f735bb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854583524 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.854583524
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1874749644
Short name T350
Test name
Test status
Simulation time 707469661263 ps
CPU time 38.75 seconds
Started Apr 02 01:03:35 PM PDT 24
Finished Apr 02 01:04:14 PM PDT 24
Peak memory 201840 kb
Host smart-20a57dd9-a3e3-4b3f-a3cf-6c96ae20d0e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874749644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.1874749644
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.3794189525
Short name T14
Test name
Test status
Simulation time 2010948368 ps
CPU time 5.82 seconds
Started Apr 02 01:03:43 PM PDT 24
Finished Apr 02 01:03:49 PM PDT 24
Peak memory 201884 kb
Host smart-fc8a3ff6-7e7b-482d-a2e1-4f9f9eb3cee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794189525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.3794189525
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1901767661
Short name T662
Test name
Test status
Simulation time 3309026698 ps
CPU time 2 seconds
Started Apr 02 01:03:36 PM PDT 24
Finished Apr 02 01:03:38 PM PDT 24
Peak memory 202016 kb
Host smart-63e92d4c-7c70-4189-8729-a01080a2c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901767661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1
901767661
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1369553465
Short name T745
Test name
Test status
Simulation time 163608038528 ps
CPU time 422.9 seconds
Started Apr 02 01:03:37 PM PDT 24
Finished Apr 02 01:10:40 PM PDT 24
Peak memory 202116 kb
Host smart-eda50d8c-2f20-45e7-835f-d7f5f08be173
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369553465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.1369553465
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.598253365
Short name T214
Test name
Test status
Simulation time 66769488996 ps
CPU time 169.99 seconds
Started Apr 02 01:03:43 PM PDT 24
Finished Apr 02 01:06:33 PM PDT 24
Peak memory 202160 kb
Host smart-d207650c-39b6-4d63-93a6-fea97fa2fbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598253365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_wi
th_pre_cond.598253365
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2732239494
Short name T697
Test name
Test status
Simulation time 2669896589 ps
CPU time 1.32 seconds
Started Apr 02 01:03:36 PM PDT 24
Finished Apr 02 01:03:37 PM PDT 24
Peak memory 201836 kb
Host smart-41113992-5d47-49a1-9974-d9d3717cc56b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732239494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.2732239494
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.4113501991
Short name T151
Test name
Test status
Simulation time 4442975307 ps
CPU time 7.78 seconds
Started Apr 02 01:03:40 PM PDT 24
Finished Apr 02 01:03:48 PM PDT 24
Peak memory 201860 kb
Host smart-6098f769-fca7-4002-8785-7e0c37f8ba5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113501991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.4113501991
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3068266604
Short name T704
Test name
Test status
Simulation time 2617827207 ps
CPU time 4.09 seconds
Started Apr 02 01:03:35 PM PDT 24
Finished Apr 02 01:03:40 PM PDT 24
Peak memory 201928 kb
Host smart-a4baa66a-8dd1-467a-abcb-6192b300990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068266604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3068266604
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.824921273
Short name T620
Test name
Test status
Simulation time 2449358420 ps
CPU time 5.74 seconds
Started Apr 02 01:03:36 PM PDT 24
Finished Apr 02 01:03:42 PM PDT 24
Peak memory 201940 kb
Host smart-182404a1-3a91-4e59-a988-65fe7d1ef2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824921273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.824921273
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3173561001
Short name T419
Test name
Test status
Simulation time 2204437437 ps
CPU time 2.06 seconds
Started Apr 02 01:03:38 PM PDT 24
Finished Apr 02 01:03:40 PM PDT 24
Peak memory 201912 kb
Host smart-f317378e-2a35-4d20-be90-8e356024c272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173561001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3173561001
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.3681253427
Short name T132
Test name
Test status
Simulation time 2555551298 ps
CPU time 1.47 seconds
Started Apr 02 01:03:36 PM PDT 24
Finished Apr 02 01:03:37 PM PDT 24
Peak memory 201868 kb
Host smart-c4612f3c-03d4-40c7-9425-f39f05fa26ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681253427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.3681253427
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.2092455576
Short name T688
Test name
Test status
Simulation time 2113703025 ps
CPU time 6.03 seconds
Started Apr 02 01:03:34 PM PDT 24
Finished Apr 02 01:03:40 PM PDT 24
Peak memory 201688 kb
Host smart-14302036-7d1b-4a99-b4b3-7247450230a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092455576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2092455576
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.2444952398
Short name T562
Test name
Test status
Simulation time 13047387286 ps
CPU time 17.35 seconds
Started Apr 02 01:03:43 PM PDT 24
Finished Apr 02 01:04:01 PM PDT 24
Peak memory 201948 kb
Host smart-02c8bf30-28d5-43d8-9b1a-3467f417e838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444952398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.2444952398
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1588493026
Short name T748
Test name
Test status
Simulation time 6252989062 ps
CPU time 8.07 seconds
Started Apr 02 01:03:40 PM PDT 24
Finished Apr 02 01:03:48 PM PDT 24
Peak memory 201952 kb
Host smart-3acd20e1-23fe-48c4-b724-41744a316e8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588493026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.1588493026
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1062004209
Short name T5
Test name
Test status
Simulation time 2034253105 ps
CPU time 2 seconds
Started Apr 02 01:03:47 PM PDT 24
Finished Apr 02 01:03:50 PM PDT 24
Peak memory 202004 kb
Host smart-b1c4eb2b-5081-4e7b-9b1a-6b2ed0acb8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062004209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1062004209
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4194464148
Short name T194
Test name
Test status
Simulation time 3784322064 ps
CPU time 5.26 seconds
Started Apr 02 01:03:43 PM PDT 24
Finished Apr 02 01:03:49 PM PDT 24
Peak memory 201988 kb
Host smart-524c935c-abd5-4ec5-930a-cc1fa0f2b192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194464148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.4
194464148
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.318917690
Short name T9
Test name
Test status
Simulation time 119504741817 ps
CPU time 83.75 seconds
Started Apr 02 01:03:47 PM PDT 24
Finished Apr 02 01:05:11 PM PDT 24
Peak memory 202068 kb
Host smart-fef38a52-fa62-4cd1-8283-f61389bec78f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318917690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_combo_detect.318917690
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3213204303
Short name T706
Test name
Test status
Simulation time 20595317787 ps
CPU time 28.98 seconds
Started Apr 02 01:03:43 PM PDT 24
Finished Apr 02 01:04:13 PM PDT 24
Peak memory 202144 kb
Host smart-3c1b5270-16c8-413e-b252-a74029f3c134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213204303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w
ith_pre_cond.3213204303
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3989805639
Short name T57
Test name
Test status
Simulation time 3037292566 ps
CPU time 8.18 seconds
Started Apr 02 01:03:44 PM PDT 24
Finished Apr 02 01:03:52 PM PDT 24
Peak memory 201928 kb
Host smart-33fdefa9-a76e-4cf9-ad7f-5b904d04e913
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989805639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.3989805639
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.2718210264
Short name T199
Test name
Test status
Simulation time 4094539753 ps
CPU time 1.25 seconds
Started Apr 02 01:03:47 PM PDT 24
Finished Apr 02 01:03:48 PM PDT 24
Peak memory 201920 kb
Host smart-aa3d529c-7f06-43fe-979b-631b38e65ed1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718210264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.2718210264
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3532158560
Short name T755
Test name
Test status
Simulation time 2618654071 ps
CPU time 4.27 seconds
Started Apr 02 01:03:41 PM PDT 24
Finished Apr 02 01:03:45 PM PDT 24
Peak memory 201884 kb
Host smart-d1aae62a-ea0b-4d68-b7ac-0b7be591a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532158560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.3532158560
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.3522658391
Short name T584
Test name
Test status
Simulation time 2459825680 ps
CPU time 6.47 seconds
Started Apr 02 01:03:40 PM PDT 24
Finished Apr 02 01:03:46 PM PDT 24
Peak memory 202140 kb
Host smart-9bd9228e-5cfd-4502-b179-0dbc5d00901f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522658391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.3522658391
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2650152120
Short name T689
Test name
Test status
Simulation time 2044400506 ps
CPU time 2.02 seconds
Started Apr 02 01:03:41 PM PDT 24
Finished Apr 02 01:03:43 PM PDT 24
Peak memory 201852 kb
Host smart-0def3e12-3439-4457-8bd8-7d825d98978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650152120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.2650152120
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2629601187
Short name T574
Test name
Test status
Simulation time 2523905708 ps
CPU time 2.33 seconds
Started Apr 02 01:03:43 PM PDT 24
Finished Apr 02 01:03:45 PM PDT 24
Peak memory 201796 kb
Host smart-9aba7c4b-0e5a-49a0-aed8-7961bf725230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629601187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2629601187
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.1037592525
Short name T431
Test name
Test status
Simulation time 2130674213 ps
CPU time 1.96 seconds
Started Apr 02 01:03:40 PM PDT 24
Finished Apr 02 01:03:42 PM PDT 24
Peak memory 201852 kb
Host smart-40cf3e28-1567-4846-8b4d-d4d0dcbe5558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037592525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.1037592525
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.2867573974
Short name T244
Test name
Test status
Simulation time 164671187794 ps
CPU time 217 seconds
Started Apr 02 01:03:47 PM PDT 24
Finished Apr 02 01:07:25 PM PDT 24
Peak memory 202040 kb
Host smart-f890a75f-cc63-4902-b037-b777f39262b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867573974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.2867573974
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2908381580
Short name T770
Test name
Test status
Simulation time 2780673144831 ps
CPU time 480.75 seconds
Started Apr 02 01:03:44 PM PDT 24
Finished Apr 02 01:11:45 PM PDT 24
Peak memory 218760 kb
Host smart-4725288c-1d04-495e-897b-b336e36f4f14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908381580 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.2908381580
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3905604368
Short name T643
Test name
Test status
Simulation time 2120273137 ps
CPU time 0.97 seconds
Started Apr 02 01:03:50 PM PDT 24
Finished Apr 02 01:03:52 PM PDT 24
Peak memory 202052 kb
Host smart-71b41c72-541a-4aa3-893e-749bd1c45361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905604368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3905604368
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1954250648
Short name T264
Test name
Test status
Simulation time 206212048090 ps
CPU time 253.88 seconds
Started Apr 02 01:03:45 PM PDT 24
Finished Apr 02 01:07:59 PM PDT 24
Peak memory 201832 kb
Host smart-cbdb755e-6a85-4a39-b101-b46e28c104cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954250648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1
954250648
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.1060532868
Short name T489
Test name
Test status
Simulation time 119077729550 ps
CPU time 275.23 seconds
Started Apr 02 01:03:45 PM PDT 24
Finished Apr 02 01:08:21 PM PDT 24
Peak memory 202136 kb
Host smart-39fb25ad-af6a-43ad-b637-08b122dd9cc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060532868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.1060532868
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.556893461
Short name T411
Test name
Test status
Simulation time 65261427246 ps
CPU time 20.65 seconds
Started Apr 02 01:03:50 PM PDT 24
Finished Apr 02 01:04:12 PM PDT 24
Peak memory 202140 kb
Host smart-a1bf5790-60ea-4ba4-ba28-a0376fbf133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556893461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.556893461
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2899526773
Short name T403
Test name
Test status
Simulation time 3775240119 ps
CPU time 10.55 seconds
Started Apr 02 01:03:45 PM PDT 24
Finished Apr 02 01:03:55 PM PDT 24
Peak memory 201984 kb
Host smart-e21e849e-bcc5-4225-8536-53e2828448ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899526773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.2899526773
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.331349179
Short name T182
Test name
Test status
Simulation time 2375541284 ps
CPU time 5.97 seconds
Started Apr 02 01:03:50 PM PDT 24
Finished Apr 02 01:03:57 PM PDT 24
Peak memory 201932 kb
Host smart-42669eca-d34f-4045-9b6e-ee191038e253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331349179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctr
l_edge_detect.331349179
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.2729860573
Short name T373
Test name
Test status
Simulation time 2636379341 ps
CPU time 2.36 seconds
Started Apr 02 01:03:45 PM PDT 24
Finished Apr 02 01:03:48 PM PDT 24
Peak memory 201932 kb
Host smart-1ddddd98-ee21-453a-83fc-0b3e5f511c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729860573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.2729860573
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.166503084
Short name T215
Test name
Test status
Simulation time 2477056918 ps
CPU time 2.65 seconds
Started Apr 02 01:03:44 PM PDT 24
Finished Apr 02 01:03:47 PM PDT 24
Peak memory 201952 kb
Host smart-ded2ae1e-5f34-4a64-ac89-3f57539f7f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166503084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.166503084
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.875172313
Short name T487
Test name
Test status
Simulation time 2113669194 ps
CPU time 3.3 seconds
Started Apr 02 01:03:45 PM PDT 24
Finished Apr 02 01:03:48 PM PDT 24
Peak memory 201884 kb
Host smart-94db508b-8f8f-4dee-a3cc-cc0f6a7f4b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875172313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.875172313
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2728248411
Short name T597
Test name
Test status
Simulation time 2521921069 ps
CPU time 4.38 seconds
Started Apr 02 01:03:47 PM PDT 24
Finished Apr 02 01:03:52 PM PDT 24
Peak memory 201912 kb
Host smart-57155319-7632-4a89-8c92-4a7ccff4c33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728248411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.2728248411
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.2973109845
Short name T161
Test name
Test status
Simulation time 2134248231 ps
CPU time 2.02 seconds
Started Apr 02 01:03:46 PM PDT 24
Finished Apr 02 01:03:48 PM PDT 24
Peak memory 201880 kb
Host smart-bf5b7c63-5922-4256-b701-b595fec17965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973109845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2973109845
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.1345904884
Short name T192
Test name
Test status
Simulation time 11185388396 ps
CPU time 7.72 seconds
Started Apr 02 01:03:53 PM PDT 24
Finished Apr 02 01:04:02 PM PDT 24
Peak memory 201996 kb
Host smart-b03c31cf-263c-4008-b6c7-0887da68396b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345904884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.1345904884
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2758917135
Short name T275
Test name
Test status
Simulation time 39910074176 ps
CPU time 102.67 seconds
Started Apr 02 01:03:51 PM PDT 24
Finished Apr 02 01:05:34 PM PDT 24
Peak memory 217952 kb
Host smart-fb018c90-662a-42bd-bffc-daf9e0e38700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758917135 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.2758917135
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2762935951
Short name T128
Test name
Test status
Simulation time 5668977582 ps
CPU time 2.57 seconds
Started Apr 02 01:03:45 PM PDT 24
Finished Apr 02 01:03:48 PM PDT 24
Peak memory 201928 kb
Host smart-b3a9419b-fe3c-4598-8ce4-d3e22fff553e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762935951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.2762935951
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.3639204849
Short name T358
Test name
Test status
Simulation time 2011735669 ps
CPU time 5.59 seconds
Started Apr 02 01:04:11 PM PDT 24
Finished Apr 02 01:04:17 PM PDT 24
Peak memory 201864 kb
Host smart-28d73ac8-c08c-4841-93f4-c29b843ca9ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639204849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.3639204849
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.578824435
Short name T708
Test name
Test status
Simulation time 3086849120 ps
CPU time 2.44 seconds
Started Apr 02 01:03:53 PM PDT 24
Finished Apr 02 01:03:56 PM PDT 24
Peak memory 202060 kb
Host smart-38ad517f-13d4-4e1e-b035-32737c6a2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578824435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.578824435
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3557352251
Short name T677
Test name
Test status
Simulation time 147561855346 ps
CPU time 48.98 seconds
Started Apr 02 01:03:58 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 202196 kb
Host smart-e514cd23-1524-4f16-bd25-80b7852afd50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557352251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.3557352251
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3526580949
Short name T391
Test name
Test status
Simulation time 3110942995 ps
CPU time 8.39 seconds
Started Apr 02 01:03:50 PM PDT 24
Finished Apr 02 01:03:58 PM PDT 24
Peak memory 201972 kb
Host smart-7fad463d-a4fc-4149-9349-c2e234252330
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526580949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.3526580949
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.8406355
Short name T712
Test name
Test status
Simulation time 3824661588 ps
CPU time 5.36 seconds
Started Apr 02 01:03:55 PM PDT 24
Finished Apr 02 01:04:03 PM PDT 24
Peak memory 201932 kb
Host smart-7ff78d59-5c0e-4b08-a056-d8acae74269b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8406355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_
edge_detect.8406355
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1080713949
Short name T219
Test name
Test status
Simulation time 2633182170 ps
CPU time 2.37 seconds
Started Apr 02 01:03:49 PM PDT 24
Finished Apr 02 01:03:52 PM PDT 24
Peak memory 201880 kb
Host smart-1197a315-5a00-4d14-a60a-181fec13f37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080713949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.1080713949
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1246578080
Short name T187
Test name
Test status
Simulation time 2466473373 ps
CPU time 3.62 seconds
Started Apr 02 01:03:55 PM PDT 24
Finished Apr 02 01:03:59 PM PDT 24
Peak memory 201948 kb
Host smart-fcfaa184-c0b9-436e-8cf0-e3b1cc38fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246578080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1246578080
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.4173389837
Short name T387
Test name
Test status
Simulation time 2108784043 ps
CPU time 3.46 seconds
Started Apr 02 01:03:49 PM PDT 24
Finished Apr 02 01:03:53 PM PDT 24
Peak memory 201876 kb
Host smart-843d873c-5a90-43f4-b354-25b681fad1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173389837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.4173389837
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1093624136
Short name T779
Test name
Test status
Simulation time 2543162901 ps
CPU time 1.81 seconds
Started Apr 02 01:03:48 PM PDT 24
Finished Apr 02 01:03:50 PM PDT 24
Peak memory 201908 kb
Host smart-7a4a38d5-c3ac-4ac2-bd3c-424974fa5cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093624136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.1093624136
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.3817944831
Short name T186
Test name
Test status
Simulation time 2123301826 ps
CPU time 3.25 seconds
Started Apr 02 01:03:47 PM PDT 24
Finished Apr 02 01:03:51 PM PDT 24
Peak memory 201864 kb
Host smart-9fb42515-9395-4968-a865-eafcc96a9a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817944831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3817944831
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.3752122982
Short name T71
Test name
Test status
Simulation time 18569963730 ps
CPU time 21.32 seconds
Started Apr 02 01:03:56 PM PDT 24
Finished Apr 02 01:04:19 PM PDT 24
Peak memory 201700 kb
Host smart-b993405d-2fb5-4045-97b6-f35054866793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752122982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.3752122982
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.679264577
Short name T24
Test name
Test status
Simulation time 5575470694 ps
CPU time 2.76 seconds
Started Apr 02 01:03:48 PM PDT 24
Finished Apr 02 01:03:51 PM PDT 24
Peak memory 201848 kb
Host smart-5bec5c56-f409-45bb-a191-ee3adfdca2b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679264577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ultra_low_pwr.679264577
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1197888645
Short name T508
Test name
Test status
Simulation time 2014439197 ps
CPU time 4.61 seconds
Started Apr 02 01:02:37 PM PDT 24
Finished Apr 02 01:02:42 PM PDT 24
Peak memory 201988 kb
Host smart-cdedc835-9068-4579-b30b-645c1222a612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197888645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1197888645
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.759413468
Short name T50
Test name
Test status
Simulation time 330682466821 ps
CPU time 887.15 seconds
Started Apr 02 01:02:35 PM PDT 24
Finished Apr 02 01:17:23 PM PDT 24
Peak memory 202004 kb
Host smart-b7bdbcbc-ae7f-475f-bd02-9cdedbb3e666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759413468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.759413468
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3400208398
Short name T31
Test name
Test status
Simulation time 149333980187 ps
CPU time 406.46 seconds
Started Apr 02 01:02:50 PM PDT 24
Finished Apr 02 01:09:37 PM PDT 24
Peak memory 202180 kb
Host smart-55b46d3d-947d-406a-a06b-fc5fab281685
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400208398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.3400208398
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3664696297
Short name T401
Test name
Test status
Simulation time 2234133017 ps
CPU time 6.69 seconds
Started Apr 02 01:02:36 PM PDT 24
Finished Apr 02 01:02:43 PM PDT 24
Peak memory 201908 kb
Host smart-14d60109-ec18-4664-816a-257ea91d273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664696297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3664696297
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.783723319
Short name T623
Test name
Test status
Simulation time 2325065727 ps
CPU time 1.78 seconds
Started Apr 02 01:02:37 PM PDT 24
Finished Apr 02 01:02:39 PM PDT 24
Peak memory 201800 kb
Host smart-9dc4bb5a-fd54-4627-b917-18cceb0f4319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783723319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.783723319
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2700972400
Short name T702
Test name
Test status
Simulation time 59492477700 ps
CPU time 95.57 seconds
Started Apr 02 01:02:38 PM PDT 24
Finished Apr 02 01:04:14 PM PDT 24
Peak memory 202184 kb
Host smart-316b9e54-d7be-45e6-b574-671afcd7e643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700972400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.2700972400
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2252407916
Short name T154
Test name
Test status
Simulation time 3528641841 ps
CPU time 3.05 seconds
Started Apr 02 01:02:36 PM PDT 24
Finished Apr 02 01:02:39 PM PDT 24
Peak memory 201812 kb
Host smart-c48a8f20-d830-4ab2-8a64-f60704559d5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252407916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.2252407916
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.1153123358
Short name T101
Test name
Test status
Simulation time 2500068127 ps
CPU time 4.22 seconds
Started Apr 02 01:02:50 PM PDT 24
Finished Apr 02 01:02:54 PM PDT 24
Peak memory 201952 kb
Host smart-770b3628-13ad-45c1-8f9d-e65fc09bf0ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153123358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.1153123358
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.179027107
Short name T541
Test name
Test status
Simulation time 2632244857 ps
CPU time 2.35 seconds
Started Apr 02 01:02:35 PM PDT 24
Finished Apr 02 01:02:37 PM PDT 24
Peak memory 201844 kb
Host smart-08314205-7594-4827-a014-fc5a542f2a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179027107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.179027107
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.753795398
Short name T590
Test name
Test status
Simulation time 2479490736 ps
CPU time 8.03 seconds
Started Apr 02 01:02:36 PM PDT 24
Finished Apr 02 01:02:44 PM PDT 24
Peak memory 201996 kb
Host smart-f31a3b99-6b40-4a72-87f3-9bae286553cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753795398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.753795398
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2813801050
Short name T740
Test name
Test status
Simulation time 2061095178 ps
CPU time 1.83 seconds
Started Apr 02 01:02:35 PM PDT 24
Finished Apr 02 01:02:37 PM PDT 24
Peak memory 201848 kb
Host smart-0408d789-fc9c-4e5d-876c-6045150e7829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813801050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2813801050
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.59316203
Short name T425
Test name
Test status
Simulation time 2545027240 ps
CPU time 1.73 seconds
Started Apr 02 01:02:35 PM PDT 24
Finished Apr 02 01:02:37 PM PDT 24
Peak memory 201920 kb
Host smart-19eac60d-552b-478d-82a3-06b5c81ed84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59316203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.59316203
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.2565448573
Short name T79
Test name
Test status
Simulation time 22017433428 ps
CPU time 29.92 seconds
Started Apr 02 01:02:40 PM PDT 24
Finished Apr 02 01:03:10 PM PDT 24
Peak memory 221740 kb
Host smart-0b11424e-2ca7-4d10-af12-2b4e04d7db15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565448573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.2565448573
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.1763344154
Short name T648
Test name
Test status
Simulation time 2111975504 ps
CPU time 6.15 seconds
Started Apr 02 01:02:37 PM PDT 24
Finished Apr 02 01:02:43 PM PDT 24
Peak memory 201880 kb
Host smart-b3a3b06b-a9e4-4356-a2ee-8e95349d9cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763344154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.1763344154
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.433001250
Short name T155
Test name
Test status
Simulation time 108439060777 ps
CPU time 70.67 seconds
Started Apr 02 01:02:39 PM PDT 24
Finished Apr 02 01:03:50 PM PDT 24
Peak memory 202152 kb
Host smart-0e8e9ba4-0d04-4172-b973-30fdcf192002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433001250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_str
ess_all.433001250
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2426755774
Short name T727
Test name
Test status
Simulation time 332670939179 ps
CPU time 21.49 seconds
Started Apr 02 01:02:39 PM PDT 24
Finished Apr 02 01:03:01 PM PDT 24
Peak memory 210556 kb
Host smart-36dc8bbe-3c48-468e-ad60-dc02a6c7afc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426755774 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.2426755774
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3981983291
Short name T164
Test name
Test status
Simulation time 4509518084 ps
CPU time 2.09 seconds
Started Apr 02 01:02:40 PM PDT 24
Finished Apr 02 01:02:43 PM PDT 24
Peak memory 201956 kb
Host smart-3f8e221b-69b5-4aec-b759-180ed2286c8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981983291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.3981983291
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.552228811
Short name T352
Test name
Test status
Simulation time 2016530898 ps
CPU time 3.32 seconds
Started Apr 02 01:03:54 PM PDT 24
Finished Apr 02 01:03:58 PM PDT 24
Peak memory 202064 kb
Host smart-44a2ef2c-0d7d-4348-b8a9-24d2b8a4bed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552228811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_tes
t.552228811
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.530013677
Short name T661
Test name
Test status
Simulation time 3591571180 ps
CPU time 1.22 seconds
Started Apr 02 01:03:55 PM PDT 24
Finished Apr 02 01:03:56 PM PDT 24
Peak memory 201980 kb
Host smart-ee73cb40-3190-45cd-b567-25b08a3e4a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530013677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.530013677
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.2553748700
Short name T113
Test name
Test status
Simulation time 80335633838 ps
CPU time 50.28 seconds
Started Apr 02 01:03:58 PM PDT 24
Finished Apr 02 01:04:48 PM PDT 24
Peak memory 201984 kb
Host smart-da5f5497-451a-42b7-866e-f521a6072716
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553748700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.2553748700
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2135897129
Short name T691
Test name
Test status
Simulation time 36290617993 ps
CPU time 27.6 seconds
Started Apr 02 01:03:57 PM PDT 24
Finished Apr 02 01:04:25 PM PDT 24
Peak memory 202132 kb
Host smart-9e617b2c-300f-4046-a940-9b7a33cb792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135897129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.2135897129
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.908541955
Short name T20
Test name
Test status
Simulation time 3213616524 ps
CPU time 2.32 seconds
Started Apr 02 01:03:54 PM PDT 24
Finished Apr 02 01:03:57 PM PDT 24
Peak memory 201980 kb
Host smart-02e28c0d-5bc8-4fc2-a708-b8f6fec0294d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908541955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_ec_pwr_on_rst.908541955
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.947827427
Short name T168
Test name
Test status
Simulation time 3223727720 ps
CPU time 9.01 seconds
Started Apr 02 01:03:58 PM PDT 24
Finished Apr 02 01:04:07 PM PDT 24
Peak memory 201828 kb
Host smart-bbc15503-48f4-44ed-bbba-b6d0c7800de0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947827427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctr
l_edge_detect.947827427
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1845524113
Short name T209
Test name
Test status
Simulation time 2637690764 ps
CPU time 2.43 seconds
Started Apr 02 01:03:52 PM PDT 24
Finished Apr 02 01:03:55 PM PDT 24
Peak memory 201940 kb
Host smart-410c7a0d-1e98-4007-9648-7648ad5a07f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845524113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.1845524113
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.78749206
Short name T632
Test name
Test status
Simulation time 2467387387 ps
CPU time 6.63 seconds
Started Apr 02 01:03:52 PM PDT 24
Finished Apr 02 01:03:59 PM PDT 24
Peak memory 201948 kb
Host smart-435469da-98d8-4230-851b-8b070d9d7427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78749206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.78749206
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.3194503531
Short name T732
Test name
Test status
Simulation time 2068585614 ps
CPU time 3.23 seconds
Started Apr 02 01:03:58 PM PDT 24
Finished Apr 02 01:04:01 PM PDT 24
Peak memory 201732 kb
Host smart-630a0339-05a2-4edf-8304-f070feeb9f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194503531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3194503531
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.1565853715
Short name T475
Test name
Test status
Simulation time 2514488141 ps
CPU time 4.67 seconds
Started Apr 02 01:03:57 PM PDT 24
Finished Apr 02 01:04:02 PM PDT 24
Peak memory 201964 kb
Host smart-189d4218-5f01-42cc-bd6e-34a625dffc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565853715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.1565853715
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.1255378202
Short name T409
Test name
Test status
Simulation time 2110291472 ps
CPU time 6.5 seconds
Started Apr 02 01:03:54 PM PDT 24
Finished Apr 02 01:04:01 PM PDT 24
Peak memory 201864 kb
Host smart-1cbfe2ef-7221-460d-9cb5-a48a6a474a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255378202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1255378202
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.3516138224
Short name T339
Test name
Test status
Simulation time 15687189568 ps
CPU time 19.55 seconds
Started Apr 02 01:03:54 PM PDT 24
Finished Apr 02 01:04:14 PM PDT 24
Peak memory 201980 kb
Host smart-9c60b86b-a6bf-4a2d-959b-7361e53a95a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516138224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.3516138224
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1667655418
Short name T180
Test name
Test status
Simulation time 105470428294 ps
CPU time 49.77 seconds
Started Apr 02 01:03:56 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 210320 kb
Host smart-d900c494-bcc9-4566-87d6-2cab2a759051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667655418 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1667655418
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.415617415
Short name T12
Test name
Test status
Simulation time 4514913721 ps
CPU time 7.64 seconds
Started Apr 02 01:03:57 PM PDT 24
Finished Apr 02 01:04:05 PM PDT 24
Peak memory 201956 kb
Host smart-a248950b-9f28-4b14-8563-f4296d8d315c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415617415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_ultra_low_pwr.415617415
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.3841343521
Short name T625
Test name
Test status
Simulation time 2038861339 ps
CPU time 2.05 seconds
Started Apr 02 01:04:00 PM PDT 24
Finished Apr 02 01:04:02 PM PDT 24
Peak memory 202036 kb
Host smart-2034e11b-9d7a-457c-8169-b1d7db07cc5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841343521 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.3841343521
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.995681847
Short name T169
Test name
Test status
Simulation time 174846495549 ps
CPU time 77.98 seconds
Started Apr 02 01:03:59 PM PDT 24
Finished Apr 02 01:05:17 PM PDT 24
Peak memory 201956 kb
Host smart-a7b4d4f7-4f5f-447b-a10a-d5bdb973a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995681847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.995681847
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.4162548780
Short name T216
Test name
Test status
Simulation time 75782244991 ps
CPU time 15.24 seconds
Started Apr 02 01:04:00 PM PDT 24
Finished Apr 02 01:04:15 PM PDT 24
Peak memory 202200 kb
Host smart-05e14edb-f1fa-4263-8df0-02f1cd831d44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162548780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.4162548780
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.3979636434
Short name T236
Test name
Test status
Simulation time 2970329435 ps
CPU time 1.91 seconds
Started Apr 02 01:03:59 PM PDT 24
Finished Apr 02 01:04:01 PM PDT 24
Peak memory 201928 kb
Host smart-f7fda676-0014-42a1-9de0-22d5078a1553
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979636434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.3979636434
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.409062157
Short name T393
Test name
Test status
Simulation time 2728917035 ps
CPU time 1.24 seconds
Started Apr 02 01:03:57 PM PDT 24
Finished Apr 02 01:03:59 PM PDT 24
Peak memory 201952 kb
Host smart-38d449d4-81ca-4dad-9ef7-1a7f65d11881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409062157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.409062157
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3132346032
Short name T6
Test name
Test status
Simulation time 2503659615 ps
CPU time 1.25 seconds
Started Apr 02 01:03:56 PM PDT 24
Finished Apr 02 01:03:59 PM PDT 24
Peak memory 201948 kb
Host smart-4be60495-3512-479d-acc2-2c2d7b515953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132346032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.3132346032
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.2014053215
Short name T527
Test name
Test status
Simulation time 2185530830 ps
CPU time 2.02 seconds
Started Apr 02 01:03:57 PM PDT 24
Finished Apr 02 01:04:00 PM PDT 24
Peak memory 201844 kb
Host smart-377103f0-f67c-45fd-87a2-97bbb9ce8059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014053215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.2014053215
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.2324261408
Short name T566
Test name
Test status
Simulation time 2517719169 ps
CPU time 3.49 seconds
Started Apr 02 01:03:58 PM PDT 24
Finished Apr 02 01:04:02 PM PDT 24
Peak memory 201804 kb
Host smart-04115260-e90e-4811-bdd2-5ff4214d4a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324261408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.2324261408
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.1580027447
Short name T253
Test name
Test status
Simulation time 2110332409 ps
CPU time 5.98 seconds
Started Apr 02 01:03:53 PM PDT 24
Finished Apr 02 01:03:59 PM PDT 24
Peak memory 201852 kb
Host smart-f47e6123-9ec7-48d9-9b68-1a7f248b3031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580027447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1580027447
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.631794651
Short name T407
Test name
Test status
Simulation time 13390937784 ps
CPU time 8.47 seconds
Started Apr 02 01:03:56 PM PDT 24
Finished Apr 02 01:04:06 PM PDT 24
Peak memory 201948 kb
Host smart-9ce53dd0-0b82-4f15-85ae-74ecf8394f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631794651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_st
ress_all.631794651
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.243329937
Short name T104
Test name
Test status
Simulation time 5811718393 ps
CPU time 7.4 seconds
Started Apr 02 01:03:57 PM PDT 24
Finished Apr 02 01:04:05 PM PDT 24
Peak memory 201792 kb
Host smart-5cec2951-87be-4ea3-9f53-e2bf61a4b262
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243329937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_ultra_low_pwr.243329937
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.780554247
Short name T399
Test name
Test status
Simulation time 2032453729 ps
CPU time 1.9 seconds
Started Apr 02 01:04:04 PM PDT 24
Finished Apr 02 01:04:06 PM PDT 24
Peak memory 202020 kb
Host smart-3c1565ae-e39f-41db-9f37-36183ed617b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780554247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_tes
t.780554247
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2534092110
Short name T266
Test name
Test status
Simulation time 3041220762 ps
CPU time 8.46 seconds
Started Apr 02 01:04:02 PM PDT 24
Finished Apr 02 01:04:10 PM PDT 24
Peak memory 201976 kb
Host smart-78975be1-8217-41ff-9e61-7576b07cd293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534092110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2
534092110
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1130142078
Short name T112
Test name
Test status
Simulation time 142459134042 ps
CPU time 101.62 seconds
Started Apr 02 01:04:06 PM PDT 24
Finished Apr 02 01:05:48 PM PDT 24
Peak memory 202136 kb
Host smart-73ff59df-f332-480f-8eaf-0da46060b020
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130142078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.1130142078
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1544604523
Short name T249
Test name
Test status
Simulation time 99362519134 ps
CPU time 242.44 seconds
Started Apr 02 01:04:04 PM PDT 24
Finished Apr 02 01:08:07 PM PDT 24
Peak memory 202168 kb
Host smart-65e09243-2e22-4247-8696-bd5a42fc42e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544604523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.1544604523
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.4025045155
Short name T124
Test name
Test status
Simulation time 4446380475 ps
CPU time 7.14 seconds
Started Apr 02 01:04:02 PM PDT 24
Finished Apr 02 01:04:10 PM PDT 24
Peak memory 201912 kb
Host smart-bb06733a-4596-46b7-9ab5-1ae97b6eec92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025045155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.4025045155
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.3568575839
Short name T211
Test name
Test status
Simulation time 3497082099 ps
CPU time 2.97 seconds
Started Apr 02 01:04:05 PM PDT 24
Finished Apr 02 01:04:08 PM PDT 24
Peak memory 201936 kb
Host smart-33de97b8-c561-4777-83a3-ca117c72f808
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568575839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.3568575839
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3411597897
Short name T466
Test name
Test status
Simulation time 2633900448 ps
CPU time 2.65 seconds
Started Apr 02 01:04:01 PM PDT 24
Finished Apr 02 01:04:04 PM PDT 24
Peak memory 201936 kb
Host smart-c4ef37a5-0025-4662-bb21-00616dc0c70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411597897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3411597897
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2976793028
Short name T705
Test name
Test status
Simulation time 2450619111 ps
CPU time 6.94 seconds
Started Apr 02 01:03:57 PM PDT 24
Finished Apr 02 01:04:05 PM PDT 24
Peak memory 201920 kb
Host smart-e9b8bf85-f51b-4189-a2f6-aaa6213e0fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976793028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2976793028
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.47194263
Short name T783
Test name
Test status
Simulation time 2053512251 ps
CPU time 5.8 seconds
Started Apr 02 01:03:58 PM PDT 24
Finished Apr 02 01:04:04 PM PDT 24
Peak memory 201780 kb
Host smart-f6ba2a5f-eda9-4be0-88af-7660235ae3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47194263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.47194263
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2062338084
Short name T461
Test name
Test status
Simulation time 2515543746 ps
CPU time 4.06 seconds
Started Apr 02 01:03:58 PM PDT 24
Finished Apr 02 01:04:02 PM PDT 24
Peak memory 201956 kb
Host smart-2765dbc5-8225-4f88-ab8a-2727e13090fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062338084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2062338084
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.2995884708
Short name T738
Test name
Test status
Simulation time 2121127789 ps
CPU time 3.21 seconds
Started Apr 02 01:03:58 PM PDT 24
Finished Apr 02 01:04:01 PM PDT 24
Peak memory 201828 kb
Host smart-89711382-88c0-415c-a18a-e5d0fbdf2403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995884708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2995884708
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.1803361804
Short name T142
Test name
Test status
Simulation time 76035537163 ps
CPU time 198.46 seconds
Started Apr 02 01:04:03 PM PDT 24
Finished Apr 02 01:07:22 PM PDT 24
Peak memory 202152 kb
Host smart-be7cb57b-287c-4871-ba8e-6087374b901e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803361804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.1803361804
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.931776728
Short name T273
Test name
Test status
Simulation time 4770337689 ps
CPU time 3.77 seconds
Started Apr 02 01:04:07 PM PDT 24
Finished Apr 02 01:04:11 PM PDT 24
Peak memory 201936 kb
Host smart-4c60f0d3-33c4-4637-ada4-28a4f981d688
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931776728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_ultra_low_pwr.931776728
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.2851083984
Short name T722
Test name
Test status
Simulation time 2010713421 ps
CPU time 6 seconds
Started Apr 02 01:04:10 PM PDT 24
Finished Apr 02 01:04:17 PM PDT 24
Peak memory 202020 kb
Host smart-f24ed1a6-2e02-4df8-a8c8-d13f865b799f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851083984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.2851083984
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2862733472
Short name T261
Test name
Test status
Simulation time 290748012753 ps
CPU time 391.95 seconds
Started Apr 02 01:04:10 PM PDT 24
Finished Apr 02 01:10:44 PM PDT 24
Peak memory 201996 kb
Host smart-5d9c8ea7-205d-4add-bdfe-57f9a8b91368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862733472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2
862733472
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3895750784
Short name T297
Test name
Test status
Simulation time 120730164632 ps
CPU time 162.18 seconds
Started Apr 02 01:04:07 PM PDT 24
Finished Apr 02 01:06:50 PM PDT 24
Peak memory 202132 kb
Host smart-03ccef0d-a98d-42ff-9463-53fe2dcefe1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895750784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_combo_detect.3895750784
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.813639488
Short name T260
Test name
Test status
Simulation time 3440225941 ps
CPU time 2.9 seconds
Started Apr 02 01:04:07 PM PDT 24
Finished Apr 02 01:04:10 PM PDT 24
Peak memory 201916 kb
Host smart-1577591b-1329-454d-8bfb-425436cc80a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813639488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c
trl_ec_pwr_on_rst.813639488
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1601009817
Short name T531
Test name
Test status
Simulation time 2666570041 ps
CPU time 1.6 seconds
Started Apr 02 01:04:10 PM PDT 24
Finished Apr 02 01:04:13 PM PDT 24
Peak memory 201948 kb
Host smart-94468aff-fbb1-4d02-b5ae-0610b008bc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601009817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.1601009817
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2639906119
Short name T484
Test name
Test status
Simulation time 2458274460 ps
CPU time 2.1 seconds
Started Apr 02 01:04:05 PM PDT 24
Finished Apr 02 01:04:07 PM PDT 24
Peak memory 201944 kb
Host smart-13eca8b2-76fd-4805-ae35-343ef96f0639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639906119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2639906119
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.2664458866
Short name T681
Test name
Test status
Simulation time 2075290095 ps
CPU time 1.46 seconds
Started Apr 02 01:04:07 PM PDT 24
Finished Apr 02 01:04:09 PM PDT 24
Peak memory 201740 kb
Host smart-63621851-eeba-46bf-ae77-768530d5f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664458866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.2664458866
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2165435423
Short name T750
Test name
Test status
Simulation time 2512465690 ps
CPU time 7.03 seconds
Started Apr 02 01:04:08 PM PDT 24
Finished Apr 02 01:04:15 PM PDT 24
Peak memory 201932 kb
Host smart-e3972f5d-078e-44eb-b27b-2789d16c3284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165435423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2165435423
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.3298476911
Short name T395
Test name
Test status
Simulation time 2127931783 ps
CPU time 2.06 seconds
Started Apr 02 01:04:03 PM PDT 24
Finished Apr 02 01:04:06 PM PDT 24
Peak memory 201804 kb
Host smart-3d224ace-577d-43fb-a441-e7db2cb19b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298476911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3298476911
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.3401013779
Short name T723
Test name
Test status
Simulation time 13913482816 ps
CPU time 25.44 seconds
Started Apr 02 01:04:10 PM PDT 24
Finished Apr 02 01:04:37 PM PDT 24
Peak memory 201980 kb
Host smart-83c0b53b-64ea-4b3e-8980-0d7eeb6cb98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401013779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.3401013779
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.972240488
Short name T212
Test name
Test status
Simulation time 1964424419656 ps
CPU time 126.26 seconds
Started Apr 02 01:04:09 PM PDT 24
Finished Apr 02 01:06:15 PM PDT 24
Peak memory 214332 kb
Host smart-92d6d2a6-b565-4768-909c-1d16eb200132
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972240488 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.972240488
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3866656786
Short name T698
Test name
Test status
Simulation time 4405073529 ps
CPU time 1.61 seconds
Started Apr 02 01:04:11 PM PDT 24
Finished Apr 02 01:04:13 PM PDT 24
Peak memory 201956 kb
Host smart-58b74bf1-ee6f-4278-9202-e6644a9af7ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866656786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.3866656786
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.605937733
Short name T205
Test name
Test status
Simulation time 2016672502 ps
CPU time 5.57 seconds
Started Apr 02 01:04:13 PM PDT 24
Finished Apr 02 01:04:19 PM PDT 24
Peak memory 201988 kb
Host smart-2ceb9efa-8557-4427-a66f-6bbaf8a312e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605937733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_tes
t.605937733
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3431721254
Short name T656
Test name
Test status
Simulation time 3694948799 ps
CPU time 10.88 seconds
Started Apr 02 01:04:13 PM PDT 24
Finished Apr 02 01:04:24 PM PDT 24
Peak memory 201976 kb
Host smart-c91488ee-1826-4b2a-b85c-1c313a1217e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431721254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3
431721254
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2146735781
Short name T709
Test name
Test status
Simulation time 111017163886 ps
CPU time 315.45 seconds
Started Apr 02 01:04:13 PM PDT 24
Finished Apr 02 01:09:29 PM PDT 24
Peak memory 202024 kb
Host smart-42e2b986-e879-4aed-89ea-d8ec1741f25b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146735781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2146735781
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.154676131
Short name T731
Test name
Test status
Simulation time 103327222342 ps
CPU time 65.18 seconds
Started Apr 02 01:04:12 PM PDT 24
Finished Apr 02 01:05:18 PM PDT 24
Peak memory 202080 kb
Host smart-06a8ef20-61bb-4ff8-a9fe-8712e4a40f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154676131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_wi
th_pre_cond.154676131
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.960067862
Short name T476
Test name
Test status
Simulation time 3562920275 ps
CPU time 9.75 seconds
Started Apr 02 01:04:13 PM PDT 24
Finished Apr 02 01:04:23 PM PDT 24
Peak memory 201964 kb
Host smart-97eea0a8-d242-47ef-ba5f-d9335156a83c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960067862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_ec_pwr_on_rst.960067862
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.2545936255
Short name T190
Test name
Test status
Simulation time 2784570180 ps
CPU time 5.35 seconds
Started Apr 02 01:04:12 PM PDT 24
Finished Apr 02 01:04:17 PM PDT 24
Peak memory 201936 kb
Host smart-eb2dca2d-6e64-4286-95f1-488783ee193e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545936255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.2545936255
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3290360355
Short name T233
Test name
Test status
Simulation time 2633437542 ps
CPU time 2.28 seconds
Started Apr 02 01:04:07 PM PDT 24
Finished Apr 02 01:04:10 PM PDT 24
Peak memory 201932 kb
Host smart-8f2fb56c-75e6-4497-9fb2-0583f77bfb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290360355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.3290360355
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3393658424
Short name T719
Test name
Test status
Simulation time 2468260966 ps
CPU time 3.9 seconds
Started Apr 02 01:04:09 PM PDT 24
Finished Apr 02 01:04:15 PM PDT 24
Peak memory 201944 kb
Host smart-1cd1c68c-0b4b-4cb4-9201-3d97e4fcea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393658424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3393658424
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2537390945
Short name T679
Test name
Test status
Simulation time 2175585080 ps
CPU time 6.6 seconds
Started Apr 02 01:04:11 PM PDT 24
Finished Apr 02 01:04:18 PM PDT 24
Peak memory 201932 kb
Host smart-8286f0f1-b285-4d1d-abf6-8df2b91cd500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537390945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.2537390945
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.4239649215
Short name T434
Test name
Test status
Simulation time 2539047228 ps
CPU time 1.93 seconds
Started Apr 02 01:04:10 PM PDT 24
Finished Apr 02 01:04:13 PM PDT 24
Peak memory 201948 kb
Host smart-e5efd248-1f01-4a2d-8fd7-7424c797eb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239649215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.4239649215
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.1042632586
Short name T715
Test name
Test status
Simulation time 2128321575 ps
CPU time 1.94 seconds
Started Apr 02 01:04:11 PM PDT 24
Finished Apr 02 01:04:14 PM PDT 24
Peak memory 201852 kb
Host smart-4779292b-1515-46dd-b474-887ccc0a22c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042632586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1042632586
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.588657317
Short name T224
Test name
Test status
Simulation time 18296596147 ps
CPU time 11.06 seconds
Started Apr 02 01:04:11 PM PDT 24
Finished Apr 02 01:04:23 PM PDT 24
Peak memory 201904 kb
Host smart-11830fde-e0a3-4744-aa49-fda63ace6594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588657317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_st
ress_all.588657317
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2988078695
Short name T349
Test name
Test status
Simulation time 467429605626 ps
CPU time 32.84 seconds
Started Apr 02 01:04:14 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 217580 kb
Host smart-0da4d0f8-0d6c-4983-9b9a-0685576716f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988078695 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.2988078695
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1311293685
Short name T598
Test name
Test status
Simulation time 701942448448 ps
CPU time 30.91 seconds
Started Apr 02 01:04:13 PM PDT 24
Finished Apr 02 01:04:44 PM PDT 24
Peak memory 201900 kb
Host smart-811a01f7-a803-4cca-b3ce-d58dcde8adbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311293685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.1311293685
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.3300715636
Short name T173
Test name
Test status
Simulation time 2031426325 ps
CPU time 1.75 seconds
Started Apr 02 01:04:20 PM PDT 24
Finished Apr 02 01:04:22 PM PDT 24
Peak memory 202008 kb
Host smart-7c3758c7-968f-458a-bb87-14d8a0b57383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300715636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.3300715636
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1914693701
Short name T488
Test name
Test status
Simulation time 139326473019 ps
CPU time 177.56 seconds
Started Apr 02 01:04:12 PM PDT 24
Finished Apr 02 01:07:09 PM PDT 24
Peak memory 201980 kb
Host smart-0ba76798-566f-471c-80bc-0c3e3c935ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914693701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.1
914693701
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.4099096249
Short name T326
Test name
Test status
Simulation time 76566499056 ps
CPU time 104.95 seconds
Started Apr 02 01:04:13 PM PDT 24
Finished Apr 02 01:05:58 PM PDT 24
Peak memory 202028 kb
Host smart-9f92fdeb-1666-431f-9397-39a593c8d63d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099096249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.4099096249
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.3766630946
Short name T72
Test name
Test status
Simulation time 61102064305 ps
CPU time 40.14 seconds
Started Apr 02 01:04:17 PM PDT 24
Finished Apr 02 01:04:57 PM PDT 24
Peak memory 202104 kb
Host smart-b93e762c-03ea-4dcb-94b4-12ef70fa1224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766630946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.3766630946
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2051826865
Short name T608
Test name
Test status
Simulation time 2600158495 ps
CPU time 2.35 seconds
Started Apr 02 01:04:12 PM PDT 24
Finished Apr 02 01:04:16 PM PDT 24
Peak memory 201884 kb
Host smart-0de1a255-c215-401d-8892-1f74c2879d72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051826865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.2051826865
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.74170707
Short name T191
Test name
Test status
Simulation time 203544976256 ps
CPU time 17.78 seconds
Started Apr 02 01:04:19 PM PDT 24
Finished Apr 02 01:04:37 PM PDT 24
Peak memory 201920 kb
Host smart-342dab45-ac37-4e6a-b811-fb4b0e094ea7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74170707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl
_edge_detect.74170707
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3905643654
Short name T741
Test name
Test status
Simulation time 2632046377 ps
CPU time 2.54 seconds
Started Apr 02 01:04:12 PM PDT 24
Finished Apr 02 01:04:15 PM PDT 24
Peak memory 201876 kb
Host smart-3af78a71-2337-477f-b96e-346b5e80114d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905643654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3905643654
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.3515481749
Short name T377
Test name
Test status
Simulation time 2477496257 ps
CPU time 8.4 seconds
Started Apr 02 01:04:14 PM PDT 24
Finished Apr 02 01:04:22 PM PDT 24
Peak memory 201844 kb
Host smart-ee026db7-60cd-43ab-b809-55da7ecf4d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515481749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.3515481749
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.3280091326
Short name T447
Test name
Test status
Simulation time 2019004336 ps
CPU time 5.45 seconds
Started Apr 02 01:04:14 PM PDT 24
Finished Apr 02 01:04:20 PM PDT 24
Peak memory 201772 kb
Host smart-a5c658ce-5d72-45b7-b5d8-0fa0c247cfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280091326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.3280091326
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2023722741
Short name T357
Test name
Test status
Simulation time 2520357682 ps
CPU time 3.84 seconds
Started Apr 02 01:04:12 PM PDT 24
Finished Apr 02 01:04:16 PM PDT 24
Peak memory 201888 kb
Host smart-0d40ab26-ddda-4f5a-8385-31ddea4ea8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023722741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.2023722741
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.2097269939
Short name T587
Test name
Test status
Simulation time 2210479973 ps
CPU time 1.01 seconds
Started Apr 02 01:04:14 PM PDT 24
Finished Apr 02 01:04:15 PM PDT 24
Peak memory 201524 kb
Host smart-c61f8ff3-dcea-441b-baa7-e474516356b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097269939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2097269939
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.4161104389
Short name T728
Test name
Test status
Simulation time 97711454116 ps
CPU time 247.84 seconds
Started Apr 02 01:04:20 PM PDT 24
Finished Apr 02 01:08:28 PM PDT 24
Peak memory 202108 kb
Host smart-cd92c873-88be-4adc-b089-0a8dc6fa13ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161104389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.4161104389
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3322298185
Short name T743
Test name
Test status
Simulation time 60102162734 ps
CPU time 34.43 seconds
Started Apr 02 01:04:22 PM PDT 24
Finished Apr 02 01:04:57 PM PDT 24
Peak memory 210492 kb
Host smart-60459ad5-206e-471b-a9df-fd7a105782ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322298185 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.3322298185
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.1913809162
Short name T663
Test name
Test status
Simulation time 2019083436 ps
CPU time 3.12 seconds
Started Apr 02 01:04:18 PM PDT 24
Finished Apr 02 01:04:21 PM PDT 24
Peak memory 201852 kb
Host smart-9bc7b458-0f4d-438b-8268-3e43b9f12ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913809162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.1913809162
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.959958688
Short name T578
Test name
Test status
Simulation time 3411189404 ps
CPU time 8.89 seconds
Started Apr 02 01:04:18 PM PDT 24
Finished Apr 02 01:04:27 PM PDT 24
Peak memory 202024 kb
Host smart-0f4be8c2-ac71-4282-be46-f25d610fe88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959958688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.959958688
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.4219063648
Short name T245
Test name
Test status
Simulation time 28664674519 ps
CPU time 21.29 seconds
Started Apr 02 01:04:23 PM PDT 24
Finished Apr 02 01:04:44 PM PDT 24
Peak memory 202132 kb
Host smart-db40be3c-bb72-4375-924c-578a363e890b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219063648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.4219063648
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3373258321
Short name T309
Test name
Test status
Simulation time 61287498696 ps
CPU time 155.38 seconds
Started Apr 02 01:04:19 PM PDT 24
Finished Apr 02 01:06:54 PM PDT 24
Peak memory 202160 kb
Host smart-3c12342b-8fab-4a14-829a-89f2912030f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373258321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.3373258321
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1368125294
Short name T634
Test name
Test status
Simulation time 5168276433 ps
CPU time 1.74 seconds
Started Apr 02 01:04:19 PM PDT 24
Finished Apr 02 01:04:20 PM PDT 24
Peak memory 201928 kb
Host smart-bb85f16a-4cfe-44af-9694-d578110a1675
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368125294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.1368125294
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.3245686389
Short name T756
Test name
Test status
Simulation time 4240647094 ps
CPU time 11.33 seconds
Started Apr 02 01:04:18 PM PDT 24
Finished Apr 02 01:04:29 PM PDT 24
Peak memory 201916 kb
Host smart-e7cad60b-ebe3-48f6-8a9f-ba5a81c5058e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245686389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.3245686389
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2349731572
Short name T356
Test name
Test status
Simulation time 2674983582 ps
CPU time 1.16 seconds
Started Apr 02 01:04:23 PM PDT 24
Finished Apr 02 01:04:25 PM PDT 24
Peak memory 201904 kb
Host smart-98d66753-7abb-4a27-879b-f6962d22916b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349731572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.2349731572
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.3044462232
Short name T67
Test name
Test status
Simulation time 2482380723 ps
CPU time 2.42 seconds
Started Apr 02 01:04:23 PM PDT 24
Finished Apr 02 01:04:26 PM PDT 24
Peak memory 201920 kb
Host smart-2d539bae-f050-41ab-8a47-5b9e93b31ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044462232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.3044462232
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3433219874
Short name T710
Test name
Test status
Simulation time 2251251605 ps
CPU time 2.19 seconds
Started Apr 02 01:04:17 PM PDT 24
Finished Apr 02 01:04:19 PM PDT 24
Peak memory 201752 kb
Host smart-bd82d5e8-bdef-4fff-a30e-477b57ddade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433219874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.3433219874
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.708033430
Short name T384
Test name
Test status
Simulation time 2509943435 ps
CPU time 7.37 seconds
Started Apr 02 01:04:23 PM PDT 24
Finished Apr 02 01:04:31 PM PDT 24
Peak memory 201912 kb
Host smart-7d73bb2e-b169-4ddc-9e87-944e95287b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708033430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.708033430
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.4105741433
Short name T435
Test name
Test status
Simulation time 2120139126 ps
CPU time 3.46 seconds
Started Apr 02 01:04:21 PM PDT 24
Finished Apr 02 01:04:25 PM PDT 24
Peak memory 201856 kb
Host smart-3ae336a8-d80e-42a6-9dbf-ae3919994771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105741433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.4105741433
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.617156127
Short name T176
Test name
Test status
Simulation time 7616894511 ps
CPU time 8.72 seconds
Started Apr 02 01:04:21 PM PDT 24
Finished Apr 02 01:04:30 PM PDT 24
Peak memory 201948 kb
Host smart-1251bca4-3943-4a0a-b927-4b45d175a661
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617156127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.617156127
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.1001733245
Short name T235
Test name
Test status
Simulation time 2012309291 ps
CPU time 6.14 seconds
Started Apr 02 01:04:27 PM PDT 24
Finished Apr 02 01:04:35 PM PDT 24
Peak memory 201948 kb
Host smart-17613c16-e1d6-4c7f-b9fd-3d815b2c971e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001733245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.1001733245
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2939193232
Short name T523
Test name
Test status
Simulation time 3786952126 ps
CPU time 3.29 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:04:28 PM PDT 24
Peak memory 201992 kb
Host smart-1bc93c75-2563-4b84-9cd1-bf3a7f679350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939193232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2
939193232
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.2178992568
Short name T327
Test name
Test status
Simulation time 206038791263 ps
CPU time 136.52 seconds
Started Apr 02 01:04:27 PM PDT 24
Finished Apr 02 01:06:45 PM PDT 24
Peak memory 201936 kb
Host smart-e2e17247-7af8-4651-aa55-f38d6ea34d1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178992568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_combo_detect.2178992568
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3201981453
Short name T375
Test name
Test status
Simulation time 3648570494 ps
CPU time 2.31 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:04:26 PM PDT 24
Peak memory 201940 kb
Host smart-8355cc1b-23b8-41fe-9e0b-4c1ac775543f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201981453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.3201981453
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.324515489
Short name T640
Test name
Test status
Simulation time 3334001044 ps
CPU time 2.14 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:04:27 PM PDT 24
Peak memory 201948 kb
Host smart-da19af9f-9481-4ff6-a70b-6bac4d6379e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324515489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctr
l_edge_detect.324515489
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1218002971
Short name T52
Test name
Test status
Simulation time 2611236455 ps
CPU time 7.23 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:04:32 PM PDT 24
Peak memory 201916 kb
Host smart-b8191e76-c123-4f00-9a53-ae070eb63382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218002971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.1218002971
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2535540015
Short name T664
Test name
Test status
Simulation time 2448668286 ps
CPU time 3.76 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:04:29 PM PDT 24
Peak memory 201948 kb
Host smart-4a79d419-ba9c-432d-8577-ad04d2bf3651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535540015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2535540015
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.141193267
Short name T152
Test name
Test status
Simulation time 2210789390 ps
CPU time 2.47 seconds
Started Apr 02 01:04:25 PM PDT 24
Finished Apr 02 01:04:28 PM PDT 24
Peak memory 201760 kb
Host smart-ee0b580d-543a-45f3-b3f9-49facff78c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141193267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.141193267
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.117886761
Short name T234
Test name
Test status
Simulation time 2537407875 ps
CPU time 2.38 seconds
Started Apr 02 01:04:27 PM PDT 24
Finished Apr 02 01:04:31 PM PDT 24
Peak memory 201900 kb
Host smart-ff52b0c1-b383-471e-8ba8-801cdc9581f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117886761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.117886761
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.4235731343
Short name T470
Test name
Test status
Simulation time 2114597097 ps
CPU time 3.19 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:04:28 PM PDT 24
Peak memory 201868 kb
Host smart-ec47518f-494a-46e2-9af0-ca07fcbcb310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235731343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.4235731343
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.3901597824
Short name T507
Test name
Test status
Simulation time 7076919447 ps
CPU time 5.55 seconds
Started Apr 02 01:04:27 PM PDT 24
Finished Apr 02 01:04:34 PM PDT 24
Peak memory 201716 kb
Host smart-812484fb-9e19-4d26-8667-b8ee777fbf6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901597824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.3901597824
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.976166853
Short name T577
Test name
Test status
Simulation time 3141324856 ps
CPU time 5.79 seconds
Started Apr 02 01:04:26 PM PDT 24
Finished Apr 02 01:04:34 PM PDT 24
Peak memory 201876 kb
Host smart-aa8b4769-b509-460b-be68-2d8d168351e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976166853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c
trl_ultra_low_pwr.976166853
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.3369774318
Short name T568
Test name
Test status
Simulation time 2029115032 ps
CPU time 1.91 seconds
Started Apr 02 01:04:32 PM PDT 24
Finished Apr 02 01:04:35 PM PDT 24
Peak memory 202036 kb
Host smart-20eebdd3-1e54-4056-9645-6b028488666a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369774318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.3369774318
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2974741496
Short name T47
Test name
Test status
Simulation time 3537843473 ps
CPU time 2.2 seconds
Started Apr 02 01:04:23 PM PDT 24
Finished Apr 02 01:04:26 PM PDT 24
Peak memory 201944 kb
Host smart-3a06d786-3671-4f18-8be6-16689dca8ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974741496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.2
974741496
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.548896613
Short name T250
Test name
Test status
Simulation time 90343450520 ps
CPU time 233.39 seconds
Started Apr 02 01:04:25 PM PDT 24
Finished Apr 02 01:08:19 PM PDT 24
Peak memory 202116 kb
Host smart-32c25cbe-107f-4b38-86cf-222d0083bfed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548896613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_combo_detect.548896613
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2082539166
Short name T581
Test name
Test status
Simulation time 26331339142 ps
CPU time 73.78 seconds
Started Apr 02 01:04:22 PM PDT 24
Finished Apr 02 01:05:37 PM PDT 24
Peak memory 202212 kb
Host smart-6f44072e-33c3-4324-a015-c9e6604ea7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082539166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.2082539166
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2507989408
Short name T451
Test name
Test status
Simulation time 2975393450 ps
CPU time 8.38 seconds
Started Apr 02 01:04:25 PM PDT 24
Finished Apr 02 01:04:34 PM PDT 24
Peak memory 201916 kb
Host smart-4e16f366-1314-48b9-a007-3ca35084cded
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507989408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.2507989408
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.2828991781
Short name T39
Test name
Test status
Simulation time 5197516358 ps
CPU time 10.41 seconds
Started Apr 02 01:04:23 PM PDT 24
Finished Apr 02 01:04:34 PM PDT 24
Peak memory 201840 kb
Host smart-2b3e654b-7fed-4e17-8ea8-e867473e8cb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828991781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.2828991781
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2393883293
Short name T443
Test name
Test status
Simulation time 2612513993 ps
CPU time 6.91 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:04:32 PM PDT 24
Peak memory 201800 kb
Host smart-d3da3ad6-ed77-4649-a4ba-4415a8784f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393883293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.2393883293
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1163075491
Short name T418
Test name
Test status
Simulation time 2475803794 ps
CPU time 2.34 seconds
Started Apr 02 01:04:25 PM PDT 24
Finished Apr 02 01:04:28 PM PDT 24
Peak memory 201924 kb
Host smart-8b63c2f3-8f2b-4035-bf62-0d5b190f4ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163075491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.1163075491
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.3179794210
Short name T380
Test name
Test status
Simulation time 2122308170 ps
CPU time 5.92 seconds
Started Apr 02 01:04:26 PM PDT 24
Finished Apr 02 01:04:34 PM PDT 24
Peak memory 201804 kb
Host smart-f736abd8-a498-4246-9a92-daa067aa85bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179794210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.3179794210
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.706839002
Short name T163
Test name
Test status
Simulation time 2517967383 ps
CPU time 4.13 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:04:29 PM PDT 24
Peak memory 201904 kb
Host smart-f31b4466-dfda-4653-be0e-fed499ae979b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706839002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.706839002
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.1275702258
Short name T626
Test name
Test status
Simulation time 2137318834 ps
CPU time 1.94 seconds
Started Apr 02 01:04:24 PM PDT 24
Finished Apr 02 01:04:27 PM PDT 24
Peak memory 201852 kb
Host smart-6b4aa7b6-9c51-47c6-9963-1d5fbb04688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275702258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.1275702258
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3496549894
Short name T167
Test name
Test status
Simulation time 11063456841 ps
CPU time 28.65 seconds
Started Apr 02 01:04:29 PM PDT 24
Finished Apr 02 01:04:59 PM PDT 24
Peak memory 201940 kb
Host smart-e24fb8c0-5a39-49d2-bdde-20ca52153c0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496549894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3496549894
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.4016972040
Short name T127
Test name
Test status
Simulation time 59633822855 ps
CPU time 137.83 seconds
Started Apr 02 01:04:30 PM PDT 24
Finished Apr 02 01:06:49 PM PDT 24
Peak memory 210444 kb
Host smart-ca6d4e47-d67c-4263-a640-9c1b34614d9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016972040 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.4016972040
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3717995144
Short name T201
Test name
Test status
Simulation time 148649640403 ps
CPU time 3.2 seconds
Started Apr 02 01:04:26 PM PDT 24
Finished Apr 02 01:04:31 PM PDT 24
Peak memory 201828 kb
Host smart-2b0d1fe1-1b2d-45ba-b0aa-db79429e77e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717995144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.3717995144
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.1818749850
Short name T439
Test name
Test status
Simulation time 2027632749 ps
CPU time 1.69 seconds
Started Apr 02 01:04:29 PM PDT 24
Finished Apr 02 01:04:32 PM PDT 24
Peak memory 202052 kb
Host smart-3cf6c3ee-a4f7-40e4-9150-939bbe4ed2b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818749850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.1818749850
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3221898756
Short name T296
Test name
Test status
Simulation time 3394304883 ps
CPU time 4.75 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:04:45 PM PDT 24
Peak memory 202012 kb
Host smart-760a5b59-9e9b-420c-8a13-f5a35dd3fd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221898756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3
221898756
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.2820402647
Short name T242
Test name
Test status
Simulation time 202184275377 ps
CPU time 132.54 seconds
Started Apr 02 01:04:31 PM PDT 24
Finished Apr 02 01:06:46 PM PDT 24
Peak memory 202152 kb
Host smart-3731c91c-1b36-46cf-8c59-42070e765c3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820402647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.2820402647
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.4114808150
Short name T693
Test name
Test status
Simulation time 3648108771 ps
CPU time 1.43 seconds
Started Apr 02 01:04:30 PM PDT 24
Finished Apr 02 01:04:32 PM PDT 24
Peak memory 201896 kb
Host smart-d2386ca9-89a8-4daa-a020-77e42899b670
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114808150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.4114808150
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.1164024966
Short name T594
Test name
Test status
Simulation time 4256964062 ps
CPU time 4.33 seconds
Started Apr 02 01:04:29 PM PDT 24
Finished Apr 02 01:04:34 PM PDT 24
Peak memory 201964 kb
Host smart-a840fa76-7969-4abc-8e46-6a9a2ce06e87
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164024966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.1164024966
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2482173366
Short name T480
Test name
Test status
Simulation time 2623751742 ps
CPU time 2.08 seconds
Started Apr 02 01:04:31 PM PDT 24
Finished Apr 02 01:04:35 PM PDT 24
Peak memory 201968 kb
Host smart-56a047b6-f5fa-4ed2-b414-966e97267dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482173366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.2482173366
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3413884976
Short name T496
Test name
Test status
Simulation time 2500471064 ps
CPU time 1.46 seconds
Started Apr 02 01:04:31 PM PDT 24
Finished Apr 02 01:04:35 PM PDT 24
Peak memory 201844 kb
Host smart-ed25f941-9410-4e02-8ed6-f8c772611a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413884976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.3413884976
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.2293181296
Short name T394
Test name
Test status
Simulation time 2177849817 ps
CPU time 1.99 seconds
Started Apr 02 01:04:27 PM PDT 24
Finished Apr 02 01:04:30 PM PDT 24
Peak memory 201864 kb
Host smart-4d13e323-39d6-478a-9ac0-6eccb1fc22c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293181296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.2293181296
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.4293621529
Short name T518
Test name
Test status
Simulation time 2531968726 ps
CPU time 2.19 seconds
Started Apr 02 01:04:31 PM PDT 24
Finished Apr 02 01:04:35 PM PDT 24
Peak memory 201948 kb
Host smart-37950071-4a8d-47dc-a7bc-c84b5c6f5686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293621529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.4293621529
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.979991784
Short name T547
Test name
Test status
Simulation time 2112551997 ps
CPU time 6.01 seconds
Started Apr 02 01:04:33 PM PDT 24
Finished Apr 02 01:04:39 PM PDT 24
Peak memory 201832 kb
Host smart-82a8665e-25b5-49f4-a3c4-89ba44aaa903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979991784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.979991784
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2180341565
Short name T129
Test name
Test status
Simulation time 53863137028 ps
CPU time 32.58 seconds
Started Apr 02 01:04:31 PM PDT 24
Finished Apr 02 01:05:06 PM PDT 24
Peak memory 218220 kb
Host smart-21288e50-6466-4385-a0d5-599d50db2c4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180341565 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2180341565
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2933970644
Short name T433
Test name
Test status
Simulation time 8767464876 ps
CPU time 4.66 seconds
Started Apr 02 01:04:30 PM PDT 24
Finished Apr 02 01:04:35 PM PDT 24
Peak memory 201928 kb
Host smart-00e264be-5280-4b08-9d51-4261a5d540a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933970644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2933970644
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.3600180107
Short name T564
Test name
Test status
Simulation time 2011817715 ps
CPU time 5.37 seconds
Started Apr 02 01:02:46 PM PDT 24
Finished Apr 02 01:02:51 PM PDT 24
Peak memory 202020 kb
Host smart-1a5e3da6-e6b1-41a8-b829-2436ff2ee581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600180107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.3600180107
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.124621101
Short name T366
Test name
Test status
Simulation time 3407683967 ps
CPU time 4.2 seconds
Started Apr 02 01:02:47 PM PDT 24
Finished Apr 02 01:02:52 PM PDT 24
Peak memory 202028 kb
Host smart-04634ef4-aa8a-4291-b4b7-07ba268555a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124621101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.124621101
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1641163654
Short name T189
Test name
Test status
Simulation time 129938286208 ps
CPU time 168.82 seconds
Started Apr 02 01:02:42 PM PDT 24
Finished Apr 02 01:05:31 PM PDT 24
Peak memory 202108 kb
Host smart-3d98ab88-38f2-4813-abc8-7736690424a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641163654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.1641163654
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.726915748
Short name T659
Test name
Test status
Simulation time 2292183691 ps
CPU time 1.08 seconds
Started Apr 02 01:02:38 PM PDT 24
Finished Apr 02 01:02:40 PM PDT 24
Peak memory 201864 kb
Host smart-57b96178-929d-4490-8e47-d9b966b8f356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726915748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.726915748
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3904202377
Short name T231
Test name
Test status
Simulation time 2537267367 ps
CPU time 2.43 seconds
Started Apr 02 01:02:50 PM PDT 24
Finished Apr 02 01:02:53 PM PDT 24
Peak memory 201940 kb
Host smart-1754846b-1df4-46dc-9d24-add40352f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904202377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3904202377
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.568030696
Short name T624
Test name
Test status
Simulation time 24829525697 ps
CPU time 67.61 seconds
Started Apr 02 01:02:47 PM PDT 24
Finished Apr 02 01:03:55 PM PDT 24
Peak memory 202080 kb
Host smart-355d39d8-b78b-4db2-8fa0-b398ac3870cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568030696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wit
h_pre_cond.568030696
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.4029358203
Short name T144
Test name
Test status
Simulation time 81188754558 ps
CPU time 57.25 seconds
Started Apr 02 01:02:43 PM PDT 24
Finished Apr 02 01:03:40 PM PDT 24
Peak memory 201912 kb
Host smart-2f7ca04e-88ef-470c-a335-bd9018584112
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029358203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.4029358203
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3271065718
Short name T565
Test name
Test status
Simulation time 3146377670 ps
CPU time 2.2 seconds
Started Apr 02 01:02:42 PM PDT 24
Finished Apr 02 01:02:45 PM PDT 24
Peak memory 201836 kb
Host smart-fd597c21-2d6c-4f8b-924a-5a8d0a90e106
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271065718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.3271065718
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.1911925809
Short name T660
Test name
Test status
Simulation time 2628454827 ps
CPU time 2.48 seconds
Started Apr 02 01:02:47 PM PDT 24
Finished Apr 02 01:02:50 PM PDT 24
Peak memory 201932 kb
Host smart-2559dc8a-a362-43ff-a321-9afa1463cc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911925809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.1911925809
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1747084766
Short name T374
Test name
Test status
Simulation time 2484606263 ps
CPU time 2.38 seconds
Started Apr 02 01:02:38 PM PDT 24
Finished Apr 02 01:02:40 PM PDT 24
Peak memory 201924 kb
Host smart-2f7848ee-17ce-4e5b-aae9-540cfc03bce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747084766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1747084766
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.323638550
Short name T481
Test name
Test status
Simulation time 2202527631 ps
CPU time 2 seconds
Started Apr 02 01:02:38 PM PDT 24
Finished Apr 02 01:02:40 PM PDT 24
Peak memory 201928 kb
Host smart-294a5e27-d227-45c3-a309-e44002927abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323638550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.323638550
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2959666332
Short name T396
Test name
Test status
Simulation time 2526872693 ps
CPU time 3.07 seconds
Started Apr 02 01:02:42 PM PDT 24
Finished Apr 02 01:02:45 PM PDT 24
Peak memory 201864 kb
Host smart-7bcd76bf-ffc1-4765-8cda-541ef205c391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959666332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2959666332
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.612530089
Short name T80
Test name
Test status
Simulation time 22009848220 ps
CPU time 61.63 seconds
Started Apr 02 01:02:53 PM PDT 24
Finished Apr 02 01:03:55 PM PDT 24
Peak memory 221816 kb
Host smart-f97944ea-fc42-4b1f-8ae7-c59cd09fae57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612530089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.612530089
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2247752428
Short name T207
Test name
Test status
Simulation time 2115653737 ps
CPU time 3.51 seconds
Started Apr 02 01:02:38 PM PDT 24
Finished Apr 02 01:02:42 PM PDT 24
Peak memory 201840 kb
Host smart-92d1459e-83e4-404a-8be6-455042f4d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247752428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2247752428
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.4258860294
Short name T348
Test name
Test status
Simulation time 3130727892701 ps
CPU time 143.49 seconds
Started Apr 02 01:02:48 PM PDT 24
Finished Apr 02 01:05:12 PM PDT 24
Peak memory 201876 kb
Host smart-4a754c5c-064e-4503-a7c8-7979e02e6c46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258860294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.4258860294
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2323666167
Short name T759
Test name
Test status
Simulation time 5606325554 ps
CPU time 3.18 seconds
Started Apr 02 01:02:42 PM PDT 24
Finished Apr 02 01:02:46 PM PDT 24
Peak memory 201980 kb
Host smart-9ad5b062-8e6e-436e-ab13-f4e54334ab3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323666167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2323666167
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.1781083564
Short name T563
Test name
Test status
Simulation time 2042101679 ps
CPU time 1.51 seconds
Started Apr 02 01:04:34 PM PDT 24
Finished Apr 02 01:04:36 PM PDT 24
Peak memory 201996 kb
Host smart-a4174617-6821-4eca-8eb9-6dc5473f843b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781083564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.1781083564
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.505042464
Short name T690
Test name
Test status
Simulation time 3230581960 ps
CPU time 2.82 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:04:43 PM PDT 24
Peak memory 201980 kb
Host smart-d2846342-9def-4c3d-971b-3c8b0ba02bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505042464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.505042464
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.889507203
Short name T252
Test name
Test status
Simulation time 94566375315 ps
CPU time 62.04 seconds
Started Apr 02 01:04:37 PM PDT 24
Finished Apr 02 01:05:42 PM PDT 24
Peak memory 202112 kb
Host smart-b6965c43-c600-4959-8dde-28288d5f544b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889507203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_combo_detect.889507203
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2426588998
Short name T317
Test name
Test status
Simulation time 59947107009 ps
CPU time 40.58 seconds
Started Apr 02 01:04:33 PM PDT 24
Finished Apr 02 01:05:15 PM PDT 24
Peak memory 202120 kb
Host smart-8584e301-714a-40a5-97c1-157e09057dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426588998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.2426588998
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3775483244
Short name T501
Test name
Test status
Simulation time 2599392366 ps
CPU time 3.9 seconds
Started Apr 02 01:04:34 PM PDT 24
Finished Apr 02 01:04:38 PM PDT 24
Peak memory 201972 kb
Host smart-7dff3436-fb87-4dc3-be0f-56a1009323db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775483244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.3775483244
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3266636816
Short name T10
Test name
Test status
Simulation time 3322343517 ps
CPU time 2.78 seconds
Started Apr 02 01:04:37 PM PDT 24
Finished Apr 02 01:04:43 PM PDT 24
Peak memory 202000 kb
Host smart-0be88d2a-da05-4a0b-8ac0-53efd9d1a215
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266636816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.3266636816
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.736443348
Short name T467
Test name
Test status
Simulation time 2614389646 ps
CPU time 7.03 seconds
Started Apr 02 01:04:37 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 201952 kb
Host smart-e2b109f3-e9c0-4060-94bc-5608239ff5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736443348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.736443348
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1817421729
Short name T450
Test name
Test status
Simulation time 2449333380 ps
CPU time 7.25 seconds
Started Apr 02 01:04:29 PM PDT 24
Finished Apr 02 01:04:37 PM PDT 24
Peak memory 201872 kb
Host smart-b28a0b88-ac1e-44a3-b1d6-25b921e8a781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817421729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1817421729
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.1860195520
Short name T596
Test name
Test status
Simulation time 2107652214 ps
CPU time 2.54 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:04:39 PM PDT 24
Peak memory 201868 kb
Host smart-dc8baa2c-903c-494e-9e29-19364e8b406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860195520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.1860195520
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.4191368013
Short name T449
Test name
Test status
Simulation time 2136488091 ps
CPU time 2.11 seconds
Started Apr 02 01:04:31 PM PDT 24
Finished Apr 02 01:04:35 PM PDT 24
Peak memory 201832 kb
Host smart-a94477ed-d7f4-4378-b92a-5cc8be64dd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191368013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.4191368013
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.1660677888
Short name T302
Test name
Test status
Simulation time 130335382210 ps
CPU time 55.96 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:05:31 PM PDT 24
Peak memory 202116 kb
Host smart-f0ba41b7-928a-4c9a-8b1a-3ad51116af23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660677888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.1660677888
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.241966728
Short name T695
Test name
Test status
Simulation time 51334753825 ps
CPU time 130.65 seconds
Started Apr 02 01:04:36 PM PDT 24
Finished Apr 02 01:06:50 PM PDT 24
Peak memory 210616 kb
Host smart-014e64ae-ae60-4d04-a342-8b9846f93510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241966728 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.241966728
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1048343023
Short name T622
Test name
Test status
Simulation time 6202289858 ps
CPU time 2.18 seconds
Started Apr 02 01:04:34 PM PDT 24
Finished Apr 02 01:04:37 PM PDT 24
Peak memory 201960 kb
Host smart-718a01cb-5ace-4a9b-8f85-70606c5c8627
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048343023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.1048343023
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.2184480463
Short name T389
Test name
Test status
Simulation time 2019257577 ps
CPU time 3.5 seconds
Started Apr 02 01:04:36 PM PDT 24
Finished Apr 02 01:04:43 PM PDT 24
Peak memory 202044 kb
Host smart-8b970686-3527-457e-a26a-44f9d61d77a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184480463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.2184480463
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3008519305
Short name T775
Test name
Test status
Simulation time 3627758864 ps
CPU time 10.04 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 201992 kb
Host smart-6e13ea66-ba7c-41a4-8879-a09488e1bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008519305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3
008519305
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.4002903000
Short name T255
Test name
Test status
Simulation time 126243194884 ps
CPU time 320.2 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:09:57 PM PDT 24
Peak memory 202096 kb
Host smart-c7e05f51-e518-4de6-8b54-4bfc289044bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002903000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.4002903000
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.755561347
Short name T605
Test name
Test status
Simulation time 42466000675 ps
CPU time 29.78 seconds
Started Apr 02 01:04:36 PM PDT 24
Finished Apr 02 01:05:10 PM PDT 24
Peak memory 202192 kb
Host smart-8b3c42ac-57c4-4aaf-bf56-2c263239cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755561347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_wi
th_pre_cond.755561347
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1065878469
Short name T482
Test name
Test status
Simulation time 3945019538 ps
CPU time 11.03 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:04:48 PM PDT 24
Peak memory 201932 kb
Host smart-a573557a-e32c-4259-91fb-2fc52aab7c1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065878469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.1065878469
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.3734208860
Short name T611
Test name
Test status
Simulation time 2909866200 ps
CPU time 1.34 seconds
Started Apr 02 01:04:36 PM PDT 24
Finished Apr 02 01:04:41 PM PDT 24
Peak memory 201964 kb
Host smart-d69a31e3-7555-4ede-bdca-f19d89736f20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734208860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.3734208860
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.526238007
Short name T512
Test name
Test status
Simulation time 2609805104 ps
CPU time 7.64 seconds
Started Apr 02 01:04:36 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 201980 kb
Host smart-69a17c43-55d1-40a9-816d-e2bac09035f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526238007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.526238007
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1180831967
Short name T25
Test name
Test status
Simulation time 2431036084 ps
CPU time 6.02 seconds
Started Apr 02 01:04:34 PM PDT 24
Finished Apr 02 01:04:40 PM PDT 24
Peak memory 201932 kb
Host smart-c306f786-f74b-4c44-8b10-42aead779cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180831967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1180831967
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.697084140
Short name T762
Test name
Test status
Simulation time 2185732480 ps
CPU time 1.88 seconds
Started Apr 02 01:04:34 PM PDT 24
Finished Apr 02 01:04:36 PM PDT 24
Peak memory 201916 kb
Host smart-28894107-70fd-41bc-a6a4-27bbfe8658a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697084140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.697084140
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.319109054
Short name T543
Test name
Test status
Simulation time 2519991434 ps
CPU time 2.39 seconds
Started Apr 02 01:04:36 PM PDT 24
Finished Apr 02 01:04:42 PM PDT 24
Peak memory 201952 kb
Host smart-c1da1585-b937-4a0e-a964-777048b1a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319109054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.319109054
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.2295151193
Short name T362
Test name
Test status
Simulation time 2122033842 ps
CPU time 3.44 seconds
Started Apr 02 01:04:36 PM PDT 24
Finished Apr 02 01:04:43 PM PDT 24
Peak memory 201884 kb
Host smart-5bd67e72-4a9e-4647-95ce-b407c01e7e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295151193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.2295151193
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.3226543903
Short name T99
Test name
Test status
Simulation time 9144986267 ps
CPU time 15.71 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:04:52 PM PDT 24
Peak memory 201860 kb
Host smart-96ca6e0c-134a-4b71-b887-28c9715d1fdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226543903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.3226543903
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.374331945
Short name T59
Test name
Test status
Simulation time 18239178629 ps
CPU time 46.69 seconds
Started Apr 02 01:04:38 PM PDT 24
Finished Apr 02 01:05:27 PM PDT 24
Peak memory 210476 kb
Host smart-1722ff59-e031-4d4a-a795-e2e856fe090e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374331945 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.374331945
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1883186550
Short name T767
Test name
Test status
Simulation time 3880051565 ps
CPU time 7.38 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:04:44 PM PDT 24
Peak memory 201928 kb
Host smart-06c57695-c1b4-4556-b6a1-c2938eabf455
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883186550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.1883186550
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.3558768559
Short name T554
Test name
Test status
Simulation time 2076585537 ps
CPU time 1.41 seconds
Started Apr 02 01:04:40 PM PDT 24
Finished Apr 02 01:04:42 PM PDT 24
Peak memory 201976 kb
Host smart-d906dcc9-140c-477c-87cb-072e92263116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558768559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.3558768559
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3652467496
Short name T615
Test name
Test status
Simulation time 3471344080 ps
CPU time 3.07 seconds
Started Apr 02 01:04:39 PM PDT 24
Finished Apr 02 01:04:43 PM PDT 24
Peak memory 201976 kb
Host smart-cbc2316a-150c-42f8-bee5-7eb25c28762e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652467496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.3
652467496
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.685171437
Short name T472
Test name
Test status
Simulation time 129319148576 ps
CPU time 171.56 seconds
Started Apr 02 01:04:41 PM PDT 24
Finished Apr 02 01:07:33 PM PDT 24
Peak memory 202176 kb
Host smart-8098f2ff-fbad-4197-8602-08cdeb5a0a91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685171437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_combo_detect.685171437
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2416577346
Short name T328
Test name
Test status
Simulation time 123002501504 ps
CPU time 319.82 seconds
Started Apr 02 01:04:46 PM PDT 24
Finished Apr 02 01:10:06 PM PDT 24
Peak memory 202180 kb
Host smart-10b16162-8fb8-4b1c-b1a4-afb07d4235a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416577346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.2416577346
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3912553600
Short name T737
Test name
Test status
Simulation time 4697456631 ps
CPU time 8.02 seconds
Started Apr 02 01:04:39 PM PDT 24
Finished Apr 02 01:04:48 PM PDT 24
Peak memory 201868 kb
Host smart-88b3db12-865f-4e86-aaf5-296b66445a49
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912553600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.3912553600
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1591888741
Short name T149
Test name
Test status
Simulation time 5293690483 ps
CPU time 4.57 seconds
Started Apr 02 01:04:47 PM PDT 24
Finished Apr 02 01:04:51 PM PDT 24
Peak memory 201952 kb
Host smart-a27e9632-6509-45df-8071-840b974aa261
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591888741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.1591888741
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1769541597
Short name T355
Test name
Test status
Simulation time 2617624660 ps
CPU time 4.25 seconds
Started Apr 02 01:04:41 PM PDT 24
Finished Apr 02 01:04:45 PM PDT 24
Peak memory 202172 kb
Host smart-ca9a30f0-9fe4-4166-8fcd-51a40c1a286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769541597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.1769541597
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1852670035
Short name T68
Test name
Test status
Simulation time 2480332071 ps
CPU time 3.77 seconds
Started Apr 02 01:04:39 PM PDT 24
Finished Apr 02 01:04:44 PM PDT 24
Peak memory 201916 kb
Host smart-227bc523-4f68-4f9b-88a1-ae3c7607fa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852670035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1852670035
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1743741344
Short name T682
Test name
Test status
Simulation time 2241258925 ps
CPU time 2.42 seconds
Started Apr 02 01:04:42 PM PDT 24
Finished Apr 02 01:04:46 PM PDT 24
Peak memory 201924 kb
Host smart-1983fd9e-489a-4f9a-8dc6-6858754d7796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743741344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1743741344
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.3499646930
Short name T271
Test name
Test status
Simulation time 2541443525 ps
CPU time 1.86 seconds
Started Apr 02 01:04:39 PM PDT 24
Finished Apr 02 01:04:42 PM PDT 24
Peak memory 201928 kb
Host smart-83cf77bc-1f4d-40e3-8876-a7efc0f25ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499646930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.3499646930
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.652110939
Short name T369
Test name
Test status
Simulation time 2128372089 ps
CPU time 2.01 seconds
Started Apr 02 01:04:35 PM PDT 24
Finished Apr 02 01:04:39 PM PDT 24
Peak memory 201848 kb
Host smart-450cda95-db1f-4641-a928-63f57bb176e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652110939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.652110939
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.1625876564
Short name T196
Test name
Test status
Simulation time 6517158415 ps
CPU time 16.45 seconds
Started Apr 02 01:04:38 PM PDT 24
Finished Apr 02 01:04:57 PM PDT 24
Peak memory 201924 kb
Host smart-04711a69-515c-4551-b808-b7734846610d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625876564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.1625876564
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2277461250
Short name T175
Test name
Test status
Simulation time 345099056668 ps
CPU time 277.35 seconds
Started Apr 02 01:04:38 PM PDT 24
Finished Apr 02 01:09:18 PM PDT 24
Peak memory 218708 kb
Host smart-92426819-8547-47a5-ade4-1348d3a8bdd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277461250 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.2277461250
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1553655488
Short name T125
Test name
Test status
Simulation time 45318957685 ps
CPU time 5.8 seconds
Started Apr 02 01:04:39 PM PDT 24
Finished Apr 02 01:04:46 PM PDT 24
Peak memory 201948 kb
Host smart-0ab5eba8-b355-4eea-bda5-3afcb41a67d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553655488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.1553655488
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.1174159200
Short name T402
Test name
Test status
Simulation time 2037686390 ps
CPU time 2.06 seconds
Started Apr 02 01:04:43 PM PDT 24
Finished Apr 02 01:04:46 PM PDT 24
Peak memory 201916 kb
Host smart-24e5d955-9834-4e34-9948-c0084b2b58f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174159200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.1174159200
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2602492926
Short name T735
Test name
Test status
Simulation time 3106168846 ps
CPU time 2.81 seconds
Started Apr 02 01:04:43 PM PDT 24
Finished Apr 02 01:04:46 PM PDT 24
Peak memory 201856 kb
Host smart-dd06a235-83a6-4730-9d74-7a2cd3c94e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602492926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.2
602492926
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3008368443
Short name T324
Test name
Test status
Simulation time 165174378857 ps
CPU time 219.74 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:08:29 PM PDT 24
Peak memory 202172 kb
Host smart-66529dc6-c7fb-45fe-a5ca-cbd16f77d1bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008368443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.3008368443
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3502226708
Short name T769
Test name
Test status
Simulation time 42138465593 ps
CPU time 110.18 seconds
Started Apr 02 01:04:45 PM PDT 24
Finished Apr 02 01:06:36 PM PDT 24
Peak memory 202036 kb
Host smart-8bf3e127-cae0-459b-ac9e-c4990b68c6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502226708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.3502226708
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2207902130
Short name T558
Test name
Test status
Simulation time 4986109859 ps
CPU time 4.09 seconds
Started Apr 02 01:04:41 PM PDT 24
Finished Apr 02 01:04:46 PM PDT 24
Peak memory 201892 kb
Host smart-5946c630-bff2-454c-a727-41d8237c9946
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207902130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ec_pwr_on_rst.2207902130
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3161860710
Short name T35
Test name
Test status
Simulation time 4565095810 ps
CPU time 3.86 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:04:54 PM PDT 24
Peak memory 201940 kb
Host smart-2a03cc9a-8eed-4636-a260-5a7d167cd801
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161860710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3161860710
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1366438534
Short name T504
Test name
Test status
Simulation time 2608466523 ps
CPU time 7.28 seconds
Started Apr 02 01:04:48 PM PDT 24
Finished Apr 02 01:04:55 PM PDT 24
Peak memory 201940 kb
Host smart-5ede9491-47b9-40b7-a6bf-c47ccd42b187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366438534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.1366438534
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.4087597391
Short name T444
Test name
Test status
Simulation time 2492399325 ps
CPU time 7.08 seconds
Started Apr 02 01:04:38 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 201932 kb
Host smart-d3c7aa34-2cd7-434a-b50f-355673b4b4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087597391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.4087597391
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.1600800839
Short name T617
Test name
Test status
Simulation time 2114950241 ps
CPU time 6.62 seconds
Started Apr 02 01:04:38 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 201852 kb
Host smart-5acc49f4-d81f-4e0d-9edd-04525689791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600800839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.1600800839
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.1676372938
Short name T771
Test name
Test status
Simulation time 2533142281 ps
CPU time 2.62 seconds
Started Apr 02 01:04:39 PM PDT 24
Finished Apr 02 01:04:43 PM PDT 24
Peak memory 201972 kb
Host smart-a946476d-5668-44f0-9ca3-d36248099ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676372938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1676372938
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.3265927518
Short name T453
Test name
Test status
Simulation time 2118860333 ps
CPU time 3.47 seconds
Started Apr 02 01:04:38 PM PDT 24
Finished Apr 02 01:04:44 PM PDT 24
Peak memory 201840 kb
Host smart-57598d11-5f40-4a76-b662-c6d5d7dadba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265927518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.3265927518
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.2522268531
Short name T347
Test name
Test status
Simulation time 15950704127 ps
CPU time 45.58 seconds
Started Apr 02 01:04:42 PM PDT 24
Finished Apr 02 01:05:29 PM PDT 24
Peak memory 201940 kb
Host smart-3b19118e-a56b-40e9-b5c3-208e1210ef26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522268531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.2522268531
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.974637620
Short name T4
Test name
Test status
Simulation time 46762400103 ps
CPU time 118.4 seconds
Started Apr 02 01:04:42 PM PDT 24
Finished Apr 02 01:06:42 PM PDT 24
Peak memory 210492 kb
Host smart-8be5d28e-d36b-4436-ac53-278c7d802c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974637620 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.974637620
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2997144184
Short name T376
Test name
Test status
Simulation time 2779205098 ps
CPU time 3.39 seconds
Started Apr 02 01:04:43 PM PDT 24
Finished Apr 02 01:04:47 PM PDT 24
Peak memory 201848 kb
Host smart-93b6cf38-d007-4041-a62b-a8b4c34440c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997144184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.2997144184
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.3525066661
Short name T637
Test name
Test status
Simulation time 2012116617 ps
CPU time 5.62 seconds
Started Apr 02 01:05:01 PM PDT 24
Finished Apr 02 01:05:07 PM PDT 24
Peak memory 202004 kb
Host smart-3e3fd6d6-d875-4269-9dfe-747c7e16db77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525066661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_te
st.3525066661
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3075995828
Short name T536
Test name
Test status
Simulation time 3576597312 ps
CPU time 10.29 seconds
Started Apr 02 01:04:41 PM PDT 24
Finished Apr 02 01:04:52 PM PDT 24
Peak memory 202012 kb
Host smart-bb123710-aa9b-4211-a53f-f0f118f0e682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075995828 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.3
075995828
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.841476974
Short name T778
Test name
Test status
Simulation time 42127219081 ps
CPU time 118.71 seconds
Started Apr 02 01:04:41 PM PDT 24
Finished Apr 02 01:06:40 PM PDT 24
Peak memory 202144 kb
Host smart-6b3e9028-f530-4efc-9d0a-d94cc9180bf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841476974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_combo_detect.841476974
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.3570137346
Short name T130
Test name
Test status
Simulation time 3970619025 ps
CPU time 10.81 seconds
Started Apr 02 01:04:48 PM PDT 24
Finished Apr 02 01:04:59 PM PDT 24
Peak memory 201932 kb
Host smart-e8848ca3-7fd5-46d9-a35b-ee6fb38fc325
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570137346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ec_pwr_on_rst.3570137346
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1095610688
Short name T742
Test name
Test status
Simulation time 3645675787 ps
CPU time 5.45 seconds
Started Apr 02 01:04:47 PM PDT 24
Finished Apr 02 01:04:53 PM PDT 24
Peak memory 201948 kb
Host smart-9835d05f-ddd8-4073-b4ea-34950fdaa866
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095610688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1095610688
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3653632445
Short name T19
Test name
Test status
Simulation time 2609992968 ps
CPU time 7.87 seconds
Started Apr 02 01:04:46 PM PDT 24
Finished Apr 02 01:04:54 PM PDT 24
Peak memory 201924 kb
Host smart-95b2df01-385a-4e3a-b14d-0855a2dafab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653632445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.3653632445
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1422868898
Short name T552
Test name
Test status
Simulation time 2465436745 ps
CPU time 7.03 seconds
Started Apr 02 01:04:49 PM PDT 24
Finished Apr 02 01:04:57 PM PDT 24
Peak memory 201984 kb
Host smart-3d7c4f71-6a97-437d-bd45-7155c511a4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422868898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.1422868898
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.3131254106
Short name T160
Test name
Test status
Simulation time 2114195333 ps
CPU time 6.53 seconds
Started Apr 02 01:04:45 PM PDT 24
Finished Apr 02 01:04:52 PM PDT 24
Peak memory 201732 kb
Host smart-2a9dc139-8fb8-4dfe-86b7-65ab2ba10f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131254106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.3131254106
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.1295440898
Short name T143
Test name
Test status
Simulation time 2519048362 ps
CPU time 4.13 seconds
Started Apr 02 01:04:41 PM PDT 24
Finished Apr 02 01:04:46 PM PDT 24
Peak memory 201872 kb
Host smart-79ad6483-7e6f-4783-95f4-ed2d20369b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295440898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.1295440898
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.601873803
Short name T515
Test name
Test status
Simulation time 2111574703 ps
CPU time 6.08 seconds
Started Apr 02 01:04:42 PM PDT 24
Finished Apr 02 01:04:50 PM PDT 24
Peak memory 201836 kb
Host smart-72654341-0409-4ade-9fcb-dea044fc5af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601873803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.601873803
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.3879573759
Short name T183
Test name
Test status
Simulation time 13836174749 ps
CPU time 36.37 seconds
Started Apr 02 01:05:01 PM PDT 24
Finished Apr 02 01:05:38 PM PDT 24
Peak memory 201896 kb
Host smart-d1b95c74-1629-4157-ab93-47c1e3e5945e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879573759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.3879573759
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.398196090
Short name T137
Test name
Test status
Simulation time 21047776207 ps
CPU time 24.52 seconds
Started Apr 02 01:04:48 PM PDT 24
Finished Apr 02 01:05:13 PM PDT 24
Peak memory 210444 kb
Host smart-8d1c3b6c-4d82-4dc5-8d67-90b134d2671e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398196090 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.398196090
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2337716767
Short name T606
Test name
Test status
Simulation time 6948826624 ps
CPU time 2.38 seconds
Started Apr 02 01:04:42 PM PDT 24
Finished Apr 02 01:04:46 PM PDT 24
Peak memory 201888 kb
Host smart-94b2440e-fef3-4bfe-8984-098024eb3fa1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337716767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2337716767
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.2830619130
Short name T717
Test name
Test status
Simulation time 2011171190 ps
CPU time 6.47 seconds
Started Apr 02 01:04:51 PM PDT 24
Finished Apr 02 01:04:59 PM PDT 24
Peak memory 202024 kb
Host smart-ebd328d4-792f-4db4-b2ca-03c77c2dc32c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830619130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.2830619130
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1568104219
Short name T465
Test name
Test status
Simulation time 79767369548 ps
CPU time 218.31 seconds
Started Apr 02 01:04:49 PM PDT 24
Finished Apr 02 01:08:28 PM PDT 24
Peak memory 202060 kb
Host smart-e8a19c73-9642-4f08-a197-670a4fd2455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568104219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.1
568104219
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2275011725
Short name T685
Test name
Test status
Simulation time 164702549523 ps
CPU time 317.25 seconds
Started Apr 02 01:05:01 PM PDT 24
Finished Apr 02 01:10:19 PM PDT 24
Peak memory 201880 kb
Host smart-68949ff8-51b9-4f69-b5d8-33fa5219b8c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275011725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_combo_detect.2275011725
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1766435141
Short name T437
Test name
Test status
Simulation time 24332512471 ps
CPU time 63.18 seconds
Started Apr 02 01:04:47 PM PDT 24
Finished Apr 02 01:05:50 PM PDT 24
Peak memory 202044 kb
Host smart-e68b539b-329b-440c-aed6-912d09e9727c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766435141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.1766435141
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1936596860
Short name T511
Test name
Test status
Simulation time 2675248436 ps
CPU time 2.3 seconds
Started Apr 02 01:04:46 PM PDT 24
Finished Apr 02 01:04:48 PM PDT 24
Peak memory 201812 kb
Host smart-79938864-41ad-49df-9f30-3b4d8a9fce8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936596860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.1936596860
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.4226580969
Short name T668
Test name
Test status
Simulation time 3843271364 ps
CPU time 5.74 seconds
Started Apr 02 01:04:47 PM PDT 24
Finished Apr 02 01:04:53 PM PDT 24
Peak memory 201964 kb
Host smart-bc127ac2-b49a-4cd2-aaee-e1315ba0e735
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226580969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_edge_detect.4226580969
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.533761965
Short name T628
Test name
Test status
Simulation time 2618231383 ps
CPU time 4.28 seconds
Started Apr 02 01:05:01 PM PDT 24
Finished Apr 02 01:05:06 PM PDT 24
Peak memory 201724 kb
Host smart-fa89a0c1-dea1-4b0e-9c1a-7205f7f1ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533761965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.533761965
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.242270387
Short name T553
Test name
Test status
Simulation time 2480919402 ps
CPU time 2.96 seconds
Started Apr 02 01:05:01 PM PDT 24
Finished Apr 02 01:05:04 PM PDT 24
Peak memory 201936 kb
Host smart-59aae54a-ed5a-4a3f-91c2-8570a5d78c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242270387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.242270387
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1517449041
Short name T441
Test name
Test status
Simulation time 2199030067 ps
CPU time 5.24 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:04:57 PM PDT 24
Peak memory 201916 kb
Host smart-aab25b1d-a4bf-476f-9686-cf372d1e8c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517449041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1517449041
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1842859653
Short name T53
Test name
Test status
Simulation time 2533590176 ps
CPU time 2.47 seconds
Started Apr 02 01:05:01 PM PDT 24
Finished Apr 02 01:05:04 PM PDT 24
Peak memory 201960 kb
Host smart-695d7def-69c6-41f4-9f50-a4d5465d80bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842859653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1842859653
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.2687969587
Short name T786
Test name
Test status
Simulation time 2119910908 ps
CPU time 3.27 seconds
Started Apr 02 01:04:49 PM PDT 24
Finished Apr 02 01:04:53 PM PDT 24
Peak memory 201872 kb
Host smart-ee984e3c-07ae-4611-9f4a-ef5841942be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687969587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2687969587
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.2846396345
Short name T64
Test name
Test status
Simulation time 12340109645 ps
CPU time 26.27 seconds
Started Apr 02 01:04:51 PM PDT 24
Finished Apr 02 01:05:19 PM PDT 24
Peak memory 201948 kb
Host smart-2a3cf1af-bea1-46ab-9227-5b4895c25970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846396345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.2846396345
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.4098865418
Short name T265
Test name
Test status
Simulation time 16229497945 ps
CPU time 20.15 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:05:10 PM PDT 24
Peak memory 211472 kb
Host smart-a3de49ec-b571-4bac-8598-281fa0e34f26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098865418 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.4098865418
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3382782206
Short name T781
Test name
Test status
Simulation time 8066801417 ps
CPU time 5.88 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:04:56 PM PDT 24
Peak memory 201940 kb
Host smart-89716b95-09d7-4aae-8421-18d01f70a61c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382782206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.3382782206
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.780345386
Short name T670
Test name
Test status
Simulation time 2018098506 ps
CPU time 3.37 seconds
Started Apr 02 01:04:52 PM PDT 24
Finished Apr 02 01:04:56 PM PDT 24
Peak memory 202040 kb
Host smart-f4057401-c5d3-4745-9abe-f3406551d840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780345386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_tes
t.780345386
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1236445605
Short name T567
Test name
Test status
Simulation time 3670838976 ps
CPU time 1.34 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:04:51 PM PDT 24
Peak memory 202000 kb
Host smart-d708ec67-0030-4ae1-b126-bbff8124849b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236445605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.1
236445605
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.566168829
Short name T528
Test name
Test status
Simulation time 2723409074 ps
CPU time 2.3 seconds
Started Apr 02 01:04:52 PM PDT 24
Finished Apr 02 01:04:55 PM PDT 24
Peak memory 201932 kb
Host smart-056d4fdf-fa14-434f-a3e0-701b11383170
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566168829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ec_pwr_on_rst.566168829
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2827536983
Short name T38
Test name
Test status
Simulation time 4336016029 ps
CPU time 3.82 seconds
Started Apr 02 01:04:51 PM PDT 24
Finished Apr 02 01:04:56 PM PDT 24
Peak memory 201948 kb
Host smart-9852c449-6432-4597-a912-2e17a57d16e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827536983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.2827536983
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2108689420
Short name T361
Test name
Test status
Simulation time 2694730181 ps
CPU time 1.11 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:04:53 PM PDT 24
Peak memory 201880 kb
Host smart-237f995a-88f0-4263-b440-92963587b88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108689420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.2108689420
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3546700475
Short name T785
Test name
Test status
Simulation time 2454075576 ps
CPU time 6.65 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:04:57 PM PDT 24
Peak memory 201956 kb
Host smart-2664539a-b7d8-4216-b80c-2fd31499fd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546700475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3546700475
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1497389080
Short name T629
Test name
Test status
Simulation time 2148185335 ps
CPU time 1.97 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:04:54 PM PDT 24
Peak memory 201800 kb
Host smart-01d73925-0ff6-4077-98e6-9b94f25d02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497389080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1497389080
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.1745619535
Short name T386
Test name
Test status
Simulation time 2595466311 ps
CPU time 1.27 seconds
Started Apr 02 01:04:53 PM PDT 24
Finished Apr 02 01:04:56 PM PDT 24
Peak memory 201936 kb
Host smart-f0de224e-f24b-4266-b433-74822ddf6b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745619535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.1745619535
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.3338709294
Short name T354
Test name
Test status
Simulation time 2108497147 ps
CPU time 6.11 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:04:58 PM PDT 24
Peak memory 201844 kb
Host smart-f87efdc4-90c7-42e9-83c2-42e6ebb2fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338709294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.3338709294
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.3104426944
Short name T671
Test name
Test status
Simulation time 11583314198 ps
CPU time 6.42 seconds
Started Apr 02 01:04:50 PM PDT 24
Finished Apr 02 01:04:56 PM PDT 24
Peak memory 202080 kb
Host smart-63b4cc97-4d14-49c1-a156-0f2d5f7de56e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104426944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.3104426944
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2713107545
Short name T276
Test name
Test status
Simulation time 106983162782 ps
CPU time 58.14 seconds
Started Apr 02 01:04:51 PM PDT 24
Finished Apr 02 01:05:50 PM PDT 24
Peak memory 210532 kb
Host smart-b26f7d7e-3527-4182-9c7e-21349e08ba11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713107545 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2713107545
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.3337269631
Short name T753
Test name
Test status
Simulation time 2044672650 ps
CPU time 1.74 seconds
Started Apr 02 01:05:04 PM PDT 24
Finished Apr 02 01:05:06 PM PDT 24
Peak memory 201964 kb
Host smart-306be675-8151-4127-afeb-0f7c65291465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337269631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.3337269631
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.618086857
Short name T651
Test name
Test status
Simulation time 227736913053 ps
CPU time 568.22 seconds
Started Apr 02 01:04:59 PM PDT 24
Finished Apr 02 01:14:27 PM PDT 24
Peak memory 201980 kb
Host smart-b81cff4e-113e-4bb5-95df-929c5ff2e566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618086857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.618086857
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3960997520
Short name T263
Test name
Test status
Simulation time 113378447658 ps
CPU time 150.23 seconds
Started Apr 02 01:04:59 PM PDT 24
Finished Apr 02 01:07:30 PM PDT 24
Peak memory 202108 kb
Host smart-698cdab4-174d-48bb-a904-e2768dc31cdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960997520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.3960997520
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3649397219
Short name T456
Test name
Test status
Simulation time 4584129719 ps
CPU time 13.57 seconds
Started Apr 02 01:05:01 PM PDT 24
Finished Apr 02 01:05:15 PM PDT 24
Peak memory 201816 kb
Host smart-410f00ef-f174-471b-9516-9b2be4a65e8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649397219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.3649397219
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3808145552
Short name T749
Test name
Test status
Simulation time 4888034663 ps
CPU time 11.28 seconds
Started Apr 02 01:04:59 PM PDT 24
Finished Apr 02 01:05:11 PM PDT 24
Peak memory 201928 kb
Host smart-cf5041f5-0e42-4b95-9bd9-804d2892d562
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808145552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.3808145552
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3862170733
Short name T534
Test name
Test status
Simulation time 2621586958 ps
CPU time 2.74 seconds
Started Apr 02 01:05:00 PM PDT 24
Finished Apr 02 01:05:03 PM PDT 24
Peak memory 201904 kb
Host smart-fb68e312-dfd4-407e-953c-8b02beb1eec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862170733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.3862170733
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.1958493212
Short name T405
Test name
Test status
Simulation time 2448956659 ps
CPU time 6.86 seconds
Started Apr 02 01:04:59 PM PDT 24
Finished Apr 02 01:05:06 PM PDT 24
Peak memory 201928 kb
Host smart-64bb14d7-b9fc-4bb9-beb3-f67f2e7ad428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958493212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.1958493212
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.3623812427
Short name T218
Test name
Test status
Simulation time 2060715394 ps
CPU time 3.21 seconds
Started Apr 02 01:04:59 PM PDT 24
Finished Apr 02 01:05:03 PM PDT 24
Peak memory 201836 kb
Host smart-d0640d61-daf4-460f-927d-b836cb6377a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623812427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3623812427
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.4267609333
Short name T666
Test name
Test status
Simulation time 2530727140 ps
CPU time 2.49 seconds
Started Apr 02 01:05:00 PM PDT 24
Finished Apr 02 01:05:02 PM PDT 24
Peak memory 201932 kb
Host smart-409754e0-0391-4f28-a8b4-de2f560965cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267609333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.4267609333
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.120393618
Short name T760
Test name
Test status
Simulation time 2115409077 ps
CPU time 3.4 seconds
Started Apr 02 01:05:04 PM PDT 24
Finished Apr 02 01:05:07 PM PDT 24
Peak memory 201868 kb
Host smart-3611e390-9db7-4bbe-9f1e-65d0f9f312c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120393618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.120393618
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.2065676846
Short name T301
Test name
Test status
Simulation time 412066243995 ps
CPU time 495.64 seconds
Started Apr 02 01:05:04 PM PDT 24
Finished Apr 02 01:13:21 PM PDT 24
Peak memory 202136 kb
Host smart-50d8499a-79b0-4c37-bf36-1d57bef94451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065676846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.2065676846
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2855171586
Short name T595
Test name
Test status
Simulation time 32168039464 ps
CPU time 86.68 seconds
Started Apr 02 01:05:00 PM PDT 24
Finished Apr 02 01:06:27 PM PDT 24
Peak memory 212136 kb
Host smart-f96270db-8e63-4591-b857-94478905efa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855171586 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2855171586
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2922817735
Short name T635
Test name
Test status
Simulation time 3796356576 ps
CPU time 1.96 seconds
Started Apr 02 01:05:06 PM PDT 24
Finished Apr 02 01:05:08 PM PDT 24
Peak memory 201932 kb
Host smart-38d566eb-31ca-42fa-a46f-763238ea2e16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922817735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.2922817735
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3320505703
Short name T720
Test name
Test status
Simulation time 2042433300 ps
CPU time 1.86 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:08 PM PDT 24
Peak memory 201960 kb
Host smart-4200dcbd-96b6-4cf3-af19-4d2d8051535e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320505703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3320505703
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.33151082
Short name T724
Test name
Test status
Simulation time 3493576084 ps
CPU time 3.25 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:09 PM PDT 24
Peak memory 201916 kb
Host smart-9d41409e-059d-4a7d-af78-b88108cacce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33151082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.33151082
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.1641099857
Short name T330
Test name
Test status
Simulation time 144066966275 ps
CPU time 376.54 seconds
Started Apr 02 01:05:11 PM PDT 24
Finished Apr 02 01:11:27 PM PDT 24
Peak memory 202164 kb
Host smart-d0567fcd-dac9-4d69-92e1-8b7c0a0b5287
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641099857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_combo_detect.1641099857
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.882207327
Short name T478
Test name
Test status
Simulation time 3441482219 ps
CPU time 9.61 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:15 PM PDT 24
Peak memory 201864 kb
Host smart-806036d9-e627-4c1f-b53b-854af0226a72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882207327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.882207327
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3500734867
Short name T649
Test name
Test status
Simulation time 5237006877 ps
CPU time 11.08 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:17 PM PDT 24
Peak memory 201884 kb
Host smart-64d68ecf-2ef4-423d-b586-dc9c376fe4cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500734867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.3500734867
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1682447627
Short name T118
Test name
Test status
Simulation time 2679263576 ps
CPU time 1.44 seconds
Started Apr 02 01:05:01 PM PDT 24
Finished Apr 02 01:05:03 PM PDT 24
Peak memory 201952 kb
Host smart-035a1025-2956-45dd-b871-392e9175b6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682447627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1682447627
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3614063653
Short name T592
Test name
Test status
Simulation time 2462120776 ps
CPU time 8.4 seconds
Started Apr 02 01:05:07 PM PDT 24
Finished Apr 02 01:05:15 PM PDT 24
Peak memory 201936 kb
Host smart-730bcb9f-4930-4b63-80d9-fc7b6fdb6280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614063653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3614063653
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3630591467
Short name T457
Test name
Test status
Simulation time 2155281752 ps
CPU time 2.05 seconds
Started Apr 02 01:05:04 PM PDT 24
Finished Apr 02 01:05:08 PM PDT 24
Peak memory 201896 kb
Host smart-35301cf0-65a2-43c9-8917-168f7463dc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630591467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3630591467
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1530496618
Short name T499
Test name
Test status
Simulation time 2513638347 ps
CPU time 3.86 seconds
Started Apr 02 01:04:59 PM PDT 24
Finished Apr 02 01:05:03 PM PDT 24
Peak memory 201796 kb
Host smart-22397c8c-a755-434b-8ba1-43b7a3d2ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530496618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1530496618
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.1058287851
Short name T751
Test name
Test status
Simulation time 2126759852 ps
CPU time 1.83 seconds
Started Apr 02 01:05:00 PM PDT 24
Finished Apr 02 01:05:02 PM PDT 24
Peak memory 201856 kb
Host smart-6696c7a8-e31f-4655-8a40-8c4109436e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058287851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1058287851
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.567790840
Short name T105
Test name
Test status
Simulation time 874948641359 ps
CPU time 211.74 seconds
Started Apr 02 01:05:06 PM PDT 24
Finished Apr 02 01:08:39 PM PDT 24
Peak memory 201900 kb
Host smart-0e470d21-d7a2-4fe2-ae5f-7ec7e537ceed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567790840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st
ress_all.567790840
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1078070293
Short name T505
Test name
Test status
Simulation time 5865068230 ps
CPU time 2.23 seconds
Started Apr 02 01:05:04 PM PDT 24
Finished Apr 02 01:05:08 PM PDT 24
Peak memory 201848 kb
Host smart-24e0291a-eac2-4e9f-b3d9-f8b7fa084b20
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078070293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.1078070293
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.330388907
Short name T16
Test name
Test status
Simulation time 2040509551 ps
CPU time 2.02 seconds
Started Apr 02 01:05:07 PM PDT 24
Finished Apr 02 01:05:09 PM PDT 24
Peak memory 202020 kb
Host smart-7c2eb01c-c472-4b2b-86a0-588e216b19a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330388907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_tes
t.330388907
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.420780320
Short name T780
Test name
Test status
Simulation time 3236219112 ps
CPU time 9.54 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:15 PM PDT 24
Peak memory 201944 kb
Host smart-b9cfbd20-cc5c-4aba-bb49-f85bc0fd33fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420780320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.420780320
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.4251244810
Short name T45
Test name
Test status
Simulation time 161477728293 ps
CPU time 404.79 seconds
Started Apr 02 01:05:02 PM PDT 24
Finished Apr 02 01:11:47 PM PDT 24
Peak memory 202056 kb
Host smart-20e4dd98-1e9a-4808-9ca3-00cf822ddd4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251244810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.4251244810
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1010616363
Short name T733
Test name
Test status
Simulation time 69022695304 ps
CPU time 22.42 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:28 PM PDT 24
Peak memory 202120 kb
Host smart-cbf38399-de32-424d-9470-a94332f13368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010616363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1010616363
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1111904988
Short name T646
Test name
Test status
Simulation time 3641541152 ps
CPU time 9.66 seconds
Started Apr 02 01:05:06 PM PDT 24
Finished Apr 02 01:05:17 PM PDT 24
Peak memory 201948 kb
Host smart-e7b06bb6-63a5-4d06-ba2f-f5d0f10fa90d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111904988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.1111904988
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.3889426778
Short name T223
Test name
Test status
Simulation time 3218981363 ps
CPU time 8.19 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:14 PM PDT 24
Peak memory 201920 kb
Host smart-88dc8d78-3246-4921-8ce2-a391ef6d0174
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889426778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.3889426778
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1517788002
Short name T763
Test name
Test status
Simulation time 2626163001 ps
CPU time 2.29 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:08 PM PDT 24
Peak memory 201888 kb
Host smart-35152638-7817-4623-9282-2c0aa7606a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517788002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1517788002
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.634047485
Short name T468
Test name
Test status
Simulation time 2458269527 ps
CPU time 2.21 seconds
Started Apr 02 01:05:03 PM PDT 24
Finished Apr 02 01:05:05 PM PDT 24
Peak memory 201920 kb
Host smart-d32bbdb3-5a51-4529-a4f8-d68008b4547e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634047485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.634047485
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2706717943
Short name T208
Test name
Test status
Simulation time 2083646376 ps
CPU time 6 seconds
Started Apr 02 01:05:02 PM PDT 24
Finished Apr 02 01:05:08 PM PDT 24
Peak memory 201864 kb
Host smart-a3e153ed-988e-4b4f-997b-a6620d4c48b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706717943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2706717943
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2722147977
Short name T618
Test name
Test status
Simulation time 2542290924 ps
CPU time 2.01 seconds
Started Apr 02 01:05:04 PM PDT 24
Finished Apr 02 01:05:06 PM PDT 24
Peak memory 201912 kb
Host smart-8cbc1643-a447-44fd-b194-f32767526074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722147977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.2722147977
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.3706152202
Short name T586
Test name
Test status
Simulation time 2124723840 ps
CPU time 2.47 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:08 PM PDT 24
Peak memory 201808 kb
Host smart-6597e38e-7966-40fd-9fb0-2c8bf0133470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706152202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3706152202
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.3718240260
Short name T243
Test name
Test status
Simulation time 168005256266 ps
CPU time 435.62 seconds
Started Apr 02 01:05:11 PM PDT 24
Finished Apr 02 01:12:26 PM PDT 24
Peak memory 202228 kb
Host smart-6fd2db62-e996-4879-8ff0-e98de1ebd2f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718240260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.3718240260
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3979680138
Short name T269
Test name
Test status
Simulation time 19212754386 ps
CPU time 48.97 seconds
Started Apr 02 01:05:05 PM PDT 24
Finished Apr 02 01:05:55 PM PDT 24
Peak memory 210508 kb
Host smart-dba022b1-4f73-4425-87ef-e101c4e3a0ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979680138 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.3979680138
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.607396306
Short name T134
Test name
Test status
Simulation time 6754472450 ps
CPU time 1.55 seconds
Started Apr 02 01:05:03 PM PDT 24
Finished Apr 02 01:05:05 PM PDT 24
Peak memory 201912 kb
Host smart-0ca3ccb9-19b0-4474-8f74-998d79147df8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607396306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_ultra_low_pwr.607396306
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.611413230
Short name T636
Test name
Test status
Simulation time 2014922394 ps
CPU time 3.33 seconds
Started Apr 02 01:02:54 PM PDT 24
Finished Apr 02 01:02:58 PM PDT 24
Peak memory 202008 kb
Host smart-3e464feb-d065-4de1-84ac-ed98ff909035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611413230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test
.611413230
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.637252977
Short name T524
Test name
Test status
Simulation time 3692665605 ps
CPU time 3.54 seconds
Started Apr 02 01:02:52 PM PDT 24
Finished Apr 02 01:02:56 PM PDT 24
Peak memory 202016 kb
Host smart-0550909d-0bbc-4568-98a8-3f378a451d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637252977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.637252977
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.130466187
Short name T557
Test name
Test status
Simulation time 116153271784 ps
CPU time 171.24 seconds
Started Apr 02 01:02:49 PM PDT 24
Finished Apr 02 01:05:41 PM PDT 24
Peak memory 202132 kb
Host smart-4102ed8c-a071-47d7-910e-88181e223388
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130466187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_combo_detect.130466187
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2801665755
Short name T421
Test name
Test status
Simulation time 2246718389 ps
CPU time 2.01 seconds
Started Apr 02 01:02:47 PM PDT 24
Finished Apr 02 01:02:50 PM PDT 24
Peak memory 201932 kb
Host smart-ddee8268-58bb-4e3a-96bc-7d63e23a1a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801665755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2801665755
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.276075314
Short name T520
Test name
Test status
Simulation time 2381744048 ps
CPU time 2.13 seconds
Started Apr 02 01:02:49 PM PDT 24
Finished Apr 02 01:02:52 PM PDT 24
Peak memory 201800 kb
Host smart-66e86655-9d62-41d9-8c86-f3bbdb6b0097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276075314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.276075314
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.79201223
Short name T239
Test name
Test status
Simulation time 36314776409 ps
CPU time 51.94 seconds
Started Apr 02 01:02:50 PM PDT 24
Finished Apr 02 01:03:43 PM PDT 24
Peak memory 202096 kb
Host smart-02a827ec-3411-49d5-b2d3-6c8bdeed1d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79201223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with
_pre_cond.79201223
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.3181574554
Short name T479
Test name
Test status
Simulation time 2377820834 ps
CPU time 6.87 seconds
Started Apr 02 01:02:51 PM PDT 24
Finished Apr 02 01:02:58 PM PDT 24
Peak memory 201916 kb
Host smart-99843dc4-c292-476f-ab70-e44c40f56e4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181574554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.3181574554
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3155330321
Short name T657
Test name
Test status
Simulation time 2611145625 ps
CPU time 7.58 seconds
Started Apr 02 01:02:49 PM PDT 24
Finished Apr 02 01:02:58 PM PDT 24
Peak memory 201852 kb
Host smart-5097ac07-afd2-4387-9994-f0c2cebc42e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155330321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.3155330321
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.4156580916
Short name T65
Test name
Test status
Simulation time 2463993679 ps
CPU time 6.74 seconds
Started Apr 02 01:02:46 PM PDT 24
Finished Apr 02 01:02:54 PM PDT 24
Peak memory 201944 kb
Host smart-090f633a-71de-48e2-ab79-cbd324eb2ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156580916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.4156580916
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.476340272
Short name T510
Test name
Test status
Simulation time 2043207261 ps
CPU time 1.87 seconds
Started Apr 02 01:02:50 PM PDT 24
Finished Apr 02 01:02:52 PM PDT 24
Peak memory 201852 kb
Host smart-52482d80-c90a-4b2c-bf5c-f293952ac75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476340272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.476340272
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1404615535
Short name T360
Test name
Test status
Simulation time 2530999715 ps
CPU time 2.29 seconds
Started Apr 02 01:02:52 PM PDT 24
Finished Apr 02 01:02:55 PM PDT 24
Peak memory 201936 kb
Host smart-ba60dcbf-bdc0-417a-bf97-3137346c74a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404615535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1404615535
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.467618120
Short name T258
Test name
Test status
Simulation time 42579046104 ps
CPU time 8.12 seconds
Started Apr 02 01:02:53 PM PDT 24
Finished Apr 02 01:03:01 PM PDT 24
Peak memory 221708 kb
Host smart-cbf19033-6255-492a-91a7-bb282cfb76ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467618120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.467618120
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.2714168984
Short name T529
Test name
Test status
Simulation time 2112875257 ps
CPU time 6.05 seconds
Started Apr 02 01:02:47 PM PDT 24
Finished Apr 02 01:02:54 PM PDT 24
Peak memory 201828 kb
Host smart-bded6e86-581a-44d3-ad5a-de7ab4214818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714168984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2714168984
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.649439171
Short name T550
Test name
Test status
Simulation time 17027869220 ps
CPU time 9.35 seconds
Started Apr 02 01:02:54 PM PDT 24
Finished Apr 02 01:03:04 PM PDT 24
Peak memory 201944 kb
Host smart-f9dc7264-5128-446f-9b2f-93a473baf8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649439171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_str
ess_all.649439171
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2724391551
Short name T157
Test name
Test status
Simulation time 213522812593 ps
CPU time 139.75 seconds
Started Apr 02 01:02:50 PM PDT 24
Finished Apr 02 01:05:11 PM PDT 24
Peak memory 215504 kb
Host smart-2a93ab59-0c28-449f-9e8e-f5d5b2b11ce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724391551 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.2724391551
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.4106252976
Short name T363
Test name
Test status
Simulation time 2022329937 ps
CPU time 3.26 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:05:15 PM PDT 24
Peak memory 202024 kb
Host smart-f8163f47-5c6a-4c0a-a0ec-256f27eb52ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106252976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.4106252976
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2744393103
Short name T126
Test name
Test status
Simulation time 3301420942 ps
CPU time 2.91 seconds
Started Apr 02 01:05:07 PM PDT 24
Finished Apr 02 01:05:10 PM PDT 24
Peak memory 201908 kb
Host smart-e3a6641d-8172-4b32-b757-a18a07319b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744393103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.2
744393103
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3425042051
Short name T210
Test name
Test status
Simulation time 193519264766 ps
CPU time 117.14 seconds
Started Apr 02 01:05:08 PM PDT 24
Finished Apr 02 01:07:05 PM PDT 24
Peak memory 202084 kb
Host smart-6f193156-a026-4b7d-a149-44386be6dd8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425042051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3425042051
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1960960428
Short name T630
Test name
Test status
Simulation time 2627028783 ps
CPU time 7.04 seconds
Started Apr 02 01:05:10 PM PDT 24
Finished Apr 02 01:05:18 PM PDT 24
Peak memory 201824 kb
Host smart-f4ed63ff-5172-4d8f-bf32-83368fc97e96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960960428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.1960960428
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3433516607
Short name T147
Test name
Test status
Simulation time 3449410928 ps
CPU time 2.61 seconds
Started Apr 02 01:05:09 PM PDT 24
Finished Apr 02 01:05:13 PM PDT 24
Peak memory 201916 kb
Host smart-aa39cec2-d9e0-4411-9cf8-0b36d314eb35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433516607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.3433516607
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1235523814
Short name T379
Test name
Test status
Simulation time 2676747529 ps
CPU time 1.44 seconds
Started Apr 02 01:05:10 PM PDT 24
Finished Apr 02 01:05:12 PM PDT 24
Peak memory 201972 kb
Host smart-fae31357-2e74-4edc-8547-564739251aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235523814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1235523814
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1759595253
Short name T537
Test name
Test status
Simulation time 2441570973 ps
CPU time 4.77 seconds
Started Apr 02 01:05:11 PM PDT 24
Finished Apr 02 01:05:16 PM PDT 24
Peak memory 201936 kb
Host smart-70e2b382-bc2b-4690-913d-32565993083d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759595253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1759595253
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.4194573914
Short name T683
Test name
Test status
Simulation time 2193250817 ps
CPU time 3.72 seconds
Started Apr 02 01:05:10 PM PDT 24
Finished Apr 02 01:05:14 PM PDT 24
Peak memory 201776 kb
Host smart-9b95cd51-1977-4ecf-9475-70f90228fb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194573914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.4194573914
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1834834111
Short name T70
Test name
Test status
Simulation time 2529687214 ps
CPU time 2.16 seconds
Started Apr 02 01:05:15 PM PDT 24
Finished Apr 02 01:05:17 PM PDT 24
Peak memory 201956 kb
Host smart-920c1178-6ea9-40f6-bbaa-acea4effe5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834834111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.1834834111
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.919960265
Short name T673
Test name
Test status
Simulation time 2136342922 ps
CPU time 1.99 seconds
Started Apr 02 01:05:10 PM PDT 24
Finished Apr 02 01:05:12 PM PDT 24
Peak memory 201872 kb
Host smart-5210daa8-ec03-4b95-abc7-8d11be6c9805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919960265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.919960265
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.355986526
Short name T303
Test name
Test status
Simulation time 86197711141 ps
CPU time 18.54 seconds
Started Apr 02 01:05:10 PM PDT 24
Finished Apr 02 01:05:29 PM PDT 24
Peak memory 202052 kb
Host smart-49848772-2321-4f28-80c7-cab8c8e618a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355986526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_st
ress_all.355986526
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3579430743
Short name T139
Test name
Test status
Simulation time 5332663543 ps
CPU time 3.9 seconds
Started Apr 02 01:05:11 PM PDT 24
Finished Apr 02 01:05:15 PM PDT 24
Peak memory 201840 kb
Host smart-769a8fca-cb34-4738-a914-3b0ea08cecc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579430743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.3579430743
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.4179760622
Short name T172
Test name
Test status
Simulation time 2011859500 ps
CPU time 5.74 seconds
Started Apr 02 01:05:14 PM PDT 24
Finished Apr 02 01:05:20 PM PDT 24
Peak memory 201964 kb
Host smart-3b20b57b-133b-4a84-9390-82b657d882b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179760622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.4179760622
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1638397692
Short name T436
Test name
Test status
Simulation time 3532707277 ps
CPU time 1.98 seconds
Started Apr 02 01:05:18 PM PDT 24
Finished Apr 02 01:05:20 PM PDT 24
Peak memory 202020 kb
Host smart-2ac6cd4d-80e6-4269-b75c-7aae4e7331f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638397692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.1
638397692
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.673367614
Short name T254
Test name
Test status
Simulation time 73966669653 ps
CPU time 176.24 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:08:08 PM PDT 24
Peak memory 202104 kb
Host smart-e151b921-24c3-4f3a-bd74-60bdc7895157
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673367614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_combo_detect.673367614
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.1424508401
Short name T315
Test name
Test status
Simulation time 149802653708 ps
CPU time 383.32 seconds
Started Apr 02 01:05:15 PM PDT 24
Finished Apr 02 01:11:38 PM PDT 24
Peak memory 202180 kb
Host smart-8b50af69-ae1b-451e-b0c6-34295bd43b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424508401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.1424508401
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3426608946
Short name T150
Test name
Test status
Simulation time 5618724525 ps
CPU time 3.06 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:05:15 PM PDT 24
Peak memory 201936 kb
Host smart-dbac54fc-ea95-4356-8372-58137790e686
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426608946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.3426608946
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1693357489
Short name T641
Test name
Test status
Simulation time 2627570876 ps
CPU time 2.08 seconds
Started Apr 02 01:05:18 PM PDT 24
Finished Apr 02 01:05:20 PM PDT 24
Peak memory 201944 kb
Host smart-441bba2e-db97-4149-be33-b7496be01e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693357489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1693357489
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3779737277
Short name T486
Test name
Test status
Simulation time 2550290609 ps
CPU time 1.34 seconds
Started Apr 02 01:05:07 PM PDT 24
Finished Apr 02 01:05:09 PM PDT 24
Peak memory 201904 kb
Host smart-6c7396ef-4b7a-4c03-8483-4e4363718a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779737277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.3779737277
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1350489244
Short name T773
Test name
Test status
Simulation time 2141618873 ps
CPU time 1.91 seconds
Started Apr 02 01:05:10 PM PDT 24
Finished Apr 02 01:05:12 PM PDT 24
Peak memory 201692 kb
Host smart-9d9df4d3-b75e-4e6b-aea5-39ad33103dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350489244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1350489244
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1542828735
Short name T638
Test name
Test status
Simulation time 2513564663 ps
CPU time 6.66 seconds
Started Apr 02 01:05:15 PM PDT 24
Finished Apr 02 01:05:22 PM PDT 24
Peak memory 201956 kb
Host smart-34d0f032-b456-486e-b957-1296f8fa8f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542828735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.1542828735
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.3081837088
Short name T571
Test name
Test status
Simulation time 2113738953 ps
CPU time 3.42 seconds
Started Apr 02 01:05:18 PM PDT 24
Finished Apr 02 01:05:21 PM PDT 24
Peak memory 201880 kb
Host smart-3c792ec2-93cf-4273-890c-40e2bd51d38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081837088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3081837088
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.2610257940
Short name T63
Test name
Test status
Simulation time 7088975327 ps
CPU time 19.23 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:05:32 PM PDT 24
Peak memory 201948 kb
Host smart-d3e5a067-274c-4b38-bcbd-da2cbe928201
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610257940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.2610257940
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1288157294
Short name T714
Test name
Test status
Simulation time 3537434293 ps
CPU time 6.1 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:05:18 PM PDT 24
Peak memory 201928 kb
Host smart-dd3306c1-9d8e-4ea3-aefb-17edd7deeced
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288157294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.1288157294
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.1290179820
Short name T477
Test name
Test status
Simulation time 2025356617 ps
CPU time 2.02 seconds
Started Apr 02 01:05:13 PM PDT 24
Finished Apr 02 01:05:15 PM PDT 24
Peak memory 202012 kb
Host smart-5435d435-b6d0-4261-b2ae-a25f21d5d1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290179820 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.1290179820
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2575280867
Short name T452
Test name
Test status
Simulation time 3145352823 ps
CPU time 9.33 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:05:22 PM PDT 24
Peak memory 202016 kb
Host smart-f32c7f47-bc3f-44d0-a413-83240110b057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575280867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.2
575280867
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.3263012607
Short name T197
Test name
Test status
Simulation time 214002219166 ps
CPU time 290.37 seconds
Started Apr 02 01:05:15 PM PDT 24
Finished Apr 02 01:10:06 PM PDT 24
Peak memory 202168 kb
Host smart-b8337fc2-27e3-4d7c-ae49-533f632f10d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263012607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.3263012607
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2460836497
Short name T49
Test name
Test status
Simulation time 29334255170 ps
CPU time 75.34 seconds
Started Apr 02 01:05:17 PM PDT 24
Finished Apr 02 01:06:32 PM PDT 24
Peak memory 202148 kb
Host smart-b916a1c5-2948-4768-a402-82b7d4e18595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460836497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_w
ith_pre_cond.2460836497
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3216270147
Short name T570
Test name
Test status
Simulation time 3722576090 ps
CPU time 1.17 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:05:13 PM PDT 24
Peak memory 201848 kb
Host smart-e055bd9f-d0af-4a1e-8873-9134f5140673
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216270147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.3216270147
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.4274826712
Short name T614
Test name
Test status
Simulation time 2807115901 ps
CPU time 1.53 seconds
Started Apr 02 01:05:12 PM PDT 24
Finished Apr 02 01:05:14 PM PDT 24
Peak memory 201932 kb
Host smart-e9452575-7b92-4b1b-a6dc-6a5102b0f6c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274826712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.4274826712
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.1931769988
Short name T416
Test name
Test status
Simulation time 2650169249 ps
CPU time 1.73 seconds
Started Apr 02 01:05:10 PM PDT 24
Finished Apr 02 01:05:12 PM PDT 24
Peak memory 201800 kb
Host smart-15ffc64e-269c-476b-9bfd-5a104dac9b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931769988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.1931769988
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.374246247
Short name T700
Test name
Test status
Simulation time 2463099556 ps
CPU time 4.77 seconds
Started Apr 02 01:05:14 PM PDT 24
Finished Apr 02 01:05:19 PM PDT 24
Peak memory 201924 kb
Host smart-6f84006d-4571-46c5-b585-e97f4a9c0259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374246247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.374246247
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.2772892454
Short name T162
Test name
Test status
Simulation time 2193415647 ps
CPU time 2.14 seconds
Started Apr 02 01:05:10 PM PDT 24
Finished Apr 02 01:05:13 PM PDT 24
Peak memory 201876 kb
Host smart-e180b681-c628-4637-b1a8-08b118c8e4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772892454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.2772892454
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.56904452
Short name T365
Test name
Test status
Simulation time 2520682786 ps
CPU time 2.73 seconds
Started Apr 02 01:05:15 PM PDT 24
Finished Apr 02 01:05:17 PM PDT 24
Peak memory 201812 kb
Host smart-9308d00d-4ab6-47b5-ba6f-eadb3c3caeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56904452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.56904452
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.1022554257
Short name T204
Test name
Test status
Simulation time 2109907605 ps
CPU time 6.15 seconds
Started Apr 02 01:05:18 PM PDT 24
Finished Apr 02 01:05:24 PM PDT 24
Peak memory 201880 kb
Host smart-dd857fe6-24c1-4fc9-9dce-624fa5a8a0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022554257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1022554257
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1467656441
Short name T299
Test name
Test status
Simulation time 124131433500 ps
CPU time 83.25 seconds
Started Apr 02 01:05:15 PM PDT 24
Finished Apr 02 01:06:38 PM PDT 24
Peak memory 202180 kb
Host smart-3f016017-840e-44b0-9a2e-5351660472bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467656441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1467656441
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.346534288
Short name T272
Test name
Test status
Simulation time 4553695545 ps
CPU time 5.95 seconds
Started Apr 02 01:05:11 PM PDT 24
Finished Apr 02 01:05:17 PM PDT 24
Peak memory 201912 kb
Host smart-98f6dfaf-f3f5-40a0-bbcf-dc8b03fc2195
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346534288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_ultra_low_pwr.346534288
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.20429374
Short name T676
Test name
Test status
Simulation time 2038123031 ps
CPU time 1.72 seconds
Started Apr 02 01:05:20 PM PDT 24
Finished Apr 02 01:05:22 PM PDT 24
Peak memory 201968 kb
Host smart-721319be-f46b-471d-b084-72af43222b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20429374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test
.20429374
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1228870245
Short name T497
Test name
Test status
Simulation time 3429310676 ps
CPU time 9.54 seconds
Started Apr 02 01:05:14 PM PDT 24
Finished Apr 02 01:05:24 PM PDT 24
Peak memory 202032 kb
Host smart-bc8c55a8-70fa-4435-84bd-ca06043a2f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228870245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.1
228870245
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.905381171
Short name T115
Test name
Test status
Simulation time 25944896597 ps
CPU time 17.5 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:39 PM PDT 24
Peak memory 202068 kb
Host smart-7c42b9e9-d2bb-43d0-8262-0736ad0d2ec3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905381171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_combo_detect.905381171
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1541521313
Short name T471
Test name
Test status
Simulation time 2734224764 ps
CPU time 1.83 seconds
Started Apr 02 01:05:15 PM PDT 24
Finished Apr 02 01:05:17 PM PDT 24
Peak memory 201912 kb
Host smart-584dd8d5-5786-44b6-8798-c61086671538
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541521313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.1541521313
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.2647213874
Short name T225
Test name
Test status
Simulation time 3302280318 ps
CPU time 1.93 seconds
Started Apr 02 01:05:19 PM PDT 24
Finished Apr 02 01:05:21 PM PDT 24
Peak memory 201936 kb
Host smart-8b0d9ec2-9568-4104-883f-e32f8333600f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647213874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.2647213874
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2658716603
Short name T729
Test name
Test status
Simulation time 2622097034 ps
CPU time 3.76 seconds
Started Apr 02 01:05:14 PM PDT 24
Finished Apr 02 01:05:18 PM PDT 24
Peak memory 201844 kb
Host smart-7059e08d-444f-4a67-90ea-8a3099aec508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658716603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2658716603
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3873530699
Short name T758
Test name
Test status
Simulation time 2447658069 ps
CPU time 6.83 seconds
Started Apr 02 01:05:16 PM PDT 24
Finished Apr 02 01:05:23 PM PDT 24
Peak memory 201844 kb
Host smart-6683320d-af9b-48b2-bc2a-82ad8c502935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873530699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3873530699
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1095730029
Short name T458
Test name
Test status
Simulation time 2226512066 ps
CPU time 6.27 seconds
Started Apr 02 01:05:18 PM PDT 24
Finished Apr 02 01:05:24 PM PDT 24
Peak memory 201864 kb
Host smart-20f52b23-9624-432f-9225-665f72d483cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095730029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.1095730029
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2042939908
Short name T546
Test name
Test status
Simulation time 2526887555 ps
CPU time 2.59 seconds
Started Apr 02 01:05:19 PM PDT 24
Finished Apr 02 01:05:21 PM PDT 24
Peak memory 201892 kb
Host smart-6582ff24-25bb-42ce-a329-f212983990b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042939908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.2042939908
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.2392624120
Short name T417
Test name
Test status
Simulation time 2111869584 ps
CPU time 6.55 seconds
Started Apr 02 01:05:18 PM PDT 24
Finished Apr 02 01:05:25 PM PDT 24
Peak memory 201804 kb
Host smart-c7670b42-04a9-4602-a353-8a37cad9f70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392624120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2392624120
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.3205074887
Short name T413
Test name
Test status
Simulation time 8266965692 ps
CPU time 12.39 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:34 PM PDT 24
Peak memory 201944 kb
Host smart-1cfcda6e-0f5a-42d7-9f9c-f6c86f68de6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205074887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.3205074887
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3055328018
Short name T133
Test name
Test status
Simulation time 5569429973 ps
CPU time 2.53 seconds
Started Apr 02 01:05:14 PM PDT 24
Finished Apr 02 01:05:17 PM PDT 24
Peak memory 201840 kb
Host smart-59e86c84-d96b-48f4-ba8d-eacafc163def
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055328018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.3055328018
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.752385169
Short name T609
Test name
Test status
Simulation time 2035556653 ps
CPU time 1.9 seconds
Started Apr 02 01:05:19 PM PDT 24
Finished Apr 02 01:05:21 PM PDT 24
Peak memory 202008 kb
Host smart-f7a20005-f3bb-4d1f-8901-b58ebe8bd82f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752385169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_tes
t.752385169
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3788875534
Short name T716
Test name
Test status
Simulation time 3294021355 ps
CPU time 9.32 seconds
Started Apr 02 01:05:20 PM PDT 24
Finished Apr 02 01:05:29 PM PDT 24
Peak memory 201980 kb
Host smart-6995f1b4-b209-4706-8634-470d3ef4d078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788875534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.3
788875534
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.808458921
Short name T535
Test name
Test status
Simulation time 43115927329 ps
CPU time 116.6 seconds
Started Apr 02 01:05:22 PM PDT 24
Finished Apr 02 01:07:19 PM PDT 24
Peak memory 202152 kb
Host smart-07738648-ee06-40ef-9bb6-ee6c6966304b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808458921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_combo_detect.808458921
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1780295506
Short name T548
Test name
Test status
Simulation time 54547963013 ps
CPU time 68.78 seconds
Started Apr 02 01:05:20 PM PDT 24
Finished Apr 02 01:06:29 PM PDT 24
Peak memory 202080 kb
Host smart-3241c90e-c3d0-43ce-81ad-6f192632656b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780295506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w
ith_pre_cond.1780295506
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1384005617
Short name T490
Test name
Test status
Simulation time 2749606574 ps
CPU time 4.18 seconds
Started Apr 02 01:05:19 PM PDT 24
Finished Apr 02 01:05:23 PM PDT 24
Peak memory 201868 kb
Host smart-608f4bdf-a012-4dc4-9f7a-e363a2beef80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384005617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.1384005617
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.4187777644
Short name T768
Test name
Test status
Simulation time 2615603075 ps
CPU time 3.63 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:25 PM PDT 24
Peak memory 201900 kb
Host smart-558880cc-064f-4598-96c3-12c517073844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187777644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.4187777644
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3308144516
Short name T398
Test name
Test status
Simulation time 2469970824 ps
CPU time 2.35 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:23 PM PDT 24
Peak memory 201972 kb
Host smart-ee7285ae-1176-4935-8c53-aa034e8ec323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308144516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.3308144516
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4020671491
Short name T544
Test name
Test status
Simulation time 2208751752 ps
CPU time 3.43 seconds
Started Apr 02 01:05:18 PM PDT 24
Finished Apr 02 01:05:21 PM PDT 24
Peak memory 201924 kb
Host smart-7b2d3b4d-ce95-4a2b-9ebd-0b25ec3ac458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020671491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.4020671491
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3331576857
Short name T351
Test name
Test status
Simulation time 2525029112 ps
CPU time 2.35 seconds
Started Apr 02 01:05:19 PM PDT 24
Finished Apr 02 01:05:22 PM PDT 24
Peak memory 201908 kb
Host smart-2063e0c3-6bc0-4866-98e5-196ca6f4e750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331576857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3331576857
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.1264702164
Short name T744
Test name
Test status
Simulation time 2115669647 ps
CPU time 3.39 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:24 PM PDT 24
Peak memory 201844 kb
Host smart-aa8880af-46c0-4be3-ae61-298953b93108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264702164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.1264702164
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.2084115933
Short name T485
Test name
Test status
Simulation time 7038609882 ps
CPU time 3.24 seconds
Started Apr 02 01:05:18 PM PDT 24
Finished Apr 02 01:05:21 PM PDT 24
Peak memory 201940 kb
Host smart-0ad4898b-45fe-408f-8a09-9929c268ccfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084115933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.2084115933
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3185788383
Short name T757
Test name
Test status
Simulation time 9124178615 ps
CPU time 8.08 seconds
Started Apr 02 01:05:18 PM PDT 24
Finished Apr 02 01:05:26 PM PDT 24
Peak memory 201988 kb
Host smart-02c59424-8fe3-4c5e-9f8a-25db191c9ae3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185788383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.3185788383
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.2706722587
Short name T368
Test name
Test status
Simulation time 2068323623 ps
CPU time 1.06 seconds
Started Apr 02 01:05:23 PM PDT 24
Finished Apr 02 01:05:24 PM PDT 24
Peak memory 202032 kb
Host smart-b688cedb-5696-4eb1-b77f-dfdb7fce30ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706722587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te
st.2706722587
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3741931243
Short name T43
Test name
Test status
Simulation time 3454530424 ps
CPU time 1.6 seconds
Started Apr 02 01:05:22 PM PDT 24
Finished Apr 02 01:05:24 PM PDT 24
Peak memory 202016 kb
Host smart-13bb21ec-6dda-42cd-b236-a3fd96555b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741931243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.3
741931243
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3372133503
Short name T259
Test name
Test status
Simulation time 151219710722 ps
CPU time 96.86 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:06:58 PM PDT 24
Peak memory 202132 kb
Host smart-9d4e4940-4575-442c-bb1b-4fac577eb77b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372133503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.3372133503
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1999025912
Short name T322
Test name
Test status
Simulation time 96371009260 ps
CPU time 268.64 seconds
Started Apr 02 01:05:22 PM PDT 24
Finished Apr 02 01:09:51 PM PDT 24
Peak memory 202232 kb
Host smart-1d05ac7a-9b79-4ef2-bfc7-27775ddc86f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999025912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.1999025912
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.648509968
Short name T604
Test name
Test status
Simulation time 3181601961 ps
CPU time 2.72 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:24 PM PDT 24
Peak memory 201852 kb
Host smart-40588f5f-001d-472e-a5cd-46a085981489
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648509968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ec_pwr_on_rst.648509968
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.629256187
Short name T184
Test name
Test status
Simulation time 4685797842 ps
CPU time 2.82 seconds
Started Apr 02 01:05:23 PM PDT 24
Finished Apr 02 01:05:26 PM PDT 24
Peak memory 201920 kb
Host smart-c60f9a1e-07f5-408c-ba48-89ea15d0edb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629256187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctr
l_edge_detect.629256187
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4129929971
Short name T119
Test name
Test status
Simulation time 2611350514 ps
CPU time 7.51 seconds
Started Apr 02 01:05:24 PM PDT 24
Finished Apr 02 01:05:32 PM PDT 24
Peak memory 201952 kb
Host smart-3fc1068f-0172-45d8-8285-8c0f7a52cdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129929971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.4129929971
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3998147529
Short name T400
Test name
Test status
Simulation time 2445059658 ps
CPU time 3.82 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:25 PM PDT 24
Peak memory 201884 kb
Host smart-526758d6-abcd-4986-86f7-c4bacfd20e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998147529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3998147529
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.4226792733
Short name T195
Test name
Test status
Simulation time 2213143407 ps
CPU time 1.93 seconds
Started Apr 02 01:05:20 PM PDT 24
Finished Apr 02 01:05:22 PM PDT 24
Peak memory 201872 kb
Host smart-7746c850-3f71-486a-b606-6447d124990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226792733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.4226792733
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3333268745
Short name T131
Test name
Test status
Simulation time 2516929319 ps
CPU time 4.06 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:25 PM PDT 24
Peak memory 201916 kb
Host smart-a8cde07a-3d52-42f9-a449-895f2de0e7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333268745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.3333268745
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.685462561
Short name T502
Test name
Test status
Simulation time 2110844464 ps
CPU time 6.32 seconds
Started Apr 02 01:05:19 PM PDT 24
Finished Apr 02 01:05:25 PM PDT 24
Peak memory 201832 kb
Host smart-7179c278-ebff-4a7c-94e1-0281b2e004ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685462561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.685462561
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.249983406
Short name T226
Test name
Test status
Simulation time 12841400345 ps
CPU time 16.31 seconds
Started Apr 02 01:05:22 PM PDT 24
Finished Apr 02 01:05:38 PM PDT 24
Peak memory 201944 kb
Host smart-2c6b4dc4-302c-4e6d-9697-5d3fa81a5393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249983406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_st
ress_all.249983406
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4202262087
Short name T268
Test name
Test status
Simulation time 45651517422 ps
CPU time 24.43 seconds
Started Apr 02 01:05:23 PM PDT 24
Finished Apr 02 01:05:47 PM PDT 24
Peak memory 210556 kb
Host smart-8ea77c9a-0718-40ce-a412-346a8616a060
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202262087 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.4202262087
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2525699147
Short name T483
Test name
Test status
Simulation time 4662968257 ps
CPU time 6.84 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:28 PM PDT 24
Peak memory 201884 kb
Host smart-4c4f96f8-d720-489b-9099-f04e50a36ba3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525699147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.2525699147
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.498248674
Short name T726
Test name
Test status
Simulation time 2036813493 ps
CPU time 2.11 seconds
Started Apr 02 01:05:25 PM PDT 24
Finished Apr 02 01:05:28 PM PDT 24
Peak memory 201984 kb
Host smart-31abe88d-68ed-482b-8e25-c171a40bc8fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498248674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_tes
t.498248674
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.977019416
Short name T438
Test name
Test status
Simulation time 3597526689 ps
CPU time 3.12 seconds
Started Apr 02 01:05:23 PM PDT 24
Finished Apr 02 01:05:26 PM PDT 24
Peak memory 202060 kb
Host smart-bfdf9e9e-bba4-47cc-959f-c0f69ece2623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977019416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.977019416
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.4036927542
Short name T111
Test name
Test status
Simulation time 60026629343 ps
CPU time 84.25 seconds
Started Apr 02 01:05:25 PM PDT 24
Finished Apr 02 01:06:49 PM PDT 24
Peak memory 202104 kb
Host smart-250f070e-bc3f-4ba6-bdff-7195fda31134
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036927542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.4036927542
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2459989972
Short name T200
Test name
Test status
Simulation time 75754319788 ps
CPU time 187.87 seconds
Started Apr 02 01:05:25 PM PDT 24
Finished Apr 02 01:08:33 PM PDT 24
Peak memory 202164 kb
Host smart-f5ccb7ae-b1ca-4061-a07f-746d62d21b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459989972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.2459989972
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2271359347
Short name T658
Test name
Test status
Simulation time 3643721623 ps
CPU time 2.91 seconds
Started Apr 02 01:05:24 PM PDT 24
Finished Apr 02 01:05:27 PM PDT 24
Peak memory 201928 kb
Host smart-b66b4e14-f136-4e1e-849c-a5930118bf7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271359347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ec_pwr_on_rst.2271359347
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2624148581
Short name T202
Test name
Test status
Simulation time 2675884832 ps
CPU time 1.1 seconds
Started Apr 02 01:05:25 PM PDT 24
Finished Apr 02 01:05:27 PM PDT 24
Peak memory 201952 kb
Host smart-c064e719-9939-4692-9acc-317961243ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624148581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.2624148581
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3262288806
Short name T575
Test name
Test status
Simulation time 2495600056 ps
CPU time 2.55 seconds
Started Apr 02 01:05:24 PM PDT 24
Finished Apr 02 01:05:27 PM PDT 24
Peak memory 201920 kb
Host smart-4681a4d2-a365-44ac-bca1-8669ae281865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262288806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3262288806
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1989505322
Short name T532
Test name
Test status
Simulation time 2059738350 ps
CPU time 3.29 seconds
Started Apr 02 01:05:21 PM PDT 24
Finished Apr 02 01:05:24 PM PDT 24
Peak memory 201860 kb
Host smart-7fb460e0-358b-4134-84c3-28c41c8eeeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989505322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1989505322
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2434658823
Short name T445
Test name
Test status
Simulation time 2509467329 ps
CPU time 7.09 seconds
Started Apr 02 01:05:23 PM PDT 24
Finished Apr 02 01:05:30 PM PDT 24
Peak memory 201820 kb
Host smart-7622c209-b85e-4d0b-b727-98cc13fdd345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434658823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2434658823
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.34735350
Short name T539
Test name
Test status
Simulation time 2112034531 ps
CPU time 5.7 seconds
Started Apr 02 01:05:22 PM PDT 24
Finished Apr 02 01:05:28 PM PDT 24
Peak memory 201824 kb
Host smart-90933156-155e-4ed2-b580-a70a86d7d729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34735350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.34735350
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.3329501073
Short name T610
Test name
Test status
Simulation time 7077686178 ps
CPU time 20.04 seconds
Started Apr 02 01:05:29 PM PDT 24
Finished Apr 02 01:05:49 PM PDT 24
Peak memory 201884 kb
Host smart-31279693-cb16-46b6-a6a4-f92cbb2fc080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329501073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.3329501073
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3237059268
Short name T274
Test name
Test status
Simulation time 93465203561 ps
CPU time 58.16 seconds
Started Apr 02 01:05:31 PM PDT 24
Finished Apr 02 01:06:30 PM PDT 24
Peak memory 218640 kb
Host smart-e3e9d049-5865-4f31-a1aa-f741cbfd8f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237059268 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.3237059268
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.1876025430
Short name T519
Test name
Test status
Simulation time 2038091960 ps
CPU time 2 seconds
Started Apr 02 01:05:30 PM PDT 24
Finished Apr 02 01:05:32 PM PDT 24
Peak memory 202020 kb
Host smart-bb20e616-5221-4d99-9216-7cab28844ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876025430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.1876025430
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3763246096
Short name T580
Test name
Test status
Simulation time 3898145961 ps
CPU time 5.88 seconds
Started Apr 02 01:05:27 PM PDT 24
Finished Apr 02 01:05:33 PM PDT 24
Peak memory 201996 kb
Host smart-a7dcd883-ef3c-4983-9ca7-a7781b0b3a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763246096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3
763246096
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.3466949262
Short name T645
Test name
Test status
Simulation time 35602575911 ps
CPU time 93.06 seconds
Started Apr 02 01:05:30 PM PDT 24
Finished Apr 02 01:07:03 PM PDT 24
Peak memory 202104 kb
Host smart-733bed73-74a9-414b-b5e0-053de29e208f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466949262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.3466949262
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1230008518
Short name T655
Test name
Test status
Simulation time 3042294773 ps
CPU time 8.96 seconds
Started Apr 02 01:05:32 PM PDT 24
Finished Apr 02 01:05:41 PM PDT 24
Peak memory 201656 kb
Host smart-b3cda727-00b0-407a-a331-4d36b3d7c7ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230008518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.1230008518
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2479831703
Short name T17
Test name
Test status
Simulation time 2612327532 ps
CPU time 7.63 seconds
Started Apr 02 01:05:30 PM PDT 24
Finished Apr 02 01:05:38 PM PDT 24
Peak memory 201844 kb
Host smart-caac7db7-5e15-4814-8c78-d2e1ed9343dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479831703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.2479831703
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2314689767
Short name T642
Test name
Test status
Simulation time 2472697964 ps
CPU time 2.28 seconds
Started Apr 02 01:05:29 PM PDT 24
Finished Apr 02 01:05:31 PM PDT 24
Peak memory 201896 kb
Host smart-40078ea9-9fc3-446d-9305-fa7da593b21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314689767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2314689767
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3023991020
Short name T430
Test name
Test status
Simulation time 2109292010 ps
CPU time 2.54 seconds
Started Apr 02 01:05:31 PM PDT 24
Finished Apr 02 01:05:34 PM PDT 24
Peak memory 201836 kb
Host smart-b5d3900d-6e59-470d-b83c-800e322b89da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023991020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3023991020
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1185506731
Short name T136
Test name
Test status
Simulation time 2518878128 ps
CPU time 3.91 seconds
Started Apr 02 01:05:29 PM PDT 24
Finished Apr 02 01:05:33 PM PDT 24
Peak memory 201932 kb
Host smart-aa28fed9-f637-4e6b-9fd7-81283f8f8373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185506731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1185506731
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.1930809728
Short name T772
Test name
Test status
Simulation time 2115055709 ps
CPU time 5.56 seconds
Started Apr 02 01:05:32 PM PDT 24
Finished Apr 02 01:05:38 PM PDT 24
Peak memory 201596 kb
Host smart-f41c5969-988d-4ef8-8d2a-d48480c469d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930809728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.1930809728
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.3512616332
Short name T718
Test name
Test status
Simulation time 548619151560 ps
CPU time 677.74 seconds
Started Apr 02 01:05:31 PM PDT 24
Finished Apr 02 01:16:49 PM PDT 24
Peak memory 201928 kb
Host smart-7bd9a284-dc0a-4411-b6e4-c0ed079f24eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512616332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.3512616332
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1142733688
Short name T270
Test name
Test status
Simulation time 25783298229 ps
CPU time 54.51 seconds
Started Apr 02 01:05:27 PM PDT 24
Finished Apr 02 01:06:22 PM PDT 24
Peak memory 210528 kb
Host smart-08b334ac-95c3-4687-8909-05ef2da54020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142733688 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1142733688
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1898781650
Short name T463
Test name
Test status
Simulation time 12307310592 ps
CPU time 9.67 seconds
Started Apr 02 01:05:32 PM PDT 24
Finished Apr 02 01:05:42 PM PDT 24
Peak memory 201920 kb
Host smart-62560f82-4518-421e-9112-57fb9c25c404
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898781650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.1898781650
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.638411328
Short name T545
Test name
Test status
Simulation time 2043879858 ps
CPU time 1.95 seconds
Started Apr 02 01:05:36 PM PDT 24
Finished Apr 02 01:05:38 PM PDT 24
Peak memory 201920 kb
Host smart-8adddab8-ad2b-429d-ab65-ec5ecc313371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638411328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_tes
t.638411328
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1850727137
Short name T494
Test name
Test status
Simulation time 3791326872 ps
CPU time 3.14 seconds
Started Apr 02 01:05:32 PM PDT 24
Finished Apr 02 01:05:36 PM PDT 24
Peak memory 202016 kb
Host smart-99953fde-1ff4-40f2-8552-33b10cbdd6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850727137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1
850727137
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.951328538
Short name T248
Test name
Test status
Simulation time 15052720264 ps
CPU time 8.61 seconds
Started Apr 02 01:05:36 PM PDT 24
Finished Apr 02 01:05:45 PM PDT 24
Peak memory 202096 kb
Host smart-ddb8dbf7-d46a-4692-ba8e-4bd2ee0cb0be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951328538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_combo_detect.951328538
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3633197962
Short name T669
Test name
Test status
Simulation time 2796362809 ps
CPU time 2.53 seconds
Started Apr 02 01:05:33 PM PDT 24
Finished Apr 02 01:05:37 PM PDT 24
Peak memory 201812 kb
Host smart-e3d5f880-e63c-4d68-8dcb-8d8cf3dad53f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633197962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.3633197962
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.3501193338
Short name T2
Test name
Test status
Simulation time 2626377334 ps
CPU time 2.05 seconds
Started Apr 02 01:05:36 PM PDT 24
Finished Apr 02 01:05:39 PM PDT 24
Peak memory 202004 kb
Host smart-3f07de47-7d06-4933-b86f-23be65ac0d01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501193338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.3501193338
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3171205680
Short name T145
Test name
Test status
Simulation time 2628940982 ps
CPU time 2.32 seconds
Started Apr 02 01:05:31 PM PDT 24
Finished Apr 02 01:05:34 PM PDT 24
Peak memory 201948 kb
Host smart-18affb48-3f19-4de4-9557-d9071ef134d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171205680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3171205680
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.651215538
Short name T367
Test name
Test status
Simulation time 2482535582 ps
CPU time 4.15 seconds
Started Apr 02 01:05:29 PM PDT 24
Finished Apr 02 01:05:33 PM PDT 24
Peak memory 201888 kb
Host smart-57e08be8-03c7-4c7e-885e-56917a501baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651215538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.651215538
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.485598245
Short name T542
Test name
Test status
Simulation time 2056152762 ps
CPU time 1.99 seconds
Started Apr 02 01:05:32 PM PDT 24
Finished Apr 02 01:05:35 PM PDT 24
Peak memory 201740 kb
Host smart-bb65361c-3d0d-477b-a90c-c6f81e7d2dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485598245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.485598245
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3239451085
Short name T371
Test name
Test status
Simulation time 2534437148 ps
CPU time 2.28 seconds
Started Apr 02 01:05:33 PM PDT 24
Finished Apr 02 01:05:36 PM PDT 24
Peak memory 201908 kb
Host smart-247debc8-4bbe-42e8-9cd0-8a336917795b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239451085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3239451085
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.320692526
Short name T120
Test name
Test status
Simulation time 2111590251 ps
CPU time 5.63 seconds
Started Apr 02 01:05:28 PM PDT 24
Finished Apr 02 01:05:34 PM PDT 24
Peak memory 201880 kb
Host smart-82a99674-8d79-417a-b19e-740124d24d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320692526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.320692526
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.3435098189
Short name T736
Test name
Test status
Simulation time 6995909021 ps
CPU time 9.33 seconds
Started Apr 02 01:05:36 PM PDT 24
Finished Apr 02 01:05:46 PM PDT 24
Peak memory 201948 kb
Host smart-a5bfb6b8-5206-4df8-897c-fd01a0b0745a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435098189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.3435098189
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3515747295
Short name T74
Test name
Test status
Simulation time 5475522526 ps
CPU time 7.62 seconds
Started Apr 02 01:05:33 PM PDT 24
Finished Apr 02 01:05:42 PM PDT 24
Peak memory 201952 kb
Host smart-d75141c1-de0c-406e-a8fd-e5ac835cf877
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515747295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.3515747295
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.2646213210
Short name T591
Test name
Test status
Simulation time 2033325509 ps
CPU time 1.9 seconds
Started Apr 02 01:05:39 PM PDT 24
Finished Apr 02 01:05:42 PM PDT 24
Peak memory 201976 kb
Host smart-502f6980-a734-4d43-a3c0-af25d3f2f37f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646213210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.2646213210
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1427751367
Short name T18
Test name
Test status
Simulation time 307690607566 ps
CPU time 780.15 seconds
Started Apr 02 01:05:39 PM PDT 24
Finished Apr 02 01:18:41 PM PDT 24
Peak memory 201996 kb
Host smart-d31693d1-e2e9-40c1-b1e5-6efdc79eea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427751367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.1
427751367
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1865320528
Short name T711
Test name
Test status
Simulation time 49916064238 ps
CPU time 61.73 seconds
Started Apr 02 01:05:39 PM PDT 24
Finished Apr 02 01:06:42 PM PDT 24
Peak memory 202148 kb
Host smart-d5fc0218-3511-43ea-a51f-89ad6266e21c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865320528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.1865320528
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1799334186
Short name T746
Test name
Test status
Simulation time 25832930740 ps
CPU time 66.79 seconds
Started Apr 02 01:05:38 PM PDT 24
Finished Apr 02 01:06:47 PM PDT 24
Peak memory 202004 kb
Host smart-c1bee5ad-8149-44cf-8d6c-6faea2b4d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799334186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.1799334186
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1420150911
Short name T506
Test name
Test status
Simulation time 4411029398 ps
CPU time 2.92 seconds
Started Apr 02 01:05:40 PM PDT 24
Finished Apr 02 01:05:43 PM PDT 24
Peak memory 201940 kb
Host smart-9d70cf8b-afd1-430c-9640-0433d9eb6823
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420150911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.1420150911
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.329152124
Short name T217
Test name
Test status
Simulation time 3695562046 ps
CPU time 5.11 seconds
Started Apr 02 01:05:44 PM PDT 24
Finished Apr 02 01:05:49 PM PDT 24
Peak memory 201940 kb
Host smart-395c58de-8d88-4b81-a40a-448c88e9e80b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329152124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctr
l_edge_detect.329152124
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3417191958
Short name T188
Test name
Test status
Simulation time 2612587362 ps
CPU time 7.47 seconds
Started Apr 02 01:05:39 PM PDT 24
Finished Apr 02 01:05:48 PM PDT 24
Peak memory 201944 kb
Host smart-3686bc4d-eec5-49c4-9b3c-f19f87d29272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417191958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.3417191958
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.627507371
Short name T612
Test name
Test status
Simulation time 2467602822 ps
CPU time 2.45 seconds
Started Apr 02 01:05:37 PM PDT 24
Finished Apr 02 01:05:41 PM PDT 24
Peak memory 201936 kb
Host smart-c1df3b4c-4876-4b33-b5ec-3cbc212e0869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627507371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.627507371
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.480284715
Short name T599
Test name
Test status
Simulation time 2245883886 ps
CPU time 2.17 seconds
Started Apr 02 01:05:37 PM PDT 24
Finished Apr 02 01:05:40 PM PDT 24
Peak memory 201900 kb
Host smart-576bffa9-ca94-4628-a8aa-ed3dbf0ae498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480284715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.480284715
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1027218058
Short name T526
Test name
Test status
Simulation time 2525386471 ps
CPU time 3.56 seconds
Started Apr 02 01:05:36 PM PDT 24
Finished Apr 02 01:05:40 PM PDT 24
Peak memory 201868 kb
Host smart-7d54b5fb-acac-42eb-b58a-20d1af84e092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027218058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1027218058
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.3250425851
Short name T213
Test name
Test status
Simulation time 2132841570 ps
CPU time 1.48 seconds
Started Apr 02 01:05:40 PM PDT 24
Finished Apr 02 01:05:42 PM PDT 24
Peak memory 201864 kb
Host smart-796cae7a-8ae9-473e-979d-c3a1f51699b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250425851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.3250425851
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3836258771
Short name T446
Test name
Test status
Simulation time 6683849823 ps
CPU time 7.18 seconds
Started Apr 02 01:05:41 PM PDT 24
Finished Apr 02 01:05:48 PM PDT 24
Peak memory 201928 kb
Host smart-41f1bdcb-32d8-435a-9955-8c1c17be0ec6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836258771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.3836258771
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.2856744199
Short name T372
Test name
Test status
Simulation time 2022910560 ps
CPU time 3.41 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:09 PM PDT 24
Peak memory 202000 kb
Host smart-234bb9ed-9ced-4daa-9840-9e0158a558b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856744199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.2856744199
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.412137491
Short name T684
Test name
Test status
Simulation time 3226710348 ps
CPU time 9.26 seconds
Started Apr 02 01:02:56 PM PDT 24
Finished Apr 02 01:03:05 PM PDT 24
Peak memory 201868 kb
Host smart-b76c810a-2a65-41f2-b639-6280289a6c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412137491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.412137491
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.65824527
Short name T11
Test name
Test status
Simulation time 97906877489 ps
CPU time 66.49 seconds
Started Apr 02 01:02:59 PM PDT 24
Finished Apr 02 01:04:07 PM PDT 24
Peak memory 202140 kb
Host smart-4d0d085a-ed69-425e-a70e-2e3e2ea1a988
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65824527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl
_combo_detect.65824527
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1381100419
Short name T734
Test name
Test status
Simulation time 3186871703 ps
CPU time 2.19 seconds
Started Apr 02 01:02:58 PM PDT 24
Finished Apr 02 01:03:00 PM PDT 24
Peak memory 201836 kb
Host smart-8308541e-8327-49d5-9c18-6242e094b883
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381100419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ec_pwr_on_rst.1381100419
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.2071467580
Short name T146
Test name
Test status
Simulation time 4031372133 ps
CPU time 7.6 seconds
Started Apr 02 01:02:56 PM PDT 24
Finished Apr 02 01:03:04 PM PDT 24
Peak memory 201936 kb
Host smart-6adeaeba-07cc-446b-8e5e-3a3100a286e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071467580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.2071467580
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1656973425
Short name T429
Test name
Test status
Simulation time 2609548887 ps
CPU time 7.7 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:13 PM PDT 24
Peak memory 201924 kb
Host smart-a59947c7-0249-4a7a-8cb1-3a1d1fec86ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656973425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1656973425
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3435500366
Short name T514
Test name
Test status
Simulation time 2509723961 ps
CPU time 2.49 seconds
Started Apr 02 01:02:53 PM PDT 24
Finished Apr 02 01:02:56 PM PDT 24
Peak memory 201892 kb
Host smart-68a88dfb-7d8b-49f1-9258-cb1273c503f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435500366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.3435500366
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2295253251
Short name T406
Test name
Test status
Simulation time 2164082316 ps
CPU time 1.55 seconds
Started Apr 02 01:02:54 PM PDT 24
Finished Apr 02 01:02:56 PM PDT 24
Peak memory 201928 kb
Host smart-8fbfa602-dd45-492b-b819-24be71bc8e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295253251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.2295253251
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1195324788
Short name T561
Test name
Test status
Simulation time 2514247011 ps
CPU time 5.39 seconds
Started Apr 02 01:02:58 PM PDT 24
Finished Apr 02 01:03:04 PM PDT 24
Peak memory 201916 kb
Host smart-4d3dd842-edb2-4498-be96-7d1ebdedea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195324788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1195324788
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.1842448640
Short name T498
Test name
Test status
Simulation time 2117152790 ps
CPU time 2.75 seconds
Started Apr 02 01:02:53 PM PDT 24
Finished Apr 02 01:02:55 PM PDT 24
Peak memory 201864 kb
Host smart-4c9890ed-8272-473e-9030-ab54301b9ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842448640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1842448640
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.912656460
Short name T782
Test name
Test status
Simulation time 130773962083 ps
CPU time 161.56 seconds
Started Apr 02 01:03:02 PM PDT 24
Finished Apr 02 01:05:44 PM PDT 24
Peak memory 202100 kb
Host smart-f92a3be5-81ba-440e-a4d2-5086a9306568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912656460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_str
ess_all.912656460
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2361877586
Short name T382
Test name
Test status
Simulation time 12501854365 ps
CPU time 4.63 seconds
Started Apr 02 01:02:59 PM PDT 24
Finished Apr 02 01:03:04 PM PDT 24
Peak memory 201792 kb
Host smart-13a6046f-901e-4a4a-9443-0d60e37900d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361877586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.2361877586
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2336076480
Short name T345
Test name
Test status
Simulation time 102734377052 ps
CPU time 47.86 seconds
Started Apr 02 01:05:39 PM PDT 24
Finished Apr 02 01:06:28 PM PDT 24
Peak memory 202172 kb
Host smart-2cf2cfc7-4cd7-4d4e-aa38-9a1f1381e6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336076480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.2336076480
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2192066425
Short name T108
Test name
Test status
Simulation time 83927499133 ps
CPU time 226.67 seconds
Started Apr 02 01:05:41 PM PDT 24
Finished Apr 02 01:09:28 PM PDT 24
Peak memory 202088 kb
Host smart-57d1e98c-56ff-45c8-85a5-401dd0355300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192066425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.2192066425
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2219106413
Short name T572
Test name
Test status
Simulation time 59811429119 ps
CPU time 162.76 seconds
Started Apr 02 01:05:39 PM PDT 24
Finished Apr 02 01:08:23 PM PDT 24
Peak memory 202220 kb
Host smart-4df1c792-ac14-48f7-8ce3-e2b7aed40e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219106413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.2219106413
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4174396239
Short name T462
Test name
Test status
Simulation time 25087697580 ps
CPU time 34.94 seconds
Started Apr 02 01:05:43 PM PDT 24
Finished Apr 02 01:06:19 PM PDT 24
Peak memory 202140 kb
Host smart-b25087d2-67f5-46c3-8e73-5c914ff3b454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174396239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.4174396239
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.34137104
Short name T240
Test name
Test status
Simulation time 97344664261 ps
CPU time 72.33 seconds
Started Apr 02 01:05:44 PM PDT 24
Finished Apr 02 01:06:57 PM PDT 24
Peak memory 202228 kb
Host smart-ec455b0f-d7f4-4963-84de-3dcd80ad5ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34137104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_wit
h_pre_cond.34137104
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2567652120
Short name T238
Test name
Test status
Simulation time 23338042428 ps
CPU time 42.97 seconds
Started Apr 02 01:05:44 PM PDT 24
Finished Apr 02 01:06:27 PM PDT 24
Peak memory 202172 kb
Host smart-4215e165-cec6-4075-9b7e-fdad1097706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567652120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_w
ith_pre_cond.2567652120
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2164121702
Short name T46
Test name
Test status
Simulation time 32331787120 ps
CPU time 85.34 seconds
Started Apr 02 01:05:43 PM PDT 24
Finished Apr 02 01:07:10 PM PDT 24
Peak memory 202140 kb
Host smart-81bba90c-1c09-42c9-910e-d24d41ed136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164121702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.2164121702
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3062579738
Short name T48
Test name
Test status
Simulation time 25097763839 ps
CPU time 18.96 seconds
Started Apr 02 01:05:46 PM PDT 24
Finished Apr 02 01:06:05 PM PDT 24
Peak memory 202168 kb
Host smart-c8d498b0-0afc-47e6-963f-b8ee682666fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062579738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.3062579738
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.76533970
Short name T318
Test name
Test status
Simulation time 82049987249 ps
CPU time 88.81 seconds
Started Apr 02 01:05:49 PM PDT 24
Finished Apr 02 01:07:18 PM PDT 24
Peak memory 202156 kb
Host smart-ad7dfb33-911d-4c28-86ea-89182ef9c754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76533970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_wit
h_pre_cond.76533970
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.2044481409
Short name T555
Test name
Test status
Simulation time 2009178071 ps
CPU time 5.84 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:11 PM PDT 24
Peak memory 201972 kb
Host smart-181582d6-905a-48df-b13b-bd319c7790a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044481409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.2044481409
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1244867046
Short name T556
Test name
Test status
Simulation time 3712976141 ps
CPU time 3.15 seconds
Started Apr 02 01:03:00 PM PDT 24
Finished Apr 02 01:03:03 PM PDT 24
Peak memory 201988 kb
Host smart-82fbf575-7149-43de-aac1-260dc6ccc41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244867046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1244867046
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.471644934
Short name T93
Test name
Test status
Simulation time 77226204259 ps
CPU time 102.58 seconds
Started Apr 02 01:03:00 PM PDT 24
Finished Apr 02 01:04:43 PM PDT 24
Peak memory 202144 kb
Host smart-35f9d9ee-cd59-4fe4-bea0-a02da819f697
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471644934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_combo_detect.471644934
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1906709239
Short name T694
Test name
Test status
Simulation time 3234082586 ps
CPU time 9 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:14 PM PDT 24
Peak memory 201944 kb
Host smart-770b3d1b-e44a-4832-b10f-d842bed4285f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906709239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.1906709239
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.107600677
Short name T181
Test name
Test status
Simulation time 5331361854 ps
CPU time 11.05 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:16 PM PDT 24
Peak memory 201940 kb
Host smart-3034c0a9-3bfa-4c02-a811-34a165e5bb5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107600677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl
_edge_detect.107600677
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.2513154935
Short name T492
Test name
Test status
Simulation time 2636823536 ps
CPU time 2.46 seconds
Started Apr 02 01:03:04 PM PDT 24
Finished Apr 02 01:03:07 PM PDT 24
Peak memory 201952 kb
Host smart-6e577ec1-af2f-4414-b4ed-dc13676a0099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513154935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.2513154935
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1222891868
Short name T721
Test name
Test status
Simulation time 2481920371 ps
CPU time 2.62 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:08 PM PDT 24
Peak memory 201892 kb
Host smart-df8e8d08-cbe2-446e-ae57-81102b914b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222891868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1222891868
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4007384681
Short name T654
Test name
Test status
Simulation time 2273211592 ps
CPU time 2.2 seconds
Started Apr 02 01:03:02 PM PDT 24
Finished Apr 02 01:03:04 PM PDT 24
Peak memory 201916 kb
Host smart-593fb4d2-b311-42c1-b166-38f561c6eebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007384681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.4007384681
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1180634612
Short name T69
Test name
Test status
Simulation time 2510596532 ps
CPU time 7.32 seconds
Started Apr 02 01:03:07 PM PDT 24
Finished Apr 02 01:03:14 PM PDT 24
Peak memory 201916 kb
Host smart-077bba22-c2dd-41a8-8e72-485132100661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180634612 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.1180634612
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.4117966045
Short name T525
Test name
Test status
Simulation time 2112150346 ps
CPU time 6.03 seconds
Started Apr 02 01:03:02 PM PDT 24
Finished Apr 02 01:03:08 PM PDT 24
Peak memory 201836 kb
Host smart-41e7d010-538d-4443-b452-82228088abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117966045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.4117966045
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.625088788
Short name T76
Test name
Test status
Simulation time 108472745335 ps
CPU time 145.66 seconds
Started Apr 02 01:03:03 PM PDT 24
Finished Apr 02 01:05:30 PM PDT 24
Peak memory 202064 kb
Host smart-5a8bce5f-1b11-4c2a-aff4-7753347e755b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625088788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_str
ess_all.625088788
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.792573466
Short name T84
Test name
Test status
Simulation time 152739824480 ps
CPU time 37.29 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:42 PM PDT 24
Peak memory 210424 kb
Host smart-86da8af7-dc4a-4eaa-80cd-ff6fad9c4daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792573466 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.792573466
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2083660169
Short name T58
Test name
Test status
Simulation time 1562861282815 ps
CPU time 42.96 seconds
Started Apr 02 01:03:04 PM PDT 24
Finished Apr 02 01:03:48 PM PDT 24
Peak memory 201980 kb
Host smart-da3f81ef-9c7c-4190-88a1-32800873dd00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083660169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.2083660169
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.568685043
Short name T237
Test name
Test status
Simulation time 54869483534 ps
CPU time 33.83 seconds
Started Apr 02 01:05:44 PM PDT 24
Finished Apr 02 01:06:18 PM PDT 24
Peak memory 202060 kb
Host smart-8a6666b7-0f9c-475f-ba05-540a602fda59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568685043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_wi
th_pre_cond.568685043
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.987135505
Short name T320
Test name
Test status
Simulation time 105455866785 ps
CPU time 144.68 seconds
Started Apr 02 01:05:42 PM PDT 24
Finished Apr 02 01:08:09 PM PDT 24
Peak memory 202196 kb
Host smart-826c5d62-804e-48a4-9fbc-4d43b395591d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987135505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_wi
th_pre_cond.987135505
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3490938
Short name T675
Test name
Test status
Simulation time 73547746457 ps
CPU time 50.29 seconds
Started Apr 02 01:05:42 PM PDT 24
Finished Apr 02 01:06:35 PM PDT 24
Peak memory 202092 kb
Host smart-2ea48d42-07f1-42db-b7ec-30b23116d37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_with
_pre_cond.3490938
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1273720926
Short name T766
Test name
Test status
Simulation time 81305720790 ps
CPU time 200.23 seconds
Started Apr 02 01:05:41 PM PDT 24
Finished Apr 02 01:09:02 PM PDT 24
Peak memory 202192 kb
Host smart-7d7a480b-fe36-4076-a773-a2f5dc0a5543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273720926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w
ith_pre_cond.1273720926
Directory /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2840142106
Short name T342
Test name
Test status
Simulation time 188999267868 ps
CPU time 134.04 seconds
Started Apr 02 01:05:49 PM PDT 24
Finished Apr 02 01:08:04 PM PDT 24
Peak memory 202172 kb
Host smart-18863098-4e6f-4769-935b-cf9b48a731e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840142106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.2840142106
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.2752676658
Short name T560
Test name
Test status
Simulation time 2020212435 ps
CPU time 3.26 seconds
Started Apr 02 01:03:17 PM PDT 24
Finished Apr 02 01:03:20 PM PDT 24
Peak memory 201996 kb
Host smart-da6107f2-992e-44f6-a0fb-6c18fb3e8754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752676658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.2752676658
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3263916950
Short name T206
Test name
Test status
Simulation time 3743152082 ps
CPU time 2.23 seconds
Started Apr 02 01:03:17 PM PDT 24
Finished Apr 02 01:03:19 PM PDT 24
Peak memory 202008 kb
Host smart-0a434ca6-3cae-4530-a1aa-4ea2365d352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263916950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.3263916950
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3840305919
Short name T177
Test name
Test status
Simulation time 94750701478 ps
CPU time 66.22 seconds
Started Apr 02 01:03:04 PM PDT 24
Finished Apr 02 01:04:10 PM PDT 24
Peak memory 202116 kb
Host smart-bfb7cdc9-0a12-40b8-bb2e-068df5063b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840305919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi
th_pre_cond.3840305919
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.500878815
Short name T198
Test name
Test status
Simulation time 2639159870 ps
CPU time 4.09 seconds
Started Apr 02 01:03:04 PM PDT 24
Finished Apr 02 01:03:08 PM PDT 24
Peak memory 201968 kb
Host smart-0bb16cf3-dd69-4a2f-9525-7e2e0b350990
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500878815 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_ec_pwr_on_rst.500878815
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2658344643
Short name T37
Test name
Test status
Simulation time 626562278335 ps
CPU time 816.17 seconds
Started Apr 02 01:03:07 PM PDT 24
Finished Apr 02 01:16:44 PM PDT 24
Peak memory 201964 kb
Host smart-1594b7d6-032a-47da-9e06-202bc4c36abe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658344643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2658344643
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.923831238
Short name T569
Test name
Test status
Simulation time 2635040130 ps
CPU time 2.3 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:03:18 PM PDT 24
Peak memory 201928 kb
Host smart-82ddd6ea-6af4-4dad-a738-1b706d4d04dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923831238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.923831238
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.794811285
Short name T600
Test name
Test status
Simulation time 2492524028 ps
CPU time 2.53 seconds
Started Apr 02 01:03:18 PM PDT 24
Finished Apr 02 01:03:20 PM PDT 24
Peak memory 201944 kb
Host smart-dff476c5-bdcf-42f6-ae5a-0e6e65aacf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794811285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.794811285
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.649304783
Short name T725
Test name
Test status
Simulation time 2043725115 ps
CPU time 1.84 seconds
Started Apr 02 01:03:06 PM PDT 24
Finished Apr 02 01:03:08 PM PDT 24
Peak memory 201812 kb
Host smart-d80c7be5-5842-47c1-b603-ad6d1f8264a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649304783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.649304783
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.303690269
Short name T647
Test name
Test status
Simulation time 2512246815 ps
CPU time 7.56 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:13 PM PDT 24
Peak memory 201824 kb
Host smart-9e77ce30-a59e-4651-be63-beefe2064b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303690269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.303690269
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.1031548849
Short name T428
Test name
Test status
Simulation time 2130669908 ps
CPU time 1.92 seconds
Started Apr 02 01:03:17 PM PDT 24
Finished Apr 02 01:03:19 PM PDT 24
Peak memory 201868 kb
Host smart-a959ee29-4071-4381-b209-d7a48489d04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031548849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1031548849
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.4293872293
Short name T593
Test name
Test status
Simulation time 10385914658 ps
CPU time 13.93 seconds
Started Apr 02 01:03:04 PM PDT 24
Finished Apr 02 01:03:18 PM PDT 24
Peak memory 202000 kb
Host smart-e19ac302-8403-4033-92c6-43cb7f4bd0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293872293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.4293872293
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1262860910
Short name T100
Test name
Test status
Simulation time 8425259190 ps
CPU time 8.05 seconds
Started Apr 02 01:03:04 PM PDT 24
Finished Apr 02 01:03:13 PM PDT 24
Peak memory 201924 kb
Host smart-a35f2670-2d89-440a-a250-f102ce5d1d9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262860910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.1262860910
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2537860703
Short name T650
Test name
Test status
Simulation time 24081254891 ps
CPU time 63.65 seconds
Started Apr 02 01:05:43 PM PDT 24
Finished Apr 02 01:06:48 PM PDT 24
Peak memory 202180 kb
Host smart-bd4a99ea-97e2-4a0e-854d-708f97d3b50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537860703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.2537860703
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.80008801
Short name T540
Test name
Test status
Simulation time 38834167325 ps
CPU time 17.54 seconds
Started Apr 02 01:05:47 PM PDT 24
Finished Apr 02 01:06:05 PM PDT 24
Peak memory 202144 kb
Host smart-37bcd9f3-72ad-4434-a464-e2a40a30a870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80008801 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_wit
h_pre_cond.80008801
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3102731594
Short name T311
Test name
Test status
Simulation time 113224263031 ps
CPU time 82.24 seconds
Started Apr 02 01:05:48 PM PDT 24
Finished Apr 02 01:07:11 PM PDT 24
Peak memory 202068 kb
Host smart-1bb1cc39-72e1-4844-901a-4dceadeee51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102731594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.3102731594
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3184810410
Short name T26
Test name
Test status
Simulation time 113500875313 ps
CPU time 77.89 seconds
Started Apr 02 01:05:49 PM PDT 24
Finished Apr 02 01:07:07 PM PDT 24
Peak memory 202172 kb
Host smart-df870fed-3f7c-4117-b09d-9241dd1cf2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184810410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.3184810410
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.516329124
Short name T107
Test name
Test status
Simulation time 23577489581 ps
CPU time 63.33 seconds
Started Apr 02 01:05:46 PM PDT 24
Finished Apr 02 01:06:50 PM PDT 24
Peak memory 202144 kb
Host smart-4b6c1ca0-1dd2-4406-af76-731b1caab06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516329124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_wi
th_pre_cond.516329124
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2583663201
Short name T633
Test name
Test status
Simulation time 125024089240 ps
CPU time 330.54 seconds
Started Apr 02 01:05:50 PM PDT 24
Finished Apr 02 01:11:21 PM PDT 24
Peak memory 202204 kb
Host smart-277055b6-e64e-448e-a049-8ecdd807cac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583663201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.2583663201
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1940205952
Short name T516
Test name
Test status
Simulation time 21350272263 ps
CPU time 14.65 seconds
Started Apr 02 01:05:48 PM PDT 24
Finished Apr 02 01:06:03 PM PDT 24
Peak memory 202072 kb
Host smart-cea36f88-6057-423c-a00f-ad1e6e4af404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940205952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.1940205952
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4164124618
Short name T313
Test name
Test status
Simulation time 101215247783 ps
CPU time 69.54 seconds
Started Apr 02 01:05:47 PM PDT 24
Finished Apr 02 01:06:57 PM PDT 24
Peak memory 202024 kb
Host smart-c4d2b576-431d-4be1-bbfa-1ddb21c38c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164124618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.4164124618
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.1285091832
Short name T135
Test name
Test status
Simulation time 2011768367 ps
CPU time 5.73 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:03:22 PM PDT 24
Peak memory 201972 kb
Host smart-cb8130a0-dc4a-4f03-ab64-2fa807e41e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285091832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.1285091832
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1152065225
Short name T51
Test name
Test status
Simulation time 3372228491 ps
CPU time 10.14 seconds
Started Apr 02 01:03:09 PM PDT 24
Finished Apr 02 01:03:19 PM PDT 24
Peak memory 201908 kb
Host smart-d215e7e3-00ef-4baa-8ac2-7d12a651eee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152065225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1152065225
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.1583573735
Short name T246
Test name
Test status
Simulation time 30520145152 ps
CPU time 81.07 seconds
Started Apr 02 01:03:12 PM PDT 24
Finished Apr 02 01:04:33 PM PDT 24
Peak memory 202072 kb
Host smart-f058ec1d-dd38-419a-a6bb-951d00bd8115
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583573735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.1583573735
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.4149335197
Short name T308
Test name
Test status
Simulation time 88835661555 ps
CPU time 113.23 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:05:09 PM PDT 24
Peak memory 202116 kb
Host smart-84d79cbd-23c4-46d5-8178-356e414f66e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149335197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.4149335197
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1523431964
Short name T503
Test name
Test status
Simulation time 3015417177 ps
CPU time 2.55 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:08 PM PDT 24
Peak memory 201936 kb
Host smart-0234f106-a860-4834-b614-94865a79e261
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523431964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.1523431964
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.598020860
Short name T158
Test name
Test status
Simulation time 4249740323 ps
CPU time 12.02 seconds
Started Apr 02 01:03:11 PM PDT 24
Finished Apr 02 01:03:23 PM PDT 24
Peak memory 201896 kb
Host smart-57a52565-92a3-46c2-827f-44004002dc8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598020860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl
_edge_detect.598020860
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.928128698
Short name T262
Test name
Test status
Simulation time 2620965841 ps
CPU time 2.46 seconds
Started Apr 02 01:03:05 PM PDT 24
Finished Apr 02 01:03:07 PM PDT 24
Peak memory 201752 kb
Host smart-2266abab-b39e-4c10-aa71-de4a47eac013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928128698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.928128698
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.719687532
Short name T644
Test name
Test status
Simulation time 2459791910 ps
CPU time 7.57 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:03:24 PM PDT 24
Peak memory 201944 kb
Host smart-edeb5f19-3f4b-4009-a8f8-d803ea92d65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719687532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.719687532
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2875683451
Short name T229
Test name
Test status
Simulation time 2156174669 ps
CPU time 6.17 seconds
Started Apr 02 01:03:06 PM PDT 24
Finished Apr 02 01:03:12 PM PDT 24
Peak memory 201944 kb
Host smart-27e47b88-981c-4238-9547-e613cc3ec702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875683451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.2875683451
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3007829650
Short name T448
Test name
Test status
Simulation time 2536864128 ps
CPU time 2.45 seconds
Started Apr 02 01:03:06 PM PDT 24
Finished Apr 02 01:03:09 PM PDT 24
Peak memory 201856 kb
Host smart-321e91aa-ee4a-4239-bc2a-fdfae9580322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007829650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.3007829650
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.2506487015
Short name T764
Test name
Test status
Simulation time 2125078251 ps
CPU time 2 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:03:18 PM PDT 24
Peak memory 201868 kb
Host smart-37ff15fc-71ec-43a8-b49a-429ee304f38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506487015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.2506487015
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.3425499549
Short name T420
Test name
Test status
Simulation time 8833986395 ps
CPU time 22.6 seconds
Started Apr 02 01:03:27 PM PDT 24
Finished Apr 02 01:03:50 PM PDT 24
Peak memory 201888 kb
Host smart-b687798e-2046-4393-9d37-b6e1f31a927b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425499549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.3425499549
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4130756467
Short name T40
Test name
Test status
Simulation time 41272420676 ps
CPU time 52.39 seconds
Started Apr 02 01:03:08 PM PDT 24
Finished Apr 02 01:04:01 PM PDT 24
Peak memory 210584 kb
Host smart-4848f48c-799e-430e-9da4-035c9f15865e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130756467 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.4130756467
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.130818829
Short name T61
Test name
Test status
Simulation time 9719055461 ps
CPU time 2.61 seconds
Started Apr 02 01:03:11 PM PDT 24
Finished Apr 02 01:03:14 PM PDT 24
Peak memory 201948 kb
Host smart-7310d8a4-1468-4297-878d-aaaa6139e544
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130818829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_ultra_low_pwr.130818829
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1179348595
Short name T517
Test name
Test status
Simulation time 25355334297 ps
CPU time 18 seconds
Started Apr 02 01:05:45 PM PDT 24
Finished Apr 02 01:06:03 PM PDT 24
Peak memory 202148 kb
Host smart-6e93dca4-25ba-4d26-b482-41427a2c2c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179348595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.1179348595
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3540596006
Short name T325
Test name
Test status
Simulation time 85045397888 ps
CPU time 32.49 seconds
Started Apr 02 01:05:48 PM PDT 24
Finished Apr 02 01:06:20 PM PDT 24
Peak memory 202160 kb
Host smart-7a3dc1ae-ab1a-4fb0-9915-89b16a7b1be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540596006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.3540596006
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3326994283
Short name T455
Test name
Test status
Simulation time 26837682175 ps
CPU time 32.66 seconds
Started Apr 02 01:05:46 PM PDT 24
Finished Apr 02 01:06:19 PM PDT 24
Peak memory 202176 kb
Host smart-7bbf7188-c434-4da7-a50e-69dcd9b07a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326994283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.3326994283
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1184017198
Short name T440
Test name
Test status
Simulation time 26832877598 ps
CPU time 72.18 seconds
Started Apr 02 01:05:46 PM PDT 24
Finished Apr 02 01:06:59 PM PDT 24
Peak memory 202180 kb
Host smart-a08a6e81-ccca-4c5b-b67e-37d244b150c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184017198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.1184017198
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.388031390
Short name T310
Test name
Test status
Simulation time 56907887887 ps
CPU time 145.41 seconds
Started Apr 02 01:05:48 PM PDT 24
Finished Apr 02 01:08:14 PM PDT 24
Peak memory 202200 kb
Host smart-5c7c817b-2a27-4f7b-8b7f-54b1457047da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388031390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_wi
th_pre_cond.388031390
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3015288455
Short name T230
Test name
Test status
Simulation time 103521365609 ps
CPU time 36.71 seconds
Started Apr 02 01:05:47 PM PDT 24
Finished Apr 02 01:06:24 PM PDT 24
Peak memory 202176 kb
Host smart-d1d4c291-b147-46a2-ae58-8962417448c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015288455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.3015288455
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.1056645517
Short name T493
Test name
Test status
Simulation time 2052957739 ps
CPU time 1.78 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:03:17 PM PDT 24
Peak memory 201968 kb
Host smart-0ca62ab7-940c-4998-9ba5-eac8810cb0f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056645517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.1056645517
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2309583285
Short name T576
Test name
Test status
Simulation time 3903522799 ps
CPU time 4.83 seconds
Started Apr 02 01:03:14 PM PDT 24
Finished Apr 02 01:03:19 PM PDT 24
Peak memory 201852 kb
Host smart-acebe6f5-eb78-4591-906f-39013409c023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309583285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.2309583285
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.2083552208
Short name T241
Test name
Test status
Simulation time 29057004848 ps
CPU time 74 seconds
Started Apr 02 01:03:14 PM PDT 24
Finished Apr 02 01:04:28 PM PDT 24
Peak memory 201948 kb
Host smart-bc905298-1788-4a07-8b3c-96fd63bc6090
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083552208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.2083552208
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2393709364
Short name T106
Test name
Test status
Simulation time 51082448288 ps
CPU time 32.36 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:03:47 PM PDT 24
Peak memory 202084 kb
Host smart-552ca248-46c9-4149-a172-ea7b6010b979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393709364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.2393709364
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2058361384
Short name T707
Test name
Test status
Simulation time 3238908225 ps
CPU time 2.65 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:03:18 PM PDT 24
Peak memory 201952 kb
Host smart-29d6410b-e04d-49b4-9137-f50826de7491
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058361384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.2058361384
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1575413538
Short name T530
Test name
Test status
Simulation time 2628992872 ps
CPU time 2.43 seconds
Started Apr 02 01:03:16 PM PDT 24
Finished Apr 02 01:03:19 PM PDT 24
Peak memory 201940 kb
Host smart-bd72e2f5-335f-4780-8fdc-33b2181c3bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575413538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.1575413538
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1209317199
Short name T549
Test name
Test status
Simulation time 2521884226 ps
CPU time 1.36 seconds
Started Apr 02 01:03:13 PM PDT 24
Finished Apr 02 01:03:14 PM PDT 24
Peak memory 201908 kb
Host smart-49e94c33-7ced-460e-9263-09d5068862a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209317199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.1209317199
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1953213267
Short name T408
Test name
Test status
Simulation time 2262983961 ps
CPU time 2.12 seconds
Started Apr 02 01:03:27 PM PDT 24
Finished Apr 02 01:03:29 PM PDT 24
Peak memory 201880 kb
Host smart-9301c90a-ddc9-42a0-b41c-8443b9c491a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953213267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1953213267
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2746045421
Short name T639
Test name
Test status
Simulation time 2520969588 ps
CPU time 4.1 seconds
Started Apr 02 01:03:25 PM PDT 24
Finished Apr 02 01:03:30 PM PDT 24
Peak memory 201888 kb
Host smart-d49602ff-d41e-422e-8ec5-83507a55902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746045421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2746045421
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.1251619729
Short name T631
Test name
Test status
Simulation time 2112417509 ps
CPU time 6.09 seconds
Started Apr 02 01:03:14 PM PDT 24
Finished Apr 02 01:03:21 PM PDT 24
Peak memory 201828 kb
Host smart-caa05ba5-93c9-49e6-b251-cf719c20c90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251619729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.1251619729
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.2726689477
Short name T114
Test name
Test status
Simulation time 142652854646 ps
CPU time 349.56 seconds
Started Apr 02 01:03:13 PM PDT 24
Finished Apr 02 01:09:03 PM PDT 24
Peak memory 201988 kb
Host smart-db876472-3018-400d-a059-de7a6f253231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726689477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.2726689477
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1408362665
Short name T776
Test name
Test status
Simulation time 7263854202 ps
CPU time 4.22 seconds
Started Apr 02 01:03:15 PM PDT 24
Finished Apr 02 01:03:19 PM PDT 24
Peak memory 201856 kb
Host smart-440f5d2c-1c7c-4f61-abc3-9a3e1e7da1a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408362665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ultra_low_pwr.1408362665
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2538220963
Short name T32
Test name
Test status
Simulation time 90545353020 ps
CPU time 249.48 seconds
Started Apr 02 01:05:49 PM PDT 24
Finished Apr 02 01:09:59 PM PDT 24
Peak memory 202180 kb
Host smart-14ad370f-28d5-43aa-a5f5-c61cd4eb5cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538220963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.2538220963
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3120776198
Short name T410
Test name
Test status
Simulation time 142205407638 ps
CPU time 177.99 seconds
Started Apr 02 01:05:51 PM PDT 24
Finished Apr 02 01:08:49 PM PDT 24
Peak memory 202020 kb
Host smart-d5bc4f0e-dcfd-4056-9941-3b20f83c9cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120776198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.3120776198
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1731742249
Short name T787
Test name
Test status
Simulation time 36204383899 ps
CPU time 100.17 seconds
Started Apr 02 01:05:51 PM PDT 24
Finished Apr 02 01:07:31 PM PDT 24
Peak memory 202160 kb
Host smart-a0f2722f-bd54-4bb5-b231-8e013cb7604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731742249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.1731742249
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.627982692
Short name T686
Test name
Test status
Simulation time 38529265208 ps
CPU time 21.49 seconds
Started Apr 02 01:05:52 PM PDT 24
Finished Apr 02 01:06:14 PM PDT 24
Peak memory 202188 kb
Host smart-2a2d3c07-e3fa-4a86-ae62-768303b2c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627982692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_wi
th_pre_cond.627982692
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2830984323
Short name T122
Test name
Test status
Simulation time 45939146019 ps
CPU time 31.89 seconds
Started Apr 02 01:05:53 PM PDT 24
Finished Apr 02 01:06:25 PM PDT 24
Peak memory 202128 kb
Host smart-f0ef18fe-b548-4901-8f09-23372190cbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830984323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.2830984323
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.878469671
Short name T423
Test name
Test status
Simulation time 22078770748 ps
CPU time 61.19 seconds
Started Apr 02 01:05:49 PM PDT 24
Finished Apr 02 01:06:51 PM PDT 24
Peak memory 202120 kb
Host smart-b270c673-2f85-46a3-8d41-3434421b3155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878469671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_wi
th_pre_cond.878469671
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.290872547
Short name T522
Test name
Test status
Simulation time 23838004561 ps
CPU time 31 seconds
Started Apr 02 01:05:51 PM PDT 24
Finished Apr 02 01:06:22 PM PDT 24
Peak memory 202136 kb
Host smart-e86c9f22-eb3b-4b55-ad9d-9faf3678ccc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290872547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_wi
th_pre_cond.290872547
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3766224949
Short name T427
Test name
Test status
Simulation time 39006092209 ps
CPU time 97 seconds
Started Apr 02 01:05:50 PM PDT 24
Finished Apr 02 01:07:27 PM PDT 24
Peak memory 202196 kb
Host smart-faef6ab2-6b1c-4d1d-8f4f-b26565c72715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766224949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.3766224949
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3967478681
Short name T415
Test name
Test status
Simulation time 23856873891 ps
CPU time 17.37 seconds
Started Apr 02 01:05:49 PM PDT 24
Finished Apr 02 01:06:07 PM PDT 24
Peak memory 202184 kb
Host smart-ac6b2f41-875d-4242-a573-7a34566cdb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967478681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.3967478681
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3783942511
Short name T739
Test name
Test status
Simulation time 63837041714 ps
CPU time 86.07 seconds
Started Apr 02 01:05:49 PM PDT 24
Finished Apr 02 01:07:15 PM PDT 24
Peak memory 202072 kb
Host smart-9ddd87c0-532c-4e3a-9473-e951383eb331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783942511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.3783942511
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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