Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T25,T26,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T25,T26,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T25,T26,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T36
1	0	Covered	T1,T2,T12
1	1	Covered	T25,T26,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T36
0	1	Covered	T87,T108,T112
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T49
0	1	Covered	T25,T26,T36
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T26,T49
1	-	Covered	T25,T26,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T36
DetectSt	168	Covered	T25,T26,T36
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T25,T26,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T26,T36
DebounceSt->IdleSt	163	Covered	T36,T53,T54
DetectSt->IdleSt	186	Covered	T87,T108,T112
DetectSt->StableSt	191	Covered	T25,T26,T36
IdleSt->DebounceSt	148	Covered	T25,T26,T36
StableSt->IdleSt	206	Covered	T25,T26,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T26,T36
0	1	Covered	T25,T26,T36
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T36
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T26,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T53,T96
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T36
DetectSt	-	-	-	-	1	-	-	Covered	T87,T108,T112
DetectSt	-	-	-	-	0	1	-	Covered	T25,T26,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T25,T26,T36
StableSt	-	-	-	-	-	-	0	Covered	T25,T26,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	273	0	0
CntIncr_A	8545490	312327	0	0
CntNoWrap_A	8545490	7910341	0	0
DetectStDropOut_A	8545490	4	0	0
DetectedOut_A	8545490	858	0	0
DetectedPulseOut_A	8545490	123	0	0
DisabledIdleSt_A	8545490	7591937	0	0
DisabledNoDetection_A	8545490	7594255	0	0
EnterDebounceSt_A	8545490	151	0	0
EnterDetectSt_A	8545490	127	0	0
EnterStableSt_A	8545490	123	0	0
PulseIsPulse_A	8545490	123	0	0
StayInStableSt	8545490	735	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8545490	6782	0	0
gen_low_level_sva.LowLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	122	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	273	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	2	0	0
T26	602	2	0	0
T36	0	3	0	0
T47	6042	0	0	0
T49	0	4	0	0
T51	0	4	0	0
T52	0	6	0	0
T53	0	1	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T80	0	2	0	0
T95	0	2	0	0
T96	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	312327	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	11	0	0
T26	602	18	0	0
T36	0	36	0	0
T47	6042	0	0	0
T49	0	127	0	0
T51	0	89	0	0
T52	0	174	0	0
T53	0	13	0	0
T54	0	1267	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T80	0	10	0	0
T95	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910341	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	4	0	0
T87	10827	1	0	0
T108	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T119	503	0	0	0
T120	402	0	0	0
T121	16323	0	0	0
T122	9123	0	0	0
T123	20616	0	0	0
T124	24311	0	0	0
T125	111255	0	0	0
T126	350124	0	0	0
T127	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	858	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	7	0	0
T26	602	2	0	0
T36	0	1	0	0
T47	6042	0	0	0
T49	0	19	0	0
T51	0	20	0	0
T52	0	19	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T80	0	1	0	0
T95	0	5	0	0
T96	0	5	0	0
T130	0	22	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	123	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	1	0	0
T26	602	1	0	0
T36	0	1	0	0
T47	6042	0	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T130	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7591937	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7594255	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	151	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	1	0	0
T26	602	1	0	0
T36	0	2	0	0
T47	6042	0	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T80	0	1	0	0
T95	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	127	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	1	0	0
T26	602	1	0	0
T36	0	1	0	0
T47	6042	0	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T130	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	123	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	1	0	0
T26	602	1	0	0
T36	0	1	0	0
T47	6042	0	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T130	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	123	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	1	0	0
T26	602	1	0	0
T36	0	1	0	0
T47	6042	0	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T130	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	735	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	6	0	0
T26	602	1	0	0
T47	6042	0	0	0
T49	0	17	0	0
T51	0	18	0	0
T52	0	16	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T95	0	4	0	0
T96	0	4	0	0
T130	0	19	0	0
T133	0	12	0	0
T134	0	14	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6782	0	0
T1	943	1	0	0
T2	6285	17	0	0
T3	75299	56	0	0
T5	17751	28	0	0
T6	0	7	0	0
T12	613	2	0	0
T13	522	7	0	0
T14	1938	4	0	0
T15	27245	4	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	122	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T8	1170	0	0	0
T25	700	1	0	0
T26	602	1	0	0
T36	0	1	0	0
T47	6042	0	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T130	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T3,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T12
1	1	Covered	T3,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T11,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Unreachable
1	0	Covered	T3,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T8
DetectSt	168	Covered	T3,T6,T8
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T8
DebounceSt->IdleSt	163	Covered	T80,T82,T83
DetectSt->IdleSt	186	Covered	T11,T82,T83
DetectSt->StableSt	191	Covered	T3,T6,T8
IdleSt->DebounceSt	148	Covered	T3,T6,T8
StableSt->IdleSt	206	Covered	T3,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T80,T82,T83
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T11,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	204	0	0
CntIncr_A	8545490	198620	0	0
CntNoWrap_A	8545490	7910410	0	0
DetectStDropOut_A	8545490	25	0	0
DetectedOut_A	8545490	299549	0	0
DetectedPulseOut_A	8545490	42	0	0
DisabledIdleSt_A	8545490	6462096	0	0
DisabledNoDetection_A	8545490	6464469	0	0
EnterDebounceSt_A	8545490	137	0	0
EnterDetectSt_A	8545490	67	0	0
EnterStableSt_A	8545490	42	0	0
PulseIsPulse_A	8545490	42	0	0
StayInStableSt	8545490	299507	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8545490	6782	0	0
gen_low_level_sva.LowLevelEvent_A	8545490	7912987	0	0
gen_sticky_sva.StableStDropOut_A	8545490	362352	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	204	0	0
T3	75299	2	0	0
T5	17751	0	0	0
T6	1738	2	0	0
T7	29126	0	0	0
T8	0	2	0	0
T11	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	4	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	5	0	0
T83	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	198620	0	0
T3	75299	13	0	0
T5	17751	0	0	0
T6	1738	81	0	0
T7	29126	0	0	0
T8	0	58	0	0
T11	0	71	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	110	0	0
T79	0	12	0	0
T80	0	72	0	0
T81	0	16	0	0
T82	0	105	0	0
T83	0	310	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910410	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69577	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	25	0	0
T11	1048	1	0	0
T27	6254	0	0	0
T32	1419	0	0	0
T36	20490	0	0	0
T75	525	0	0	0
T82	0	2	0	0
T83	0	4	0	0
T90	0	2	0	0
T131	448	0	0	0
T132	407	0	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	414	0	0	0
T143	421	0	0	0
T144	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	299549	0	0
T3	75299	67	0	0
T5	17751	0	0	0
T6	1738	284	0	0
T7	29126	0	0	0
T8	0	149	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	68	0	0
T79	0	7	0	0
T81	0	81	0	0
T83	0	779	0	0
T90	0	1	0	0
T94	0	602	0	0
T104	0	19867	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	42	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T90	0	1	0	0
T94	0	1	0	0
T104	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6462096	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69342	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6464469	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69372	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	137	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0
T83	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	67	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T81	0	1	0	0
T82	0	2	0	0
T83	0	5	0	0
T94	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	42	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T90	0	1	0	0
T94	0	1	0	0
T104	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	42	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T90	0	1	0	0
T94	0	1	0	0
T104	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	299507	0	0
T3	75299	66	0	0
T5	17751	0	0	0
T6	1738	283	0	0
T7	29126	0	0	0
T8	0	148	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	66	0	0
T79	0	6	0	0
T81	0	80	0	0
T83	0	778	0	0
T92	0	738	0	0
T94	0	601	0	0
T104	0	19865	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6782	0	0
T1	943	1	0	0
T2	6285	17	0	0
T3	75299	56	0	0
T5	17751	28	0	0
T6	0	7	0	0
T12	613	2	0	0
T13	522	7	0	0
T14	1938	4	0	0
T15	27245	4	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	362352	0	0
T3	75299	130	0	0
T5	17751	0	0	0
T6	1738	180	0	0
T7	29126	0	0	0
T8	0	73	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	50	0	0
T79	0	53434	0	0
T81	0	612	0	0
T83	0	66	0	0
T90	0	120	0	0
T94	0	257	0	0
T104	0	166	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T3,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T12
1	1	Covered	T3,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Unreachable
1	0	Covered	T3,T6,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T8
DetectSt	168	Covered	T3,T6,T8
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T8
DebounceSt->IdleSt	163	Covered	T11,T79,T82
DetectSt->IdleSt	186	Covered	T92,T93
DetectSt->StableSt	191	Covered	T3,T6,T8
IdleSt->DebounceSt	148	Covered	T3,T6,T8
StableSt->IdleSt	206	Covered	T3,T6,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T79,T82
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T8
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	170	0	0
CntIncr_A	8545490	251183	0	0
CntNoWrap_A	8545490	7910444	0	0
DetectStDropOut_A	8545490	4	0	0
DetectedOut_A	8545490	300690	0	0
DetectedPulseOut_A	8545490	60	0	0
DisabledIdleSt_A	8545490	6462096	0	0
DisabledNoDetection_A	8545490	6464469	0	0
EnterDebounceSt_A	8545490	106	0	0
EnterDetectSt_A	8545490	64	0	0
EnterStableSt_A	8545490	60	0	0
PulseIsPulse_A	8545490	60	0	0
StayInStableSt	8545490	300630	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_sticky_sva.StableStDropOut_A	8545490	674584	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	170	0	0
T3	75299	2	0	0
T5	17751	0	0	0
T6	1738	2	0	0
T7	29126	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	4	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	3	0	0
T83	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	251183	0	0
T3	75299	19	0	0
T5	17751	0	0	0
T6	1738	89	0	0
T7	29126	0	0	0
T8	0	68	0	0
T11	0	52	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	38	0	0
T79	0	53423	0	0
T80	0	83	0	0
T81	0	99	0	0
T82	0	75	0	0
T83	0	138	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910444	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69577	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	4	0	0
T92	2572	3	0	0
T93	0	1	0	0
T145	524	0	0	0
T146	427	0	0	0
T147	527	0	0	0
T148	715	0	0	0
T149	5367	0	0	0
T150	697	0	0	0
T151	597	0	0	0
T152	522	0	0	0
T153	280785	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	300690	0	0
T3	75299	89	0	0
T5	17751	0	0	0
T6	1738	408	0	0
T7	29126	0	0	0
T8	0	187	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	31	0	0
T80	0	35	0	0
T81	0	533	0	0
T83	0	488	0	0
T90	0	274	0	0
T91	0	82	0	0
T94	0	283	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	60	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T90	0	1	0	0
T91	0	3	0	0
T94	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6462096	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69342	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6464469	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69372	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	106	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0
T83	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	64	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T90	0	1	0	0
T91	0	3	0	0
T94	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	60	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T90	0	1	0	0
T91	0	3	0	0
T94	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	60	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0
T83	0	1	0	0
T90	0	1	0	0
T91	0	3	0	0
T94	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	300630	0	0
T3	75299	88	0	0
T5	17751	0	0	0
T6	1738	407	0	0
T7	29126	0	0	0
T8	0	186	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	29	0	0
T80	0	34	0	0
T81	0	532	0	0
T83	0	487	0	0
T90	0	273	0	0
T91	0	79	0	0
T94	0	282	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	674584	0	0
T3	75299	117	0	0
T5	17751	0	0	0
T6	1738	49	0	0
T7	29126	0	0	0
T8	0	33	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	161	0	0
T80	0	96	0	0
T81	0	79	0	0
T83	0	384	0	0
T90	0	58	0	0
T91	0	950	0	0
T94	0	621	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T3,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T12
1	1	Covered	T3,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T8,T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Unreachable
1	0	Covered	T3,T6,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T8
DetectSt	168	Covered	T3,T6,T8
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T8
DebounceSt->IdleSt	163	Covered	T8,T94,T87
DetectSt->IdleSt	186	Covered	T8,T90,T91
DetectSt->StableSt	191	Covered	T3,T6,T11
IdleSt->DebounceSt	148	Covered	T3,T6,T8
StableSt->IdleSt	206	Covered	T3,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T8
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T94,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T90,T91
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	191	0	0
CntIncr_A	8545490	123485	0	0
CntNoWrap_A	8545490	7910423	0	0
DetectStDropOut_A	8545490	20	0	0
DetectedOut_A	8545490	323716	0	0
DetectedPulseOut_A	8545490	50	0	0
DisabledIdleSt_A	8545490	6462096	0	0
DisabledNoDetection_A	8545490	6464469	0	0
EnterDebounceSt_A	8545490	121	0	0
EnterDetectSt_A	8545490	70	0	0
EnterStableSt_A	8545490	50	0	0
PulseIsPulse_A	8545490	50	0	0
StayInStableSt	8545490	323666	0	0
gen_high_event_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_sticky_sva.StableStDropOut_A	8545490	955881	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	191	0	0
T3	75299	2	0	0
T5	17751	0	0	0
T6	1738	2	0	0
T7	29126	0	0	0
T8	0	3	0	0
T11	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	4	0	0
T79	0	2	0	0
T80	0	2	0	0
T81	0	2	0	0
T82	0	2	0	0
T83	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	123485	0	0
T3	75299	20	0	0
T5	17751	0	0	0
T6	1738	53	0	0
T7	29126	0	0	0
T8	0	160	0	0
T11	0	34	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	116	0	0
T79	0	32	0	0
T80	0	71	0	0
T81	0	50	0	0
T82	0	60	0	0
T83	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910423	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69577	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	20	0	0
T8	1170	1	0	0
T9	18861	0	0	0
T10	483	0	0	0
T11	1048	0	0	0
T36	20490	0	0	0
T72	507	0	0	0
T73	522	0	0	0
T74	524	0	0	0
T90	0	1	0	0
T91	0	5	0	0
T93	0	1	0	0
T131	448	0	0	0
T135	430	0	0	0
T139	0	1	0	0
T154	0	4	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	323716	0	0
T3	75299	122	0	0
T5	17751	0	0	0
T6	1738	221	0	0
T7	29126	0	0	0
T11	0	22	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	15	0	0
T79	0	25	0	0
T80	0	52	0	0
T81	0	313	0	0
T82	0	285	0	0
T83	0	404	0	0
T90	0	100	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	50	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T11	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T90	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6462096	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69342	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6464469	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69372	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	121	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	70	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	50	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T11	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T90	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	50	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T6	1738	1	0	0
T7	29126	0	0	0
T11	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	2	0	0
T90	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	323666	0	0
T3	75299	121	0	0
T5	17751	0	0	0
T6	1738	220	0	0
T7	29126	0	0	0
T11	0	21	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	13	0	0
T79	0	24	0	0
T80	0	51	0	0
T81	0	312	0	0
T82	0	284	0	0
T83	0	402	0	0
T90	0	99	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	955881	0	0
T3	75299	85	0	0
T5	17751	0	0	0
T6	1738	284	0	0
T7	29126	0	0	0
T11	0	54	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T55	401	0	0	0
T56	570	0	0	0
T61	0	127	0	0
T79	0	53410	0	0
T80	0	93	0	0
T81	0	365	0	0
T82	0	113	0	0
T83	0	1029	0	0
T90	0	96	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T2,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T36
0	1	Covered	T1,T158,T102
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T36
1	-	Covered	T1,T158,T102

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T36
DetectSt	168	Covered	T1,T2,T36
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T2,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T36
DebounceSt->IdleSt	163	Covered	T84,T159
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T2,T36
IdleSt->DebounceSt	148	Covered	T1,T2,T36
StableSt->IdleSt	206	Covered	T1,T2,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T36
0	1	Covered	T1,T2,T36
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T36
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T159
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T158,T102
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	68	0	0
CntIncr_A	8545490	52621	0	0
CntNoWrap_A	8545490	7910546	0	0
DetectStDropOut_A	8545490	0	0	0
DetectedOut_A	8545490	2339	0	0
DetectedPulseOut_A	8545490	33	0	0
DisabledIdleSt_A	8545490	7544529	0	0
DisabledNoDetection_A	8545490	7546855	0	0
EnterDebounceSt_A	8545490	35	0	0
EnterDetectSt_A	8545490	33	0	0
EnterStableSt_A	8545490	33	0	0
PulseIsPulse_A	8545490	33	0	0
StayInStableSt	8545490	2284	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	68	0	0
T1	943	2	0	0
T2	6285	2	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T83	0	4	0	0
T102	0	2	0	0
T130	0	2	0	0
T158	0	4	0	0
T160	0	2	0	0
T161	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	52621	0	0
T1	943	67	0	0
T2	6285	27	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	90	0	0
T39	0	49	0	0
T83	0	152	0	0
T102	0	46	0	0
T130	0	27	0	0
T158	0	164	0	0
T160	0	71	0	0
T161	0	126	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910546	0	0
T1	943	540	0	0
T2	6285	1341	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2339	0	0
T1	943	56	0	0
T2	6285	37	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	40	0	0
T39	0	88	0	0
T83	0	237	0	0
T102	0	15	0	0
T130	0	51	0	0
T158	0	296	0	0
T160	0	112	0	0
T161	0	171	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	33	0	0
T1	943	1	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T83	0	2	0	0
T102	0	1	0	0
T130	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7544529	0	0
T1	943	4	0	0
T2	6285	1241	0	0
T3	75299	37796	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7546855	0	0
T1	943	4	0	0
T2	6285	1251	0	0
T3	75299	37825	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	35	0	0
T1	943	1	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T83	0	2	0	0
T102	0	1	0	0
T130	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	33	0	0
T1	943	1	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T83	0	2	0	0
T102	0	1	0	0
T130	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	33	0	0
T1	943	1	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T83	0	2	0	0
T102	0	1	0	0
T130	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	33	0	0
T1	943	1	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T83	0	2	0	0
T102	0	1	0	0
T130	0	1	0	0
T158	0	2	0	0
T160	0	1	0	0
T161	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2284	0	0
T1	943	55	0	0
T2	6285	35	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	38	0	0
T39	0	86	0	0
T83	0	234	0	0
T102	0	14	0	0
T130	0	49	0	0
T158	0	293	0	0
T160	0	111	0	0
T161	0	168	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	10	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T83	0	1	0	0
T102	0	1	0	0
T105	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0
T163	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T3,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T3,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T36
1	0	Covered	T1,T2,T13
1	1	Covered	T2,T3,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T36
0	1	Covered	T164
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T36
0	1	Covered	T36,T37,T43
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T36
1	-	Covered	T36,T37,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T36
DetectSt	168	Covered	T2,T3,T36
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T3,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T36
DebounceSt->IdleSt	163	Covered	T84,T165,T156
DetectSt->IdleSt	186	Covered	T166,T164
DetectSt->StableSt	191	Covered	T2,T3,T36
IdleSt->DebounceSt	148	Covered	T2,T3,T36
StableSt->IdleSt	206	Covered	T2,T3,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T36
0	1	Covered	T2,T3,T36
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T36
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T165
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T36
DetectSt	-	-	-	-	1	-	-	Covered	T164
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T37,T43
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	96	0	0
CntIncr_A	8545490	114352	0	0
CntNoWrap_A	8545490	7910518	0	0
DetectStDropOut_A	8545490	1	0	0
DetectedOut_A	8545490	155611	0	0
DetectedPulseOut_A	8545490	46	0	0
DisabledIdleSt_A	8545490	7439539	0	0
DisabledNoDetection_A	8545490	7441870	0	0
EnterDebounceSt_A	8545490	51	0	0
EnterDetectSt_A	8545490	47	0	0
EnterStableSt_A	8545490	46	0	0
PulseIsPulse_A	8545490	46	0	0
StayInStableSt	8545490	155550	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8545490	2497	0	0
gen_low_level_sva.LowLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	96	0	0
T2	6285	2	0	0
T3	75299	2	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T38	0	4	0	0
T39	0	2	0	0
T40	0	4	0	0
T43	0	2	0	0
T44	0	2	0	0
T130	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	114352	0	0
T2	6285	78	0	0
T3	75299	27892	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T36	0	90	0	0
T37	0	110	0	0
T38	0	20	0	0
T39	0	49	0	0
T40	0	164	0	0
T43	0	36	0	0
T44	0	35	0	0
T130	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910518	0	0
T1	943	542	0	0
T2	6285	1341	0	0
T3	75299	69577	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1	0	0
T164	14613	1	0	0
T167	649	0	0	0
T168	422	0	0	0
T169	410	0	0	0
T170	450	0	0	0
T171	502	0	0	0
T172	495	0	0	0
T173	26390	0	0	0
T174	27286	0	0	0
T175	9900	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	155611	0	0
T2	6285	43	0	0
T3	75299	3885	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T36	0	208	0	0
T37	0	145	0	0
T38	0	109	0	0
T39	0	88	0	0
T40	0	333	0	0
T43	0	40	0	0
T44	0	109	0	0
T130	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	46	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T130	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7439539	0	0
T1	943	542	0	0
T2	6285	1217	0	0
T3	75299	37796	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7441870	0	0
T1	943	543	0	0
T2	6285	1227	0	0
T3	75299	37825	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	51	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T130	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	47	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T130	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	46	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T130	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	46	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T130	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	155550	0	0
T2	6285	41	0	0
T3	75299	3883	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T36	0	207	0	0
T37	0	142	0	0
T38	0	106	0	0
T39	0	87	0	0
T40	0	330	0	0
T43	0	39	0	0
T44	0	108	0	0
T130	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2497	0	0
T1	943	2	0	0
T2	6285	13	0	0
T3	75299	29	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	5	0	0
T14	1938	6	0	0
T15	27245	5	0	0
T16	884	0	0	0
T17	405	0	0	0
T72	0	7	0	0
T73	0	6	0	0
T74	0	7	0	0
T135	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	30	0	0
T27	6254	0	0	0
T32	1419	0	0	0
T36	20490	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T75	525	0	0	0
T83	0	2	0	0
T130	0	1	0	0
T132	407	0	0	0
T142	414	0	0	0
T143	421	0	0	0
T144	522	0	0	0
T176	0	1	0	0
T177	422	0	0	0
T178	524	0	0	0