Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.35	100.00	96.30		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	91.56	95.65	90.48		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	91.64	95.65	90.48		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
91.64	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
91.56	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T3,T5

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T3,T5

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T14,T15
1	1	Covered	T2,T3,T5

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T3,T47,T33
1	0	Covered	T84,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T3,T5,T7
1	0	Covered	T84,T85,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T5,T7
1	-	Covered	T3,T5,T7

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
91.64	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T3,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T3,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T3,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T25
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T3,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T25
0	1	Covered	T83,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T25
0	1	Covered	T25,T26,T36
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T25
1	-	Covered	T25,T26,T36

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T9,T27
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T27
1	0	Covered	T5,T9,T27
1	1	Covered	T5,T9,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T27
0	1	Covered	T27,T59,T68
1	0	Covered	T5,T27,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T27
0	1	Covered	T5,T9,T27
1	0	Covered	T89,T84,T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T9,T27
1	-	Covered	T5,T9,T27

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T12
1	1	Covered	T3,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T8,T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Unreachable
1	0	Covered	T3,T6,T11

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
91.56	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T45,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T37,T42
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T37,T42

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T12
1	1	Covered	T3,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Unreachable
1	0	Covered	T3,T6,T8

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T12
1	1	Covered	T3,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T11,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Unreachable
1	0	Covered	T3,T6,T8

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T25
DetectSt	168	Covered	T2,T3,T25
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T3,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T25
DebounceSt->IdleSt	163	Covered	T36,T45,T53
DetectSt->IdleSt	186	Covered	T8,T11,T82
DetectSt->StableSt	191	Covered	T2,T3,T25
IdleSt->DebounceSt	148	Covered	T2,T3,T25
StableSt->IdleSt	206	Covered	T2,T3,T25

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
91.64	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
91.56	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T25
0	1	Covered	T2,T3,T25
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T25
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T36,T45,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T25
DetectSt	-	-	-	-	1	-	-	Covered	T1,T11,T82
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T25
DetectSt	-	-	-	-	0	0	-	Covered	T3,T5,T7
StableSt	-	-	-	-	-	-	1	Covered	T25,T26,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T25
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T5,T6
0	1	Covered	T3,T5,T6
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T6
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T5,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T5,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T94,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T5,T6
DetectSt	-	-	-	-	1	-	-	Covered	T5,T8,T27
DetectSt	-	-	-	-	0	1	-	Covered	T3,T5,T6
DetectSt	-	-	-	-	0	0	-	Covered	T5,T9,T27
StableSt	-	-	-	-	-	-	1	Covered	T3,T5,T6
StableSt	-	-	-	-	-	-	0	Covered	T3,T5,T6
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	222182740	17131	0	0
CntIncr_A	222182740	2103692	0	0
CntNoWrap_A	222182740	205658833	0	0
DetectStDropOut_A	222182740	1594	0	0
DetectedOut_A	222182740	1613996	0	0
DetectedPulseOut_A	222182740	5868	0	0
DisabledIdleSt_A	222182740	194322940	0	0
DisabledNoDetection_A	222182740	194380272	0	0
EnterDebounceSt_A	222182740	8823	0	0
EnterDetectSt_A	222182740	8325	0	0
EnterStableSt_A	222182740	5867	0	0
PulseIsPulse_A	222182740	5867	0	0
StayInStableSt	222182740	1607217	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	76909410	50411	0	0
gen_high_event_sva.HighLevelEvent_A	42727450	39564935	0	0
gen_high_level_sva.HighLevelEvent_A	145273330	134520779	0	0
gen_low_level_sva.LowLevelEvent_A	76909410	71216883	0	0
gen_not_sticky_sva.StableStDropOut_A	196546270	4774	0	0
gen_sticky_sva.StableStDropOut_A	25636470	1992817	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	17131	0	0
T1	1886	0	0	0
T2	31425	1	0	0
T3	602392	14	0	0
T5	213012	8	0	0
T6	13904	0	0	0
T7	233008	0	0	0
T8	1170	0	0	0
T10	0	2	0	0
T12	3065	0	0	0
T13	2610	0	0	0
T14	9690	0	0	0
T15	136225	0	0	0
T16	10608	0	0	0
T17	4860	0	0	0
T25	7700	2	0	0
T26	4816	2	0	0
T32	0	2	0	0
T33	0	15	0	0
T34	0	70	0	0
T35	0	3	0	0
T36	0	3	0	0
T45	2440	0	0	0
T47	6042	3	0	0
T48	0	6	0	0
T49	0	4	0	0
T51	0	4	0	0
T52	0	6	0	0
T53	0	1	0	0
T55	3208	0	0	0
T56	4560	0	0	0
T57	1387680	0	0	0
T72	507	0	0	0
T77	0	62	0	0
T80	0	2	0	0
T95	0	2	0	0
T96	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	2103692	0	0
T1	1886	0	0	0
T2	31425	20	0	0
T3	602392	509	0	0
T5	213012	395	0	0
T6	13904	0	0	0
T7	233008	0	0	0
T8	1170	0	0	0
T10	0	25	0	0
T12	3065	0	0	0
T13	2610	0	0	0
T14	9690	0	0	0
T15	136225	0	0	0
T16	10608	0	0	0
T17	4860	0	0	0
T25	7700	11	0	0
T26	4816	18	0	0
T32	0	25	0	0
T33	0	1062	0	0
T34	0	2914	0	0
T35	0	447	0	0
T36	0	36	0	0
T45	2440	0	0	0
T47	6042	178	0	0
T48	0	576	0	0
T49	0	127	0	0
T51	0	89	0	0
T52	0	174	0	0
T53	0	13	0	0
T54	0	1267	0	0
T55	3208	0	0	0
T56	4560	0	0	0
T57	1387680	0	0	0
T72	507	0	0	0
T77	0	1904	0	0
T80	0	10	0	0
T95	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	205658833	0	0
T1	24518	14070	0	0
T2	163410	34905	0	0
T3	1957774	1808981	0	0
T4	13182	2756	0	0
T5	461526	450160	0	0
T12	15938	5512	0	0
T13	13572	3146	0	0
T14	50388	8710	0	0
T15	708370	677118	0	0
T16	22984	12558	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	1594	0	0
T33	33021	7	0	0
T35	15572	0	0	0
T37	908	0	0	0
T48	18191	0	0	0
T49	6789	0	0	0
T59	5970	10	0	0
T68	0	4	0	0
T87	10827	1	0	0
T97	0	18	0	0
T98	0	3	0	0
T99	0	26	0	0
T100	0	24	0	0
T101	0	12	0	0
T102	0	5	0	0
T103	0	15	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	6	0	0
T107	0	7	0	0
T108	0	1	0	0
T109	0	6	0	0
T110	0	5	0	0
T111	0	3	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	4402	0	0	0
T115	522	0	0	0
T116	502	0	0	0
T117	423	0	0	0
T118	502	0	0	0
T119	503	0	0	0
T120	402	0	0	0
T121	16323	0	0	0
T122	9123	0	0	0
T123	20616	0	0	0
T124	24311	0	0	0
T125	111255	0	0	0
T126	350124	0	0	0
T127	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	1613996	0	0
T3	75299	53	0	0
T5	17751	0	0	0
T6	3476	0	0	0
T7	58252	0	0	0
T8	1170	0	0	0
T9	18861	161	0	0
T10	483	3	0	0
T11	1048	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	1400	7	0	0
T26	1204	2	0	0
T32	0	4	0	0
T34	0	3375	0	0
T35	0	52	0	0
T36	20490	1	0	0
T47	6042	12	0	0
T48	0	9	0	0
T49	0	19	0	0
T51	0	20	0	0
T52	0	19	0	0
T55	802	0	0	0
T56	1140	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T74	524	0	0	0
T77	0	4483	0	0
T80	0	1	0	0
T95	0	5	0	0
T96	0	5	0	0
T128	0	3	0	0
T129	0	35	0	0
T130	0	22	0	0
T131	448	0	0	0
T132	407	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	5868	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	3476	0	0	0
T7	58252	0	0	0
T8	1170	0	0	0
T9	18861	11	0	0
T10	483	1	0	0
T11	1048	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	1400	1	0	0
T26	1204	1	0	0
T32	0	1	0	0
T34	0	35	0	0
T35	0	1	0	0
T36	20490	1	0	0
T47	6042	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	802	0	0	0
T56	1140	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T74	524	0	0	0
T77	0	31	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	3	0	0
T131	448	0	0	0
T132	407	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	194322940	0	0
T1	24518	10864	0	0
T2	163410	32542	0	0
T3	1957774	1499655	0	0
T4	13182	2756	0	0
T5	461526	421712	0	0
T12	15938	5512	0	0
T13	13572	3146	0	0
T14	50388	8710	0	0
T15	708370	677118	0	0
T16	22984	12558	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	194380272	0	0
T1	24518	10884	0	0
T2	163410	32810	0	0
T3	1957774	1500368	0	0
T4	13182	2782	0	0
T5	461526	421826	0	0
T12	15938	5538	0	0
T13	13572	3172	0	0
T14	50388	8788	0	0
T15	708370	677170	0	0
T16	22984	12584	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	8823	0	0
T1	1886	0	0	0
T2	31425	1	0	0
T3	602392	9	0	0
T5	213012	4	0	0
T6	13904	0	0	0
T7	233008	0	0	0
T8	1170	0	0	0
T10	0	1	0	0
T12	3065	0	0	0
T13	2610	0	0	0
T14	9690	0	0	0
T15	136225	0	0	0
T16	10608	0	0	0
T17	4860	0	0	0
T25	7700	1	0	0
T26	4816	1	0	0
T32	0	1	0	0
T33	0	8	0	0
T34	0	35	0	0
T35	0	2	0	0
T36	0	2	0	0
T45	2440	0	0	0
T47	6042	2	0	0
T48	0	4	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	3208	0	0	0
T56	4560	0	0	0
T57	1387680	0	0	0
T72	507	0	0	0
T77	0	31	0	0
T80	0	1	0	0
T95	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	8325	0	0
T1	1886	0	0	0
T2	25140	0	0	0
T3	602392	5	0	0
T5	213012	4	0	0
T6	15642	0	0	0
T7	262134	0	0	0
T8	1170	0	0	0
T10	0	1	0	0
T12	2452	0	0	0
T13	2088	0	0	0
T14	7752	0	0	0
T15	108980	0	0	0
T16	10608	0	0	0
T17	4860	0	0	0
T25	7700	1	0	0
T26	5418	1	0	0
T32	0	1	0	0
T33	0	7	0	0
T34	0	35	0	0
T35	0	1	0	0
T36	0	1	0	0
T45	2440	0	0	0
T47	6042	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	3609	0	0	0
T56	5130	0	0	0
T57	1387680	0	0	0
T72	507	0	0	0
T77	0	31	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T128	0	1	0	0
T130	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	5867	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	3476	0	0	0
T7	58252	0	0	0
T8	1170	0	0	0
T9	18861	11	0	0
T10	483	1	0	0
T11	1048	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	1400	1	0	0
T26	1204	1	0	0
T32	0	1	0	0
T34	0	35	0	0
T35	0	1	0	0
T36	20490	1	0	0
T47	6042	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	802	0	0	0
T56	1140	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T74	524	0	0	0
T77	0	31	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	3	0	0
T131	448	0	0	0
T132	407	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	5867	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	3476	0	0	0
T7	58252	0	0	0
T8	1170	0	0	0
T9	18861	11	0	0
T10	483	1	0	0
T11	1048	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	1400	1	0	0
T26	1204	1	0	0
T32	0	1	0	0
T34	0	35	0	0
T35	0	1	0	0
T36	20490	1	0	0
T47	6042	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	802	0	0	0
T56	1140	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T74	524	0	0	0
T77	0	31	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	3	0	0
T131	448	0	0	0
T132	407	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	222182740	1607217	0	0
T3	75299	48	0	0
T5	17751	0	0	0
T6	3476	0	0	0
T7	58252	0	0	0
T8	1170	0	0	0
T9	18861	150	0	0
T10	483	2	0	0
T11	1048	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	1400	6	0	0
T26	1204	1	0	0
T32	0	3	0	0
T34	0	3331	0	0
T35	0	51	0	0
T36	20490	0	0	0
T47	6042	11	0	0
T48	0	7	0	0
T49	0	17	0	0
T51	0	18	0	0
T52	0	16	0	0
T55	802	0	0	0
T56	1140	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T74	524	0	0	0
T77	0	4449	0	0
T95	0	4	0	0
T96	0	4	0	0
T128	0	2	0	0
T129	0	34	0	0
T130	0	19	0	0
T131	448	0	0	0
T132	407	0	0	0
T133	0	12	0	0
T134	0	14	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76909410	50411	0	0
T1	7544	13	0	0
T2	56565	123	0	0
T3	677691	408	0	0
T4	507	2	0	0
T5	159759	204	0	0
T6	0	28	0	0
T7	0	47	0	0
T12	5517	8	0	0
T13	4698	51	0	0
T14	17442	42	0	0
T15	245205	42	0	0
T16	7956	4	0	0
T17	3240	0	0	0
T25	700	9	0	0
T47	0	32	0	0
T56	0	5	0	0
T72	0	27	0	0
T73	0	6	0	0
T74	0	7	0	0
T135	0	4	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42727450	39564935	0	0
T1	4715	2715	0	0
T2	31425	6770	0	0
T3	376495	348045	0	0
T4	2535	535	0	0
T5	88755	86620	0	0
T12	3065	1065	0	0
T13	2610	610	0	0
T14	9690	1690	0	0
T15	136225	130225	0	0
T16	4420	2420	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	145273330	134520779	0	0
T1	16031	9231	0	0
T2	106845	23018	0	0
T3	1280083	1183353	0	0
T4	8619	1819	0	0
T5	301767	294508	0	0
T12	10421	3621	0	0
T13	8874	2074	0	0
T14	32946	5746	0	0
T15	463165	442765	0	0
T16	15028	8228	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76909410	71216883	0	0
T1	8487	4887	0	0
T2	56565	12186	0	0
T3	677691	626481	0	0
T4	4563	963	0	0
T5	159759	155916	0	0
T12	5517	1917	0	0
T13	4698	1098	0	0
T14	17442	3042	0	0
T15	245205	234405	0	0
T16	7956	4356	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196546270	4774	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	3476	0	0	0
T7	58252	0	0	0
T8	1170	0	0	0
T9	18861	11	0	0
T10	483	1	0	0
T11	1048	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	1400	1	0	0
T26	1204	1	0	0
T32	0	1	0	0
T34	0	26	0	0
T35	0	1	0	0
T36	20490	1	0	0
T47	6042	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	0	2	0	0
T52	0	3	0	0
T55	802	0	0	0
T56	1140	0	0	0
T57	277536	0	0	0
T72	507	0	0	0
T74	524	0	0	0
T77	0	28	0	0
T80	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	3	0	0
T131	448	0	0	0
T132	407	0	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25636470	1992817	0	0
T3	225897	332	0	0
T5	53253	0	0	0
T6	5214	513	0	0
T7	87378	0	0	0
T8	0	106	0	0
T11	0	54	0	0
T16	2652	0	0	0
T17	1215	0	0	0
T25	2100	0	0	0
T26	1806	0	0	0
T55	1203	0	0	0
T56	1710	0	0	0
T61	0	338	0	0
T79	0	106844	0	0
T80	0	189	0	0
T81	0	1056	0	0
T82	0	113	0	0
T83	0	1479	0	0
T90	0	274	0	0
T91	0	950	0	0
T94	0	878	0	0
T104	0	166	0	0