Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T36
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T36,T37
0	1	Covered	T110
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T36,T37
0	1	Covered	T1,T42,T83
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T36,T37
1	-	Covered	T1,T42,T83

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T36,T37
DetectSt	168	Covered	T1,T36,T37
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T36,T37
DebounceSt->IdleSt	163	Covered	T179,T84,T180
DetectSt->IdleSt	186	Covered	T110
DetectSt->StableSt	191	Covered	T1,T36,T37
IdleSt->DebounceSt	148	Covered	T1,T36,T37
StableSt->IdleSt	206	Covered	T1,T36,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T36,T37
0	1	Covered	T1,T36,T37
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T36,T37
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T179,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T110
DetectSt	-	-	-	-	0	1	-	Covered	T1,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T42,T83
StableSt	-	-	-	-	-	-	0	Covered	T1,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	79	0	0
CntIncr_A	8545490	2453	0	0
CntNoWrap_A	8545490	7910535	0	0
DetectStDropOut_A	8545490	1	0	0
DetectedOut_A	8545490	3434	0	0
DetectedPulseOut_A	8545490	37	0	0
DisabledIdleSt_A	8545490	7469182	0	0
DisabledNoDetection_A	8545490	7471502	0	0
EnterDebounceSt_A	8545490	41	0	0
EnterDetectSt_A	8545490	38	0	0
EnterStableSt_A	8545490	37	0	0
PulseIsPulse_A	8545490	37	0	0
StayInStableSt	8545490	3375	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	79	0	0
T1	943	2	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T39	0	2	0	0
T42	0	4	0	0
T44	0	2	0	0
T83	0	2	0	0
T102	0	2	0	0
T158	0	2	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2453	0	0
T1	943	67	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	90	0	0
T37	0	55	0	0
T39	0	49	0	0
T42	0	184	0	0
T44	0	35	0	0
T83	0	76	0	0
T102	0	46	0	0
T158	0	82	0	0
T181	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910535	0	0
T1	943	540	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1	0	0
T110	20279	1	0	0
T111	13760	0	0	0
T182	406	0	0	0
T183	621	0	0	0
T184	522	0	0	0
T185	11410	0	0	0
T186	503	0	0	0
T187	440	0	0	0
T188	490	0	0	0
T189	23785	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	3434	0	0
T1	943	56	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	209	0	0
T37	0	46	0	0
T39	0	181	0	0
T42	0	308	0	0
T44	0	233	0	0
T83	0	39	0	0
T102	0	209	0	0
T158	0	51	0	0
T181	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	37	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T83	0	1	0	0
T102	0	1	0	0
T158	0	1	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7469182	0	0
T1	943	4	0	0
T2	6285	1115	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7471502	0	0
T1	943	4	0	0
T2	6285	1124	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	41	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T83	0	1	0	0
T102	0	1	0	0
T158	0	1	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	38	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T83	0	1	0	0
T102	0	1	0	0
T158	0	1	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	37	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T83	0	1	0	0
T102	0	1	0	0
T158	0	1	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	37	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T83	0	1	0	0
T102	0	1	0	0
T158	0	1	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	3375	0	0
T1	943	55	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	207	0	0
T37	0	44	0	0
T39	0	179	0	0
T42	0	305	0	0
T44	0	231	0	0
T83	0	38	0	0
T102	0	207	0	0
T158	0	49	0	0
T181	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	14	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T42	0	1	0	0
T83	0	1	0	0
T105	0	1	0	0
T126	0	1	0	0
T162	0	1	0	0
T179	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T37,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T37,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T37,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T37,T43
1	0	Covered	T4,T1,T2
1	1	Covered	T2,T37,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T37,T43
0	1	Covered	T88,T162,T136
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T37,T43
0	1	Covered	T37,T158,T130
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T37,T43
1	-	Covered	T37,T158,T130

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T37,T43
DetectSt	168	Covered	T2,T37,T43
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T2,T37,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T37,T43
DebounceSt->IdleSt	163	Covered	T38,T130,T84
DetectSt->IdleSt	186	Covered	T88,T162,T136
DetectSt->StableSt	191	Covered	T2,T37,T43
IdleSt->DebounceSt	148	Covered	T2,T37,T43
StableSt->IdleSt	206	Covered	T2,T37,T158

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T37,T43
0	1	Covered	T2,T37,T43
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T37,T43
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T37,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T37,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T130,T193
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T37,T43
DetectSt	-	-	-	-	1	-	-	Covered	T88,T162,T136
DetectSt	-	-	-	-	0	1	-	Covered	T2,T37,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T158,T130
StableSt	-	-	-	-	-	-	0	Covered	T2,T37,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	108	0	0
CntIncr_A	8545490	4541	0	0
CntNoWrap_A	8545490	7910506	0	0
DetectStDropOut_A	8545490	4	0	0
DetectedOut_A	8545490	3847	0	0
DetectedPulseOut_A	8545490	48	0	0
DisabledIdleSt_A	8545490	7894084	0	0
DisabledNoDetection_A	8545490	7896410	0	0
EnterDebounceSt_A	8545490	57	0	0
EnterDetectSt_A	8545490	52	0	0
EnterStableSt_A	8545490	48	0	0
PulseIsPulse_A	8545490	48	0	0
StayInStableSt	8545490	3779	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8545490	2894	0	0
gen_low_level_sva.LowLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	108	0	0
T2	6285	2	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T37	0	2	0	0
T38	0	3	0	0
T43	0	2	0	0
T83	0	4	0	0
T130	0	3	0	0
T158	0	2	0	0
T161	0	2	0	0
T194	0	2	0	0
T195	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	4541	0	0
T2	6285	27	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T37	0	55	0	0
T38	0	20	0	0
T43	0	36	0	0
T83	0	152	0	0
T130	0	54	0	0
T158	0	82	0	0
T161	0	63	0	0
T194	0	13	0	0
T195	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910506	0	0
T1	943	542	0	0
T2	6285	1341	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	4	0	0
T88	490	1	0	0
T136	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T196	701	0	0	0
T197	422	0	0	0
T198	699	0	0	0
T199	15194	0	0	0
T200	26237	0	0	0
T201	503	0	0	0
T202	498	0	0	0
T203	491	0	0	0
T204	968	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	3847	0	0
T2	6285	70	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T37	0	34	0	0
T38	0	106	0	0
T43	0	156	0	0
T83	0	238	0	0
T130	0	17	0	0
T158	0	250	0	0
T161	0	25	0	0
T194	0	46	0	0
T195	0	171	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	48	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	0	1	0	0
T83	0	2	0	0
T130	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7894084	0	0
T1	943	542	0	0
T2	6285	1241	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7896410	0	0
T1	943	543	0	0
T2	6285	1251	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	57	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T43	0	1	0	0
T83	0	2	0	0
T130	0	2	0	0
T158	0	1	0	0
T161	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	52	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	0	1	0	0
T83	0	2	0	0
T130	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	48	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	0	1	0	0
T83	0	2	0	0
T130	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	48	0	0
T2	6285	1	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	0	1	0	0
T83	0	2	0	0
T130	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T194	0	1	0	0
T195	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	3779	0	0
T2	6285	68	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T37	0	33	0	0
T38	0	104	0	0
T43	0	154	0	0
T83	0	235	0	0
T130	0	16	0	0
T158	0	249	0	0
T161	0	24	0	0
T194	0	44	0	0
T195	0	169	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2894	0	0
T1	943	2	0	0
T2	6285	14	0	0
T3	75299	24	0	0
T4	507	2	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	6	0	0
T14	1938	8	0	0
T15	27245	8	0	0
T16	884	4	0	0
T56	0	5	0	0
T72	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	27	0	0
T35	15572	0	0	0
T37	908	1	0	0
T45	2440	0	0	0
T48	18191	0	0	0
T49	6789	0	0	0
T83	0	1	0	0
T87	0	1	0	0
T105	0	1	0	0
T116	502	0	0	0
T117	423	0	0	0
T118	502	0	0	0
T126	0	2	0	0
T130	0	1	0	0
T158	0	1	0	0
T161	0	1	0	0
T190	0	1	0	0
T205	0	1	0	0
T206	402	0	0	0
T207	506	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T12,T13
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T45
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T37,T40
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T37,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T39,T208,T209
DetectSt->IdleSt	186	Covered	T1,T45
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T208,T209
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T1,T45
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T37,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	136	0	0
CntIncr_A	8545490	94173	0	0
CntNoWrap_A	8545490	7910478	0	0
DetectStDropOut_A	8545490	2	0	0
DetectedOut_A	8545490	19089	0	0
DetectedPulseOut_A	8545490	63	0	0
DisabledIdleSt_A	8545490	7754706	0	0
DisabledNoDetection_A	8545490	7757031	0	0
EnterDebounceSt_A	8545490	71	0	0
EnterDetectSt_A	8545490	65	0	0
EnterStableSt_A	8545490	63	0	0
PulseIsPulse_A	8545490	63	0	0
StayInStableSt	8545490	19003	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	136	0	0
T1	943	6	0	0
T2	6285	2	0	0
T3	75299	2	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	1	0	0
T40	0	4	0	0
T45	0	4	0	0
T158	0	6	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	94173	0	0
T1	943	201	0	0
T2	6285	27	0	0
T3	75299	27892	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	90	0	0
T37	0	110	0	0
T39	0	49	0	0
T40	0	164	0	0
T45	0	90	0	0
T158	0	246	0	0
T181	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910478	0	0
T1	943	536	0	0
T2	6285	1341	0	0
T3	75299	69577	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T45	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	19089	0	0
T1	943	82	0	0
T2	6285	38	0	0
T3	75299	3884	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	41	0	0
T37	0	140	0	0
T40	0	212	0	0
T45	0	40	0	0
T46	0	116	0	0
T158	0	250	0	0
T181	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	63	0	0
T1	943	2	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T158	0	3	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7754706	0	0
T1	943	4	0	0
T2	6285	1241	0	0
T3	75299	37796	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7757031	0	0
T1	943	4	0	0
T2	6285	1251	0	0
T3	75299	37825	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	71	0	0
T1	943	3	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T45	0	2	0	0
T158	0	3	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	65	0	0
T1	943	3	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T158	0	3	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	63	0	0
T1	943	2	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T158	0	3	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	63	0	0
T1	943	2	0	0
T2	6285	1	0	0
T3	75299	1	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T158	0	3	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	19003	0	0
T1	943	79	0	0
T2	6285	36	0	0
T3	75299	3882	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T36	0	39	0	0
T37	0	138	0	0
T40	0	210	0	0
T45	0	38	0	0
T46	0	114	0	0
T158	0	246	0	0
T181	0	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	39	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T40	0	2	0	0
T83	0	1	0	0
T102	0	1	0	0
T130	0	1	0	0
T158	0	2	0	0
T181	0	1	0	0
T210	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T45,T44,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T45,T44,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T45,T44,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T36
1	0	Covered	T1,T2,T12
1	1	Covered	T45,T44,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T44,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T44,T38
0	1	Covered	T45,T44,T38
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T44,T38
1	-	Covered	T45,T44,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T45,T44,T38
DetectSt	168	Covered	T45,T44,T38
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T45,T44,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T45,T44,T38
DebounceSt->IdleSt	163	Covered	T125,T136,T84
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T45,T44,T38
IdleSt->DebounceSt	148	Covered	T45,T44,T38
StableSt->IdleSt	206	Covered	T45,T44,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T44,T38
0	1	Covered	T45,T44,T38
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T44,T38
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T44,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T44,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T136,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T44,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T45,T44,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T44,T38
StableSt	-	-	-	-	-	-	0	Covered	T45,T44,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	63	0	0
CntIncr_A	8545490	33703	0	0
CntNoWrap_A	8545490	7910551	0	0
DetectStDropOut_A	8545490	0	0	0
DetectedOut_A	8545490	2685	0	0
DetectedPulseOut_A	8545490	30	0	0
DisabledIdleSt_A	8545490	7757332	0	0
DisabledNoDetection_A	8545490	7759658	0	0
EnterDebounceSt_A	8545490	34	0	0
EnterDetectSt_A	8545490	30	0	0
EnterStableSt_A	8545490	30	0	0
PulseIsPulse_A	8545490	30	0	0
StayInStableSt	8545490	2640	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8545490	6457	0	0
gen_low_level_sva.LowLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	63	0	0
T22	1636	0	0	0
T38	0	2	0	0
T41	1334	0	0	0
T44	0	2	0	0
T45	2440	2	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T83	0	2	0	0
T102	0	2	0	0
T105	0	2	0	0
T161	0	4	0	0
T190	0	2	0	0
T195	0	2	0	0
T210	0	2	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	33703	0	0
T22	1636	0	0	0
T38	0	10	0	0
T41	1334	0	0	0
T44	0	35	0	0
T45	2440	45	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T83	0	76	0	0
T102	0	46	0	0
T105	0	56	0	0
T161	0	126	0	0
T190	0	22	0	0
T195	0	68	0	0
T210	0	16	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910551	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2685	0	0
T22	1636	0	0	0
T38	0	67	0	0
T41	1334	0	0	0
T44	0	88	0	0
T45	2440	49	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T83	0	236	0	0
T102	0	359	0	0
T105	0	293	0	0
T161	0	82	0	0
T190	0	81	0	0
T195	0	42	0	0
T210	0	73	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	30	0	0
T22	1636	0	0	0
T38	0	1	0	0
T41	1334	0	0	0
T44	0	1	0	0
T45	2440	1	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T83	0	1	0	0
T102	0	1	0	0
T105	0	1	0	0
T161	0	2	0	0
T190	0	1	0	0
T195	0	1	0	0
T210	0	1	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7757332	0	0
T1	943	542	0	0
T2	6285	984	0	0
T3	75299	37796	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7759658	0	0
T1	943	543	0	0
T2	6285	993	0	0
T3	75299	37825	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	34	0	0
T22	1636	0	0	0
T38	0	1	0	0
T41	1334	0	0	0
T44	0	1	0	0
T45	2440	1	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T83	0	1	0	0
T102	0	1	0	0
T105	0	1	0	0
T161	0	2	0	0
T190	0	1	0	0
T195	0	1	0	0
T210	0	1	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	30	0	0
T22	1636	0	0	0
T38	0	1	0	0
T41	1334	0	0	0
T44	0	1	0	0
T45	2440	1	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T83	0	1	0	0
T102	0	1	0	0
T105	0	1	0	0
T161	0	2	0	0
T190	0	1	0	0
T195	0	1	0	0
T210	0	1	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	30	0	0
T22	1636	0	0	0
T38	0	1	0	0
T41	1334	0	0	0
T44	0	1	0	0
T45	2440	1	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T83	0	1	0	0
T102	0	1	0	0
T105	0	1	0	0
T161	0	2	0	0
T190	0	1	0	0
T195	0	1	0	0
T210	0	1	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	30	0	0
T22	1636	0	0	0
T38	0	1	0	0
T41	1334	0	0	0
T44	0	1	0	0
T45	2440	1	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T83	0	1	0	0
T102	0	1	0	0
T105	0	1	0	0
T161	0	2	0	0
T190	0	1	0	0
T195	0	1	0	0
T210	0	1	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2640	0	0
T22	1636	0	0	0
T38	0	66	0	0
T41	1334	0	0	0
T44	0	87	0	0
T45	2440	48	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T83	0	234	0	0
T102	0	357	0	0
T105	0	292	0	0
T161	0	79	0	0
T190	0	80	0	0
T195	0	41	0	0
T210	0	71	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6457	0	0
T1	943	2	0	0
T2	6285	10	0	0
T3	75299	53	0	0
T5	17751	33	0	0
T6	0	7	0	0
T7	0	11	0	0
T12	613	2	0	0
T13	522	5	0	0
T14	1938	5	0	0
T15	27245	4	0	0
T16	884	0	0	0
T17	405	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	14	0	0
T22	1636	0	0	0
T38	0	1	0	0
T41	1334	0	0	0
T44	0	1	0	0
T45	2440	1	0	0
T50	675	0	0	0
T58	8552	0	0	0
T76	19961	0	0	0
T105	0	1	0	0
T125	0	1	0	0
T161	0	1	0	0
T179	0	1	0	0
T190	0	1	0	0
T195	0	1	0	0
T211	7728	0	0	0
T212	551	0	0	0
T213	526	0	0	0
T214	503	0	0	0
T215	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T2,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T1,T2,T13
1	1	Covered	T1,T2,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T37,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T1,T37,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T1,T37,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T37,T45
1	0	Covered	T2,T13,T14
1	1	Covered	T1,T37,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T37,T45
0	1	Covered	T1
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T37,T45
0	1	Covered	T1,T41,T40
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T37,T45
1	-	Covered	T1,T41,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T37,T45
DetectSt	168	Covered	T1,T37,T45
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T1,T37,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T37,T45
DebounceSt->IdleSt	163	Covered	T37,T104,T84
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1,T37,T45
IdleSt->DebounceSt	148	Covered	T1,T37,T45
StableSt->IdleSt	206	Covered	T1,T41,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T37,T45
0	1	Covered	T1,T37,T45
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T37,T45
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T37,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T37,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T37,T104,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T37,T45
DetectSt	-	-	-	-	1	-	-	Covered	T1
DetectSt	-	-	-	-	0	1	-	Covered	T1,T37,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T41,T40
StableSt	-	-	-	-	-	-	0	Covered	T1,T37,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	105	0	0
CntIncr_A	8545490	3185	0	0
CntNoWrap_A	8545490	7910509	0	0
DetectStDropOut_A	8545490	1	0	0
DetectedOut_A	8545490	5108	0	0
DetectedPulseOut_A	8545490	49	0	0
DisabledIdleSt_A	8545490	7893506	0	0
DisabledNoDetection_A	8545490	7895837	0	0
EnterDebounceSt_A	8545490	55	0	0
EnterDetectSt_A	8545490	50	0	0
EnterStableSt_A	8545490	49	0	0
PulseIsPulse_A	8545490	49	0	0
StayInStableSt	8545490	5037	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	105	0	0
T1	943	4	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	3	0	0
T40	0	2	0	0
T41	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T102	0	4	0	0
T158	0	6	0	0
T161	0	2	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	3185	0	0
T1	943	134	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	110	0	0
T40	0	82	0	0
T41	0	99	0	0
T45	0	50	0	0
T46	0	11	0	0
T102	0	92	0	0
T158	0	246	0	0
T161	0	63	0	0
T181	0	63	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910509	0	0
T1	943	538	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	5108	0	0
T1	943	53	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	45	0	0
T40	0	505	0	0
T41	0	190	0	0
T45	0	95	0	0
T46	0	43	0	0
T102	0	28	0	0
T158	0	166	0	0
T161	0	256	0	0
T181	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	49	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T102	0	2	0	0
T158	0	3	0	0
T161	0	1	0	0
T181	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7893506	0	0
T1	943	4	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7895837	0	0
T1	943	4	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	55	0	0
T1	943	2	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T102	0	2	0	0
T158	0	3	0	0
T161	0	1	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	50	0	0
T1	943	2	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T102	0	2	0	0
T158	0	3	0	0
T161	0	1	0	0
T181	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	49	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T102	0	2	0	0
T158	0	3	0	0
T161	0	1	0	0
T181	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	49	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T102	0	2	0	0
T158	0	3	0	0
T161	0	1	0	0
T181	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	5037	0	0
T1	943	52	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T37	0	43	0	0
T40	0	504	0	0
T41	0	189	0	0
T45	0	93	0	0
T46	0	41	0	0
T102	0	26	0	0
T158	0	162	0	0
T161	0	254	0	0
T181	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	26	0	0
T1	943	1	0	0
T2	6285	0	0	0
T3	75299	0	0	0
T5	17751	0	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T87	0	1	0	0
T102	0	2	0	0
T105	0	3	0	0
T158	0	2	0	0
T181	0	1	0	0
T190	0	1	0	0
T195	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T43,T44,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T43,T44,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T43,T44,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T45,T43
1	0	Covered	T1,T2,T13
1	1	Covered	T43,T44,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T42
0	1	Covered	T44,T42,T217
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T44,T42
1	-	Covered	T44,T42,T217

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T43,T44,T42
DetectSt	168	Covered	T43,T44,T42
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T43,T44,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T44,T42
DebounceSt->IdleSt	163	Covered	T176,T192,T84
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T43,T44,T42
IdleSt->DebounceSt	148	Covered	T43,T44,T42
StableSt->IdleSt	206	Covered	T44,T42,T83

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T43,T44,T42
0	1	Covered	T43,T44,T42
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T44,T42
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T43,T44,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T44,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T176,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T43,T44,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T43,T44,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T42,T217
StableSt	-	-	-	-	-	-	0	Covered	T43,T44,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	61	0	0
CntIncr_A	8545490	1794	0	0
CntNoWrap_A	8545490	7910553	0	0
DetectStDropOut_A	8545490	0	0	0
DetectedOut_A	8545490	1833	0	0
DetectedPulseOut_A	8545490	29	0	0
DisabledIdleSt_A	8545490	7577634	0	0
DisabledNoDetection_A	8545490	7579966	0	0
EnterDebounceSt_A	8545490	32	0	0
EnterDetectSt_A	8545490	29	0	0
EnterStableSt_A	8545490	29	0	0
PulseIsPulse_A	8545490	29	0	0
StayInStableSt	8545490	1789	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8545490	6030	0	0
gen_low_level_sva.LowLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	61	0	0
T24	493	0	0	0
T42	1041	2	0	0
T43	639	2	0	0
T44	793	2	0	0
T83	0	2	0	0
T105	0	2	0	0
T176	0	1	0	0
T181	0	2	0	0
T190	0	2	0	0
T217	0	2	0	0
T218	0	2	0	0
T219	426	0	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1794	0	0
T24	493	0	0	0
T42	1041	92	0	0
T43	639	36	0	0
T44	793	35	0	0
T83	0	76	0	0
T105	0	24	0	0
T176	0	57	0	0
T181	0	63	0	0
T190	0	22	0	0
T217	0	32	0	0
T218	0	45	0	0
T219	426	0	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7910553	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1833	0	0
T24	493	0	0	0
T42	1041	40	0	0
T43	639	79	0	0
T44	793	31	0	0
T83	0	42	0	0
T87	0	90	0	0
T105	0	154	0	0
T181	0	42	0	0
T190	0	41	0	0
T217	0	23	0	0
T218	0	45	0	0
T219	426	0	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	29	0	0
T24	493	0	0	0
T42	1041	1	0	0
T43	639	1	0	0
T44	793	1	0	0
T83	0	1	0	0
T87	0	1	0	0
T105	0	1	0	0
T181	0	1	0	0
T190	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	426	0	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7577634	0	0
T1	943	542	0	0
T2	6285	1086	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7579966	0	0
T1	943	543	0	0
T2	6285	1096	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	32	0	0
T24	493	0	0	0
T42	1041	1	0	0
T43	639	1	0	0
T44	793	1	0	0
T83	0	1	0	0
T105	0	1	0	0
T176	0	1	0	0
T181	0	1	0	0
T190	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	426	0	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	29	0	0
T24	493	0	0	0
T42	1041	1	0	0
T43	639	1	0	0
T44	793	1	0	0
T83	0	1	0	0
T87	0	1	0	0
T105	0	1	0	0
T181	0	1	0	0
T190	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	426	0	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	29	0	0
T24	493	0	0	0
T42	1041	1	0	0
T43	639	1	0	0
T44	793	1	0	0
T83	0	1	0	0
T87	0	1	0	0
T105	0	1	0	0
T181	0	1	0	0
T190	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	426	0	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	29	0	0
T24	493	0	0	0
T42	1041	1	0	0
T43	639	1	0	0
T44	793	1	0	0
T83	0	1	0	0
T87	0	1	0	0
T105	0	1	0	0
T181	0	1	0	0
T190	0	1	0	0
T217	0	1	0	0
T218	0	1	0	0
T219	426	0	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1789	0	0
T24	493	0	0	0
T42	1041	39	0	0
T43	639	77	0	0
T44	793	30	0	0
T83	0	40	0	0
T87	0	88	0	0
T105	0	153	0	0
T181	0	40	0	0
T190	0	39	0	0
T217	0	22	0	0
T218	0	43	0	0
T219	426	0	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	6030	0	0
T1	943	2	0	0
T2	6285	12	0	0
T3	75299	41	0	0
T5	17751	32	0	0
T7	0	15	0	0
T12	613	0	0	0
T13	522	4	0	0
T14	1938	3	0	0
T15	27245	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T47	0	13	0	0
T72	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	13	0	0
T24	493	0	0	0
T39	2782	0	0	0
T42	1041	1	0	0
T44	793	1	0	0
T105	0	1	0	0
T191	0	1	0	0
T209	0	2	0	0
T217	0	1	0	0
T220	2267	0	0	0
T221	426	0	0	0
T222	430	0	0	0
T223	10272	0	0	0
T224	406	0	0	0
T225	0	1	0	0
T226	0	1	0	0
T227	0	1	0	0
T228	0	1	0	0
T229	505	0	0	0