Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T9,T27
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T27
1	0	Covered	T5,T9,T27
1	1	Covered	T5,T9,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T27
0	1	Covered	T59,T68,T97
1	0	Covered	T5,T68,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T27,T34
0	1	Covered	T9,T27,T34
1	0	Covered	T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T27,T34
1	-	Covered	T9,T27,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T9,T27
DetectSt	168	Covered	T5,T9,T27
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T9,T27,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T9,T27
DebounceSt->IdleSt	163	Covered	T84,T60
DetectSt->IdleSt	186	Covered	T5,T59,T68
DetectSt->StableSt	191	Covered	T9,T27,T34
IdleSt->DebounceSt	148	Covered	T5,T9,T27
StableSt->IdleSt	206	Covered	T9,T27,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T9,T27
0	1	Covered	T5,T9,T27
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T27
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T9,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T9,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T9,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T9,T27
DetectSt	-	-	-	-	1	-	-	Covered	T5,T59,T68
DetectSt	-	-	-	-	0	1	-	Covered	T9,T27,T34
DetectSt	-	-	-	-	0	0	-	Covered	T5,T9,T27
StableSt	-	-	-	-	-	-	1	Covered	T9,T27,T34
StableSt	-	-	-	-	-	-	0	Covered	T9,T27,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	3063	0	0
CntIncr_A	8545490	106056	0	0
CntNoWrap_A	8545490	7907551	0	0
DetectStDropOut_A	8545490	421	0	0
DetectedOut_A	8545490	90196	0	0
DetectedPulseOut_A	8545490	893	0	0
DisabledIdleSt_A	8545490	7428783	0	0
DisabledNoDetection_A	8545490	7430938	0	0
EnterDebounceSt_A	8545490	1534	0	0
EnterDetectSt_A	8545490	1529	0	0
EnterStableSt_A	8545490	893	0	0
PulseIsPulse_A	8545490	893	0	0
StayInStableSt	8545490	89176	0	0
gen_high_event_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	765	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	3063	0	0
T5	17751	8	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	22	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	16	0	0
T34	0	58	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	20	0	0
T59	0	20	0	0
T68	0	24	0	0
T76	0	12	0	0
T77	0	58	0	0
T78	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	106056	0	0
T5	17751	395	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	913	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	392	0	0
T34	0	2494	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	870	0	0
T59	0	664	0	0
T68	0	820	0	0
T76	0	438	0	0
T77	0	1798	0	0
T78	0	832	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7907551	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17311	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	421	0	0
T23	496	0	0	0
T51	742	0	0	0
T52	1977	0	0	0
T59	5970	10	0	0
T61	1151	0	0	0
T68	7541	4	0	0
T69	423	0	0	0
T70	405	0	0	0
T71	186607	0	0	0
T77	14224	0	0	0
T97	0	18	0	0
T99	0	26	0	0
T100	0	24	0	0
T101	0	12	0	0
T103	0	15	0	0
T149	0	21	0	0
T275	0	20	0	0
T276	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	90196	0	0
T9	18861	161	0	0
T10	483	0	0	0
T11	1048	0	0	0
T27	6254	64	0	0
T32	1419	0	0	0
T34	0	2991	0	0
T36	20490	0	0	0
T58	0	218	0	0
T74	524	0	0	0
T76	0	162	0	0
T77	0	4031	0	0
T78	0	322	0	0
T131	448	0	0	0
T132	407	0	0	0
T142	414	0	0	0
T277	0	2593	0	0
T278	0	1379	0	0
T279	0	3031	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	893	0	0
T9	18861	11	0	0
T10	483	0	0	0
T11	1048	0	0	0
T27	6254	8	0	0
T32	1419	0	0	0
T34	0	29	0	0
T36	20490	0	0	0
T58	0	10	0	0
T74	524	0	0	0
T76	0	6	0	0
T77	0	29	0	0
T78	0	13	0	0
T131	448	0	0	0
T132	407	0	0	0
T142	414	0	0	0
T277	0	30	0	0
T278	0	16	0	0
T279	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7428783	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	12201	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7430938	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	12205	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1534	0	0
T5	17751	4	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	11	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	8	0	0
T34	0	29	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T68	0	12	0	0
T76	0	6	0	0
T77	0	29	0	0
T78	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1529	0	0
T5	17751	4	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	11	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	8	0	0
T34	0	29	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	10	0	0
T59	0	10	0	0
T68	0	12	0	0
T76	0	6	0	0
T77	0	29	0	0
T78	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	893	0	0
T9	18861	11	0	0
T10	483	0	0	0
T11	1048	0	0	0
T27	6254	8	0	0
T32	1419	0	0	0
T34	0	29	0	0
T36	20490	0	0	0
T58	0	10	0	0
T74	524	0	0	0
T76	0	6	0	0
T77	0	29	0	0
T78	0	13	0	0
T131	448	0	0	0
T132	407	0	0	0
T142	414	0	0	0
T277	0	30	0	0
T278	0	16	0	0
T279	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	893	0	0
T9	18861	11	0	0
T10	483	0	0	0
T11	1048	0	0	0
T27	6254	8	0	0
T32	1419	0	0	0
T34	0	29	0	0
T36	20490	0	0	0
T58	0	10	0	0
T74	524	0	0	0
T76	0	6	0	0
T77	0	29	0	0
T78	0	13	0	0
T131	448	0	0	0
T132	407	0	0	0
T142	414	0	0	0
T277	0	30	0	0
T278	0	16	0	0
T279	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	89176	0	0
T9	18861	150	0	0
T10	483	0	0	0
T11	1048	0	0	0
T27	6254	56	0	0
T32	1419	0	0	0
T34	0	2953	0	0
T36	20490	0	0	0
T58	0	208	0	0
T74	524	0	0	0
T76	0	156	0	0
T77	0	4000	0	0
T78	0	309	0	0
T131	448	0	0	0
T132	407	0	0	0
T142	414	0	0	0
T277	0	2563	0	0
T278	0	1361	0	0
T279	0	2997	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	765	0	0
T9	18861	11	0	0
T10	483	0	0	0
T11	1048	0	0	0
T27	6254	8	0	0
T32	1419	0	0	0
T34	0	20	0	0
T36	20490	0	0	0
T58	0	10	0	0
T74	524	0	0	0
T76	0	6	0	0
T77	0	27	0	0
T78	0	13	0	0
T131	448	0	0	0
T132	407	0	0	0
T142	414	0	0	0
T277	0	30	0	0
T278	0	14	0	0
T279	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T5
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T2,T3,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T2,T3,T47

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T47,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T14,T15
1	1	Covered	T2,T3,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T47,T10
0	1	Covered	T33,T98,T102
1	0	Covered	T84,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T47,T10
0	1	Covered	T3,T47,T10
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T47,T10
1	-	Covered	T3,T47,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T47
DetectSt	168	Covered	T3,T47,T10
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T47,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T47,T10
DebounceSt->IdleSt	163	Covered	T2,T3,T47
DetectSt->IdleSt	186	Covered	T33,T98,T102
DetectSt->StableSt	191	Covered	T3,T47,T10
IdleSt->DebounceSt	148	Covered	T2,T3,T47
StableSt->IdleSt	206	Covered	T3,T47,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T47
0	1	Covered	T2,T3,T47
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T47,T10
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T47,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T3,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T47
DetectSt	-	-	-	-	1	-	-	Covered	T33,T98,T102
DetectSt	-	-	-	-	0	1	-	Covered	T3,T47,T10
DetectSt	-	-	-	-	0	0	-	Covered	T3,T47,T10
StableSt	-	-	-	-	-	-	1	Covered	T3,T47,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T47,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	936	0	0
CntIncr_A	8545490	49825	0	0
CntNoWrap_A	8545490	7909678	0	0
DetectStDropOut_A	8545490	51	0	0
DetectedOut_A	8545490	14613	0	0
DetectedPulseOut_A	8545490	372	0	0
DisabledIdleSt_A	8545490	7518992	0	0
DisabledNoDetection_A	8545490	7520613	0	0
EnterDebounceSt_A	8545490	512	0	0
EnterDetectSt_A	8545490	427	0	0
EnterStableSt_A	8545490	372	0	0
PulseIsPulse_A	8545490	372	0	0
StayInStableSt	8545490	14206	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	335	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	936	0	0
T2	6285	1	0	0
T3	75299	14	0	0
T5	17751	0	0	0
T10	0	2	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T32	0	2	0	0
T33	0	15	0	0
T34	0	12	0	0
T35	0	3	0	0
T47	0	3	0	0
T48	0	6	0	0
T77	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	49825	0	0
T2	6285	20	0	0
T3	75299	509	0	0
T5	17751	0	0	0
T10	0	25	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T32	0	25	0	0
T33	0	1062	0	0
T34	0	420	0	0
T35	0	447	0	0
T47	0	178	0	0
T48	0	576	0	0
T77	0	106	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7909678	0	0
T1	943	542	0	0
T2	6285	1342	0	0
T3	75299	69565	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	51	0	0
T33	33021	7	0	0
T35	15572	0	0	0
T37	908	0	0	0
T48	18191	0	0	0
T49	6789	0	0	0
T98	0	3	0	0
T102	0	5	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	6	0	0
T107	0	7	0	0
T109	0	6	0	0
T110	0	5	0	0
T111	0	3	0	0
T114	4402	0	0	0
T115	522	0	0	0
T116	502	0	0	0
T117	423	0	0	0
T118	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	14613	0	0
T3	75299	53	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T10	0	3	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T32	0	4	0	0
T34	0	384	0	0
T35	0	52	0	0
T47	0	12	0	0
T48	0	9	0	0
T55	401	0	0	0
T56	570	0	0	0
T77	0	452	0	0
T128	0	3	0	0
T129	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	372	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T10	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T32	0	1	0	0
T34	0	6	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T77	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7518992	0	0
T1	943	542	0	0
T2	6285	1310	0	0
T3	75299	63820	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7520613	0	0
T1	943	543	0	0
T2	6285	1320	0	0
T3	75299	63834	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	512	0	0
T2	6285	1	0	0
T3	75299	9	0	0
T5	17751	0	0	0
T10	0	1	0	0
T12	613	0	0	0
T13	522	0	0	0
T14	1938	0	0	0
T15	27245	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T32	0	1	0	0
T33	0	8	0	0
T34	0	6	0	0
T35	0	2	0	0
T47	0	2	0	0
T48	0	4	0	0
T77	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	427	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T10	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T32	0	1	0	0
T33	0	7	0	0
T34	0	6	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T77	0	2	0	0
T128	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	372	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T10	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T32	0	1	0	0
T34	0	6	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T77	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	372	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T10	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T32	0	1	0	0
T34	0	6	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T77	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	14206	0	0
T3	75299	48	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T10	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T32	0	3	0	0
T34	0	378	0	0
T35	0	51	0	0
T47	0	11	0	0
T48	0	7	0	0
T55	401	0	0	0
T56	570	0	0	0
T77	0	449	0	0
T128	0	2	0	0
T129	0	34	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	335	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T10	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T32	0	1	0	0
T34	0	6	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T77	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T9,T27
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T27
1	0	Covered	T5,T9,T27
1	1	Covered	T5,T9,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T27
0	1	Covered	T27,T59,T280
1	0	Covered	T27,T279,T280

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T34
0	1	Covered	T5,T9,T34
1	0	Covered	T84,T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T9,T34
1	-	Covered	T5,T9,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T9,T27
DetectSt	168	Covered	T5,T9,T27
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T5,T9,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T9,T27
DebounceSt->IdleSt	163	Covered	T84,T60
DetectSt->IdleSt	186	Covered	T27,T59,T279
DetectSt->StableSt	191	Covered	T5,T9,T34
IdleSt->DebounceSt	148	Covered	T5,T9,T27
StableSt->IdleSt	206	Covered	T5,T9,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T9,T27
0	1	Covered	T5,T9,T27
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T27
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T9,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T9,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T9,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T9,T27
DetectSt	-	-	-	-	1	-	-	Covered	T27,T59,T279
DetectSt	-	-	-	-	0	1	-	Covered	T5,T9,T34
DetectSt	-	-	-	-	0	0	-	Covered	T5,T9,T27
StableSt	-	-	-	-	-	-	1	Covered	T5,T9,T34
StableSt	-	-	-	-	-	-	0	Covered	T5,T9,T34
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	2975	0	0
CntIncr_A	8545490	104975	0	0
CntNoWrap_A	8545490	7907639	0	0
DetectStDropOut_A	8545490	265	0	0
DetectedOut_A	8545490	92029	0	0
DetectedPulseOut_A	8545490	968	0	0
DisabledIdleSt_A	8545490	7430462	0	0
DisabledNoDetection_A	8545490	7432600	0	0
EnterDebounceSt_A	8545490	1490	0	0
EnterDetectSt_A	8545490	1485	0	0
EnterStableSt_A	8545490	968	0	0
PulseIsPulse_A	8545490	968	0	0
StayInStableSt	8545490	90917	0	0
gen_high_event_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	822	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2975	0	0
T5	17751	48	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	54	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	24	0	0
T34	0	58	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	32	0	0
T59	0	18	0	0
T68	0	50	0	0
T76	0	38	0	0
T77	0	22	0	0
T78	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	104975	0	0
T5	17751	1368	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	1809	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	669	0	0
T34	0	2494	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	1104	0	0
T59	0	600	0	0
T68	0	1275	0	0
T76	0	1368	0	0
T77	0	484	0	0
T78	0	1326	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7907639	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17271	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	265	0	0
T27	6254	1	0	0
T32	1419	0	0	0
T59	0	9	0	0
T75	525	0	0	0
T99	0	26	0	0
T100	0	15	0	0
T101	0	12	0	0
T103	0	9	0	0
T142	414	0	0	0
T143	421	0	0	0
T144	522	0	0	0
T149	0	11	0	0
T177	422	0	0	0
T178	524	0	0	0
T280	0	8	0	0
T281	0	6	0	0
T282	0	5	0	0
T283	502	0	0	0
T284	438	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	92029	0	0
T5	17751	2506	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	2233	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T34	0	2991	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	571	0	0
T68	0	1897	0	0
T76	0	2586	0	0
T77	0	432	0	0
T78	0	2063	0	0
T277	0	335	0	0
T278	0	710	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	968	0	0
T5	17751	24	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	27	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T34	0	29	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	16	0	0
T68	0	25	0	0
T76	0	19	0	0
T77	0	11	0	0
T78	0	26	0	0
T277	0	10	0	0
T278	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7430462	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	10673	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7432600	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	10675	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1490	0	0
T5	17751	24	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	27	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	12	0	0
T34	0	29	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	16	0	0
T59	0	9	0	0
T68	0	25	0	0
T76	0	19	0	0
T77	0	11	0	0
T78	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1485	0	0
T5	17751	24	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	27	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	12	0	0
T34	0	29	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	16	0	0
T59	0	9	0	0
T68	0	25	0	0
T76	0	19	0	0
T77	0	11	0	0
T78	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	968	0	0
T5	17751	24	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	27	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T34	0	29	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	16	0	0
T68	0	25	0	0
T76	0	19	0	0
T77	0	11	0	0
T78	0	26	0	0
T277	0	10	0	0
T278	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	968	0	0
T5	17751	24	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	27	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T34	0	29	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	16	0	0
T68	0	25	0	0
T76	0	19	0	0
T77	0	11	0	0
T78	0	26	0	0
T277	0	10	0	0
T278	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	90917	0	0
T5	17751	2480	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	2201	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T34	0	2953	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	555	0	0
T68	0	1872	0	0
T76	0	2563	0	0
T77	0	421	0	0
T78	0	2036	0	0
T277	0	323	0	0
T278	0	698	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	822	0	0
T5	17751	22	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	22	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T34	0	20	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	16	0	0
T68	0	25	0	0
T76	0	15	0	0
T77	0	11	0	0
T78	0	25	0	0
T277	0	8	0	0
T278	0	10	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T3,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T5,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T2,T14,T15
1	1	Covered	T3,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T3,T54,T98
1	0	Covered	T84,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T7
0	1	Covered	T3,T5,T7
1	0	Covered	T85

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T5,T7
1	-	Covered	T3,T5,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T5,T7
DetectSt	168	Covered	T3,T5,T7
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T5,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T5,T7
DebounceSt->IdleSt	163	Covered	T3,T7,T35
DetectSt->IdleSt	186	Covered	T3,T54,T98
DetectSt->StableSt	191	Covered	T3,T5,T7
IdleSt->DebounceSt	148	Covered	T3,T5,T7
StableSt->IdleSt	206	Covered	T3,T5,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T5,T7
0	1	Covered	T3,T5,T7
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T5,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T7,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T3,T54,T98
DetectSt	-	-	-	-	0	1	-	Covered	T3,T5,T7
DetectSt	-	-	-	-	0	0	-	Covered	T3,T5,T7
StableSt	-	-	-	-	-	-	1	Covered	T3,T5,T7
StableSt	-	-	-	-	-	-	0	Covered	T3,T5,T7
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	846	0	0
CntIncr_A	8545490	43208	0	0
CntNoWrap_A	8545490	7909768	0	0
DetectStDropOut_A	8545490	60	0	0
DetectedOut_A	8545490	15558	0	0
DetectedPulseOut_A	8545490	335	0	0
DisabledIdleSt_A	8545490	7541460	0	0
DisabledNoDetection_A	8545490	7543149	0	0
EnterDebounceSt_A	8545490	448	0	0
EnterDetectSt_A	8545490	399	0	0
EnterStableSt_A	8545490	335	0	0
PulseIsPulse_A	8545490	335	0	0
StayInStableSt	8545490	15188	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	298	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	846	0	0
T3	75299	19	0	0
T5	17751	6	0	0
T6	1738	0	0	0
T7	29126	17	0	0
T9	0	10	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	26	0	0
T34	0	6	0	0
T35	0	9	0	0
T48	0	4	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	2	0	0
T76	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	43208	0	0
T3	75299	887	0	0
T5	17751	195	0	0
T6	1738	0	0	0
T7	29126	1188	0	0
T9	0	385	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	1534	0	0
T34	0	213	0	0
T35	0	1470	0	0
T48	0	226	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	73	0	0
T76	0	150	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7909768	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69560	0	0
T4	507	106	0	0
T5	17751	17313	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	60	0	0
T3	75299	5	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T54	0	1	0	0
T55	401	0	0	0
T56	570	0	0	0
T98	0	5	0	0
T102	0	6	0	0
T105	0	1	0	0
T124	0	2	0	0
T174	0	8	0	0
T285	0	4	0	0
T286	0	10	0	0
T287	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	15558	0	0
T3	75299	203	0	0
T5	17751	223	0	0
T6	1738	0	0	0
T7	29126	126	0	0
T9	0	187	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	263	0	0
T34	0	190	0	0
T35	0	29	0	0
T48	0	196	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	29	0	0
T76	0	273	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	335	0	0
T3	75299	3	0	0
T5	17751	3	0	0
T6	1738	0	0	0
T7	29126	8	0	0
T9	0	5	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	13	0	0
T34	0	3	0	0
T35	0	3	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	1	0	0
T76	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7541460	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	63946	0	0
T4	507	106	0	0
T5	17751	14815	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7543149	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	63962	0	0
T4	507	107	0	0
T5	17751	14818	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	448	0	0
T3	75299	11	0	0
T5	17751	3	0	0
T6	1738	0	0	0
T7	29126	9	0	0
T9	0	5	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	13	0	0
T34	0	3	0	0
T35	0	6	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	1	0	0
T76	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	399	0	0
T3	75299	8	0	0
T5	17751	3	0	0
T6	1738	0	0	0
T7	29126	8	0	0
T9	0	5	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	13	0	0
T34	0	3	0	0
T35	0	3	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	1	0	0
T76	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	335	0	0
T3	75299	3	0	0
T5	17751	3	0	0
T6	1738	0	0	0
T7	29126	8	0	0
T9	0	5	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	13	0	0
T34	0	3	0	0
T35	0	3	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	1	0	0
T76	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	335	0	0
T3	75299	3	0	0
T5	17751	3	0	0
T6	1738	0	0	0
T7	29126	8	0	0
T9	0	5	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	13	0	0
T34	0	3	0	0
T35	0	3	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	1	0	0
T76	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	15188	0	0
T3	75299	200	0	0
T5	17751	220	0	0
T6	1738	0	0	0
T7	29126	118	0	0
T9	0	182	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	250	0	0
T34	0	187	0	0
T35	0	26	0	0
T48	0	194	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	28	0	0
T76	0	270	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	298	0	0
T3	75299	3	0	0
T5	17751	3	0	0
T6	1738	0	0	0
T7	29126	8	0	0
T9	0	5	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	13	0	0
T34	0	3	0	0
T35	0	3	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	1	0	0
T76	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T9,T27
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T27
1	0	Covered	T5,T9,T27
1	1	Covered	T5,T9,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T27
0	1	Covered	T59,T68,T99
1	0	Covered	T68,T278,T288

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T27
0	1	Covered	T5,T9,T27
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T9,T27
1	-	Covered	T5,T9,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T9,T27
DetectSt	168	Covered	T5,T9,T27
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T5,T9,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T9,T27
DebounceSt->IdleSt	163	Covered	T84,T60
DetectSt->IdleSt	186	Covered	T59,T68,T278
DetectSt->StableSt	191	Covered	T5,T9,T27
IdleSt->DebounceSt	148	Covered	T5,T9,T27
StableSt->IdleSt	206	Covered	T5,T9,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T9,T27
0	1	Covered	T5,T9,T27
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T27
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T9,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T9,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T9,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T9,T27
DetectSt	-	-	-	-	1	-	-	Covered	T59,T68,T278
DetectSt	-	-	-	-	0	1	-	Covered	T5,T9,T27
DetectSt	-	-	-	-	0	0	-	Covered	T5,T9,T27
StableSt	-	-	-	-	-	-	1	Covered	T5,T9,T27
StableSt	-	-	-	-	-	-	0	Covered	T5,T9,T27
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	2786	0	0
CntIncr_A	8545490	92206	0	0
CntNoWrap_A	8545490	7907828	0	0
DetectStDropOut_A	8545490	341	0	0
DetectedOut_A	8545490	74085	0	0
DetectedPulseOut_A	8545490	854	0	0
DisabledIdleSt_A	8545490	7441642	0	0
DisabledNoDetection_A	8545490	7443815	0	0
EnterDebounceSt_A	8545490	1395	0	0
EnterDetectSt_A	8545490	1391	0	0
EnterStableSt_A	8545490	854	0	0
PulseIsPulse_A	8545490	854	0	0
StayInStableSt	8545490	73120	0	0
gen_high_event_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	743	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2786	0	0
T5	17751	14	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	4	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	44	0	0
T34	0	26	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	24	0	0
T59	0	10	0	0
T68	0	52	0	0
T76	0	50	0	0
T77	0	14	0	0
T78	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	92206	0	0
T5	17751	602	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	114	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	770	0	0
T34	0	1144	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	960	0	0
T59	0	331	0	0
T68	0	1788	0	0
T76	0	1800	0	0
T77	0	336	0	0
T78	0	255	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7907828	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17305	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	341	0	0
T23	496	0	0	0
T51	742	0	0	0
T52	1977	0	0	0
T59	5970	5	0	0
T61	1151	0	0	0
T68	7541	7	0	0
T69	423	0	0	0
T70	405	0	0	0
T71	186607	0	0	0
T77	14224	0	0	0
T99	0	23	0	0
T100	0	20	0	0
T101	0	26	0	0
T149	0	8	0	0
T289	0	15	0	0
T290	0	13	0	0
T291	0	9	0	0
T292	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	74085	0	0
T5	17751	243	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	187	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	1287	0	0
T34	0	1016	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	210	0	0
T76	0	1321	0	0
T77	0	245	0	0
T78	0	135	0	0
T277	0	215	0	0
T279	0	2861	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	854	0	0
T5	17751	7	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	22	0	0
T34	0	13	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	12	0	0
T76	0	25	0	0
T77	0	7	0	0
T78	0	5	0	0
T277	0	12	0	0
T279	0	25	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7441642	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	12040	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7443815	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	12044	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1395	0	0
T5	17751	7	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	22	0	0
T34	0	13	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	12	0	0
T59	0	5	0	0
T68	0	26	0	0
T76	0	25	0	0
T77	0	7	0	0
T78	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1391	0	0
T5	17751	7	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	22	0	0
T34	0	13	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	12	0	0
T59	0	5	0	0
T68	0	26	0	0
T76	0	25	0	0
T77	0	7	0	0
T78	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	854	0	0
T5	17751	7	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	22	0	0
T34	0	13	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	12	0	0
T76	0	25	0	0
T77	0	7	0	0
T78	0	5	0	0
T277	0	12	0	0
T279	0	25	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	854	0	0
T5	17751	7	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	22	0	0
T34	0	13	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	12	0	0
T76	0	25	0	0
T77	0	7	0	0
T78	0	5	0	0
T277	0	12	0	0
T279	0	25	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	73120	0	0
T5	17751	236	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	185	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	1265	0	0
T34	0	1000	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	198	0	0
T76	0	1293	0	0
T77	0	238	0	0
T78	0	130	0	0
T277	0	202	0	0
T279	0	2826	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	743	0	0
T5	17751	7	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	22	0	0
T34	0	10	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	12	0	0
T76	0	22	0	0
T77	0	7	0	0
T78	0	5	0	0
T277	0	11	0	0
T279	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T7,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T3,T7,T47

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T7,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T2,T14,T15
1	1	Covered	T3,T7,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T47
0	1	Covered	T47,T35,T293
1	0	Covered	T84,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T9
0	1	Covered	T3,T7,T9
1	0	Covered	T86,T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T9
1	-	Covered	T3,T7,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T47
DetectSt	168	Covered	T3,T7,T47
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T47
DebounceSt->IdleSt	163	Covered	T3,T47,T27
DetectSt->IdleSt	186	Covered	T47,T35,T293
DetectSt->StableSt	191	Covered	T3,T7,T9
IdleSt->DebounceSt	148	Covered	T3,T7,T47
StableSt->IdleSt	206	Covered	T3,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T47
0	1	Covered	T3,T7,T47
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T47
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T47,T27
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T47
DetectSt	-	-	-	-	1	-	-	Covered	T47,T35,T293
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T9
DetectSt	-	-	-	-	0	0	-	Covered	T3,T7,T47
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T9
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	869	0	0
CntIncr_A	8545490	49902	0	0
CntNoWrap_A	8545490	7909745	0	0
DetectStDropOut_A	8545490	78	0	0
DetectedOut_A	8545490	14628	0	0
DetectedPulseOut_A	8545490	329	0	0
DisabledIdleSt_A	8545490	7538770	0	0
DisabledNoDetection_A	8545490	7540464	0	0
EnterDebounceSt_A	8545490	459	0	0
EnterDetectSt_A	8545490	411	0	0
EnterStableSt_A	8545490	329	0	0
PulseIsPulse_A	8545490	329	0	0
StayInStableSt	8545490	14262	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	288	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	869	0	0
T3	75299	13	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	10	0	0
T9	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	1	0	0
T33	0	3	0	0
T34	0	2	0	0
T35	0	25	0	0
T47	0	7	0	0
T48	0	6	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	49902	0	0
T3	75299	965	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	750	0	0
T9	0	71	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	11	0	0
T33	0	208	0	0
T34	0	79	0	0
T35	0	3713	0	0
T47	0	447	0	0
T48	0	522	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	178	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7909745	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69566	0	0
T4	507	106	0	0
T5	17751	17319	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	78	0	0
T8	1170	0	0	0
T9	18861	0	0	0
T10	483	0	0	0
T11	1048	0	0	0
T35	0	12	0	0
T47	6042	3	0	0
T72	507	0	0	0
T73	522	0	0	0
T74	524	0	0	0
T131	448	0	0	0
T135	430	0	0	0
T174	0	3	0	0
T286	0	6	0	0
T293	0	12	0	0
T294	0	6	0	0
T295	0	4	0	0
T296	0	2	0	0
T297	0	3	0	0
T298	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	14628	0	0
T3	75299	49	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	23	0	0
T9	0	44	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	28	0	0
T34	0	55	0	0
T48	0	63	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	105	0	0
T129	0	58	0	0
T211	0	72	0	0
T240	0	483	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	329	0	0
T3	75299	6	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	5	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	2	0	0
T129	0	2	0	0
T211	0	2	0	0
T240	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7538770	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	63952	0	0
T4	507	106	0	0
T5	17751	17076	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7540464	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	63968	0	0
T4	507	107	0	0
T5	17751	17081	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	459	0	0
T3	75299	7	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	5	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T35	0	13	0	0
T47	0	4	0	0
T48	0	4	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	411	0	0
T3	75299	6	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	5	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	12	0	0
T47	0	3	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	2	0	0
T211	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	329	0	0
T3	75299	6	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	5	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	2	0	0
T129	0	2	0	0
T211	0	2	0	0
T240	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	329	0	0
T3	75299	6	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	5	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	2	0	0
T129	0	2	0	0
T211	0	2	0	0
T240	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	14262	0	0
T3	75299	43	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	18	0	0
T9	0	43	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	27	0	0
T34	0	54	0	0
T48	0	61	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	103	0	0
T129	0	56	0	0
T211	0	70	0	0
T240	0	475	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	288	0	0
T3	75299	6	0	0
T5	17751	0	0	0
T6	1738	0	0	0
T7	29126	5	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T48	0	2	0	0
T55	401	0	0	0
T56	570	0	0	0
T76	0	2	0	0
T129	0	2	0	0
T211	0	2	0	0
T240	0	8	0	0