Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T9,T27
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T5,T9,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T9,T27
1	0	Covered	T5,T9,T27
1	1	Covered	T5,T9,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T27
0	1	Covered	T59,T99,T100
1	0	Covered	T280,T299,T103

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T27
0	1	Covered	T5,T9,T27
1	0	Covered	T89

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T9,T27
1	-	Covered	T5,T9,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T9,T27
DetectSt	168	Covered	T5,T9,T27
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T5,T9,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T9,T27
DebounceSt->IdleSt	163	Covered	T84,T60
DetectSt->IdleSt	186	Covered	T59,T280,T299
DetectSt->StableSt	191	Covered	T5,T9,T27
IdleSt->DebounceSt	148	Covered	T5,T9,T27
StableSt->IdleSt	206	Covered	T5,T9,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T9,T27
0	1	Covered	T5,T9,T27
0	0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T9,T27
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T5,T9,T27
IdleSt	0	-	-	-	-	-	-	Covered	T5,T9,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T9,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T84,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T9,T27
DetectSt	-	-	-	-	1	-	-	Covered	T59,T280,T299
DetectSt	-	-	-	-	0	1	-	Covered	T5,T9,T27
DetectSt	-	-	-	-	0	0	-	Covered	T5,T9,T27
StableSt	-	-	-	-	-	-	1	Covered	T5,T9,T27
StableSt	-	-	-	-	-	-	0	Covered	T5,T9,T27
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	2622	0	0
CntIncr_A	8545490	88597	0	0
CntNoWrap_A	8545490	7907992	0	0
DetectStDropOut_A	8545490	273	0	0
DetectedOut_A	8545490	81825	0	0
DetectedPulseOut_A	8545490	854	0	0
DisabledIdleSt_A	8545490	7439256	0	0
DisabledNoDetection_A	8545490	7441420	0	0
EnterDebounceSt_A	8545490	1313	0	0
EnterDetectSt_A	8545490	1309	0	0
EnterStableSt_A	8545490	854	0	0
PulseIsPulse_A	8545490	854	0	0
StayInStableSt	8545490	80852	0	0
gen_high_event_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	734	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	2622	0	0
T5	17751	50	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	18	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	16	0	0
T34	0	28	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	50	0	0
T59	0	6	0	0
T68	0	30	0	0
T76	0	24	0	0
T77	0	24	0	0
T78	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	88597	0	0
T5	17751	1525	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	594	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	280	0	0
T34	0	784	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	1500	0	0
T59	0	198	0	0
T68	0	870	0	0
T76	0	1056	0	0
T77	0	876	0	0
T78	0	588	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7907992	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	17269	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	273	0	0
T23	496	0	0	0
T51	742	0	0	0
T52	1977	0	0	0
T59	5970	3	0	0
T61	1151	0	0	0
T68	7541	0	0	0
T69	423	0	0	0
T70	405	0	0	0
T71	186607	0	0	0
T77	14224	0	0	0
T99	0	14	0	0
T100	0	14	0	0
T101	0	26	0	0
T149	0	12	0	0
T235	0	6	0	0
T275	0	8	0	0
T282	0	14	0	0
T289	0	6	0	0
T300	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	81825	0	0
T5	17751	2302	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	433	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	176	0	0
T34	0	1484	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	1991	0	0
T68	0	189	0	0
T76	0	147	0	0
T77	0	1544	0	0
T78	0	353	0	0
T277	0	252	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	854	0	0
T5	17751	25	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	9	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	8	0	0
T34	0	14	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	25	0	0
T68	0	15	0	0
T76	0	12	0	0
T77	0	12	0	0
T78	0	12	0	0
T277	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7439256	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69579	0	0
T4	507	106	0	0
T5	17751	10825	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7441420	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	10825	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1313	0	0
T5	17751	25	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	9	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	8	0	0
T34	0	14	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	25	0	0
T59	0	3	0	0
T68	0	15	0	0
T76	0	12	0	0
T77	0	12	0	0
T78	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	1309	0	0
T5	17751	25	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	9	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	8	0	0
T34	0	14	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	25	0	0
T59	0	3	0	0
T68	0	15	0	0
T76	0	12	0	0
T77	0	12	0	0
T78	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	854	0	0
T5	17751	25	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	9	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	8	0	0
T34	0	14	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	25	0	0
T68	0	15	0	0
T76	0	12	0	0
T77	0	12	0	0
T78	0	12	0	0
T277	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	854	0	0
T5	17751	25	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	9	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	8	0	0
T34	0	14	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	25	0	0
T68	0	15	0	0
T76	0	12	0	0
T77	0	12	0	0
T78	0	12	0	0
T277	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	80852	0	0
T5	17751	2273	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	424	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	168	0	0
T34	0	1466	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	1966	0	0
T68	0	174	0	0
T76	0	135	0	0
T77	0	1531	0	0
T78	0	341	0	0
T277	0	247	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	734	0	0
T5	17751	21	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	9	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T27	0	8	0	0
T34	0	10	0	0
T55	401	0	0	0
T56	570	0	0	0
T57	277536	0	0	0
T58	0	25	0	0
T68	0	15	0	0
T76	0	12	0	0
T77	0	11	0	0
T78	0	12	0	0
T277	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T5,T7
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T5,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T1,T2	VC_COV_UNR
1	Covered	T3,T5,T47

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T3,T5,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Covered	T2,T14,T15
1	1	Covered	T3,T5,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T47
0	1	Covered	T240,T98,T122
1	0	Covered	T84,T60

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T47
0	1	Covered	T3,T5,T47
1	0	Covered	T84,T60

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T5,T47
1	-	Covered	T3,T5,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T5,T47
DetectSt	168	Covered	T3,T5,T47
IdleSt	163	Covered	T4,T1,T2
StableSt	191	Covered	T3,T5,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T5,T47
DebounceSt->IdleSt	163	Covered	T3,T47,T33
DetectSt->IdleSt	186	Covered	T240,T98,T301
DetectSt->StableSt	191	Covered	T3,T5,T47
IdleSt->DebounceSt	148	Covered	T3,T5,T47
StableSt->IdleSt	206	Covered	T3,T5,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T5,T47
0	1	Covered	T3,T5,T47
0	0	Excluded	T4,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T47
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T5,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T84,T60
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T5,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T47,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T5,T47
DetectSt	-	-	-	-	1	-	-	Covered	T240,T98,T122
DetectSt	-	-	-	-	0	1	-	Covered	T3,T5,T47
DetectSt	-	-	-	-	0	0	-	Covered	T3,T5,T47
StableSt	-	-	-	-	-	-	1	Covered	T3,T5,T47
StableSt	-	-	-	-	-	-	0	Covered	T3,T5,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T1,T2
0	Covered	T4,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8545490	909	0	0
CntIncr_A	8545490	51059	0	0
CntNoWrap_A	8545490	7909705	0	0
DetectStDropOut_A	8545490	35	0	0
DetectedOut_A	8545490	17660	0	0
DetectedPulseOut_A	8545490	387	0	0
DisabledIdleSt_A	8545490	7530036	0	0
DisabledNoDetection_A	8545490	7531718	0	0
EnterDebounceSt_A	8545490	483	0	0
EnterDetectSt_A	8545490	428	0	0
EnterStableSt_A	8545490	387	0	0
PulseIsPulse_A	8545490	387	0	0
StayInStableSt	8545490	17243	0	0
gen_high_level_sva.HighLevelEvent_A	8545490	7912987	0	0
gen_not_sticky_sva.StableStDropOut_A	8545490	354	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	909	0	0
T3	75299	13	0	0
T5	17751	8	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	2	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	20	0	0
T34	0	8	0	0
T35	0	16	0	0
T47	0	21	0	0
T48	0	12	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	4	0	0
T211	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	51059	0	0
T3	75299	366	0	0
T5	17751	196	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	62	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	1278	0	0
T34	0	224	0	0
T35	0	2026	0	0
T47	0	1232	0	0
T48	0	964	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	126	0	0
T211	0	83	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7909705	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	69566	0	0
T4	507	106	0	0
T5	17751	17311	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	35	0	0
T53	636	0	0	0
T65	2322	0	0	0
T66	497	0	0	0
T98	0	2	0	0
T122	0	7	0	0
T240	24616	1	0	0
T241	906	0	0	0
T242	515	0	0	0
T243	1514	0	0	0
T267	0	2	0	0
T277	12873	0	0	0
T297	0	4	0	0
T302	0	4	0	0
T303	0	1	0	0
T304	0	2	0	0
T305	0	2	0	0
T306	0	2	0	0
T307	441	0	0	0
T308	514	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	17660	0	0
T3	75299	252	0	0
T5	17751	359	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	53	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	165	0	0
T34	0	312	0	0
T35	0	429	0	0
T47	0	119	0	0
T48	0	252	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	76	0	0
T211	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	387	0	0
T3	75299	6	0	0
T5	17751	4	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	9	0	0
T34	0	4	0	0
T35	0	7	0	0
T47	0	10	0	0
T48	0	5	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	2	0	0
T211	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7530036	0	0
T1	943	542	0	0
T2	6285	1343	0	0
T3	75299	63957	0	0
T4	507	106	0	0
T5	17751	15021	0	0
T12	613	212	0	0
T13	522	121	0	0
T14	1938	335	0	0
T15	27245	26043	0	0
T16	884	483	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7531718	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	63973	0	0
T4	507	107	0	0
T5	17751	15022	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	483	0	0
T3	75299	7	0	0
T5	17751	4	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	11	0	0
T34	0	4	0	0
T35	0	9	0	0
T47	0	11	0	0
T48	0	7	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	2	0	0
T211	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	428	0	0
T3	75299	6	0	0
T5	17751	4	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	9	0	0
T34	0	4	0	0
T35	0	7	0	0
T47	0	10	0	0
T48	0	5	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	2	0	0
T211	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	387	0	0
T3	75299	6	0	0
T5	17751	4	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	9	0	0
T34	0	4	0	0
T35	0	7	0	0
T47	0	10	0	0
T48	0	5	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	2	0	0
T211	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	387	0	0
T3	75299	6	0	0
T5	17751	4	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	9	0	0
T34	0	4	0	0
T35	0	7	0	0
T47	0	10	0	0
T48	0	5	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	2	0	0
T211	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	17243	0	0
T3	75299	246	0	0
T5	17751	353	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	52	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	156	0	0
T34	0	308	0	0
T35	0	422	0	0
T47	0	109	0	0
T48	0	247	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	74	0	0
T211	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	7912987	0	0
T1	943	543	0	0
T2	6285	1354	0	0
T3	75299	69609	0	0
T4	507	107	0	0
T5	17751	17324	0	0
T12	613	213	0	0
T13	522	122	0	0
T14	1938	338	0	0
T15	27245	26045	0	0
T16	884	484	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8545490	354	0	0
T3	75299	6	0	0
T5	17751	2	0	0
T6	1738	0	0	0
T7	29126	0	0	0
T9	0	1	0	0
T16	884	0	0	0
T17	405	0	0	0
T25	700	0	0	0
T26	602	0	0	0
T33	0	9	0	0
T34	0	4	0	0
T35	0	7	0	0
T47	0	10	0	0
T48	0	5	0	0
T55	401	0	0	0
T56	570	0	0	0
T58	0	2	0	0
T211	0	1	0	0