Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T10,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T24,T10,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T24,T10,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T24,T10,T25
1	0	Covered	T4,T1,T2
1	1	Covered	T24,T10,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T24,T10,T25
0	1	Covered	T24
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T24,T10,T25
0	1	Covered	T24,T10,T25
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T24,T10,T25
1	-	Covered	T24,T10,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T24,T10,T25
DetectSt	168	Covered	T24,T10,T25
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T24,T10,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T24,T10,T25
DebounceSt->IdleSt	163	Covered	T44,T46,T48
DetectSt->IdleSt	186	Covered	T24
DetectSt->StableSt	191	Covered	T24,T10,T25
IdleSt->DebounceSt	148	Covered	T24,T10,T25
StableSt->IdleSt	206	Covered	T24,T10,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T24,T10,T25
0	1	Covered	T24,T10,T25
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T10,T25
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T24,T10,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T24,T10,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T46,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T24,T10,T25
DetectSt	-	-	-	-	1	-	-	Covered	T24
DetectSt	-	-	-	-	0	1	-	Covered	T24,T10,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T24,T10,T25
StableSt	-	-	-	-	-	-	0	Covered	T24,T10,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	285	0	0
CntIncr_A	7138179	194575	0	0
CntNoWrap_A	7138179	6471766	0	0
DetectStDropOut_A	7138179	1	0	0
DetectedOut_A	7138179	880	0	0
DetectedPulseOut_A	7138179	129	0	0
DisabledIdleSt_A	7138179	6270872	0	0
DisabledNoDetection_A	7138179	6273206	0	0
EnterDebounceSt_A	7138179	159	0	0
EnterDetectSt_A	7138179	130	0	0
EnterStableSt_A	7138179	129	0	0
PulseIsPulse_A	7138179	129	0	0
StayInStableSt	7138179	751	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138179	7090	0	0
gen_low_level_sva.LowLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	129	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	285	0	0
T9	875	0	0	0
T10	4873	4	0	0
T11	848	0	0	0
T24	20701	4	0	0
T25	0	4	0	0
T43	0	2	0	0
T44	0	3	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	4	0	0
T48	0	5	0	0
T49	0	4	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	194575	0	0
T9	875	0	0	0
T10	4873	122	0	0
T11	848	0	0	0
T24	20701	120	0	0
T25	0	48	0	0
T43	0	57	0	0
T44	0	182	0	0
T45	0	10	0	0
T46	0	19979	0	0
T47	0	80	0	0
T48	0	114	0	0
T49	0	48	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471766	0	0
T1	21441	14653	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1	0	0
T9	875	0	0	0
T10	4873	0	0	0
T11	848	0	0	0
T24	20701	1	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	880	0	0
T9	875	0	0	0
T10	4873	5	0	0
T11	848	0	0	0
T24	20701	6	0	0
T25	0	14	0	0
T43	0	2	0	0
T44	0	8	0	0
T45	0	2	0	0
T46	0	6	0	0
T47	0	8	0	0
T48	0	8	0	0
T49	0	11	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	129	0	0
T9	875	0	0	0
T10	4873	2	0	0
T11	848	0	0	0
T24	20701	1	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6270872	0	0
T1	21441	14653	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6273206	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	159	0	0
T9	875	0	0	0
T10	4873	2	0	0
T11	848	0	0	0
T24	20701	2	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	3	0	0
T49	0	2	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	130	0	0
T9	875	0	0	0
T10	4873	2	0	0
T11	848	0	0	0
T24	20701	2	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	129	0	0
T9	875	0	0	0
T10	4873	2	0	0
T11	848	0	0	0
T24	20701	1	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	129	0	0
T9	875	0	0	0
T10	4873	2	0	0
T11	848	0	0	0
T24	20701	1	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	751	0	0
T9	875	0	0	0
T10	4873	3	0	0
T11	848	0	0	0
T24	20701	5	0	0
T25	0	12	0	0
T43	0	1	0	0
T44	0	7	0	0
T45	0	1	0	0
T46	0	5	0	0
T47	0	6	0	0
T48	0	6	0	0
T49	0	9	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	7090	0	0
T1	21441	46	0	0
T2	13902	31	0	0
T3	16928	12	0	0
T4	202500	4	0	0
T5	797	0	0	0
T13	496	8	0	0
T14	527	3	0	0
T15	492	4	0	0
T16	7883	4	0	0
T17	504	6	0	0
T18	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	129	0	0
T9	875	0	0	0
T10	4873	2	0	0
T11	848	0	0	0
T24	20701	1	0	0
T25	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T55	525	0	0	0
T56	525	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T10,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T23
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T10,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T23
0	1	Covered	T23,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T23
0	1	Unreachable
1	0	Covered	T1,T10,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T23
DetectSt	168	Covered	T1,T10,T23
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T10,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T23
DebounceSt->IdleSt	163	Covered	T71,T77,T111
DetectSt->IdleSt	186	Covered	T23,T84,T85
DetectSt->StableSt	191	Covered	T1,T10,T23
IdleSt->DebounceSt	148	Covered	T1,T10,T23
StableSt->IdleSt	206	Covered	T1,T10,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T23
0	1	Covered	T1,T10,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T23
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T111,T112
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T23
DetectSt	-	-	-	-	1	-	-	Covered	T23,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T23
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	150	0	0
CntIncr_A	7138179	132751	0	0
CntNoWrap_A	7138179	6471901	0	0
DetectStDropOut_A	7138179	13	0	0
DetectedOut_A	7138179	411787	0	0
DetectedPulseOut_A	7138179	51	0	0
DisabledIdleSt_A	7138179	5667368	0	0
DisabledNoDetection_A	7138179	5669757	0	0
EnterDebounceSt_A	7138179	86	0	0
EnterDetectSt_A	7138179	64	0	0
EnterStableSt_A	7138179	51	0	0
PulseIsPulse_A	7138179	51	0	0
StayInStableSt	7138179	411736	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138179	7090	0	0
gen_low_level_sva.LowLevelEvent_A	7138179	6474440	0	0
gen_sticky_sva.StableStDropOut_A	7138179	256319	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	150	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	6	0	0
T31	0	2	0	0
T34	0	2	0	0
T71	0	2	0	0
T72	0	4	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	132751	0	0
T1	21441	81	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	115	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	258	0	0
T31	0	98	0	0
T34	0	49	0	0
T71	0	76	0	0
T72	0	94	0	0
T73	0	52797	0	0
T74	0	18271	0	0
T75	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471901	0	0
T1	21441	14651	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	13	0	0
T23	2391	2	0	0
T29	10746	0	0	0
T38	8035	0	0	0
T61	2948	0	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	2350	0	0	0
T111	0	3	0	0
T113	0	2	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	2	0	0
T117	1059	0	0	0
T118	410	0	0	0
T119	425	0	0	0
T120	427	0	0	0
T121	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	411787	0	0
T1	21441	506	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	580	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	175	0	0
T31	0	67	0	0
T34	0	104	0	0
T72	0	371	0	0
T73	0	235343	0	0
T74	0	53018	0	0
T75	0	165	0	0
T80	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	51	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T80	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5667368	0	0
T1	21441	13953	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5669757	0	0
T1	21441	13972	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	86	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	3	0	0
T31	0	1	0	0
T34	0	1	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	64	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	3	0	0
T31	0	1	0	0
T34	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T80	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	51	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T80	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	51	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T80	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	411736	0	0
T1	21441	505	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	578	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	174	0	0
T31	0	66	0	0
T34	0	103	0	0
T72	0	369	0	0
T73	0	235341	0	0
T74	0	53017	0	0
T75	0	164	0	0
T80	0	105	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	7090	0	0
T1	21441	46	0	0
T2	13902	31	0	0
T3	16928	12	0	0
T4	202500	4	0	0
T5	797	0	0	0
T13	496	8	0	0
T14	527	3	0	0
T15	492	4	0	0
T16	7883	4	0	0
T17	504	6	0	0
T18	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	256319	0	0
T1	21441	98	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	604	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	109	0	0
T31	0	27	0	0
T34	0	156942	0	0
T72	0	161	0	0
T73	0	400	0	0
T74	0	65	0	0
T75	0	32	0	0
T80	0	301	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T10,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T23
1	0	Covered	T4,T1,T13
1	1	Covered	T1,T10,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T23
0	1	Covered	T72,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T23
0	1	Unreachable
1	0	Covered	T1,T10,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T23
DetectSt	168	Covered	T1,T10,T23
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T10,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T23
DebounceSt->IdleSt	163	Covered	T10,T72,T73
DetectSt->IdleSt	186	Covered	T72,T82,T83
DetectSt->StableSt	191	Covered	T1,T10,T23
IdleSt->DebounceSt	148	Covered	T1,T10,T23
StableSt->IdleSt	206	Covered	T1,T10,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T23
0	1	Covered	T1,T10,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T23
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T72,T73
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T23
DetectSt	-	-	-	-	1	-	-	Covered	T72,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T10,T23
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	162	0	0
CntIncr_A	7138179	65635	0	0
CntNoWrap_A	7138179	6471889	0	0
DetectStDropOut_A	7138179	11	0	0
DetectedOut_A	7138179	32326	0	0
DetectedPulseOut_A	7138179	49	0	0
DisabledIdleSt_A	7138179	5667368	0	0
DisabledNoDetection_A	7138179	5669757	0	0
EnterDebounceSt_A	7138179	102	0	0
EnterDetectSt_A	7138179	60	0	0
EnterStableSt_A	7138179	49	0	0
PulseIsPulse_A	7138179	49	0	0
StayInStableSt	7138179	32277	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_sticky_sva.StableStDropOut_A	7138179	571251	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	162	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	7	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	2	0	0
T31	0	2	0	0
T34	0	2	0	0
T71	0	2	0	0
T72	0	5	0	0
T73	0	5	0	0
T74	0	2	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	65635	0	0
T1	21441	56	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	114	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	93	0	0
T31	0	50	0	0
T34	0	11	0	0
T71	0	82	0	0
T72	0	192	0	0
T73	0	295	0	0
T74	0	90	0	0
T75	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471889	0	0
T1	21441	14651	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	11	0	0
T46	20541	0	0	0
T70	5566	0	0	0
T72	1107	1	0	0
T73	289830	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T105	435	0	0	0
T106	497	0	0	0
T111	0	1	0	0
T114	0	1	0	0
T116	0	1	0	0
T122	0	4	0	0
T123	869	0	0	0
T124	439	0	0	0
T125	522	0	0	0
T126	882	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	32326	0	0
T1	21441	382	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	196	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	420	0	0
T31	0	27	0	0
T34	0	54	0	0
T71	0	170	0	0
T72	0	261	0	0
T73	0	318	0	0
T74	0	395	0	0
T75	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	49	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5667368	0	0
T1	21441	13953	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5669757	0	0
T1	21441	13972	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	102	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	6	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T71	0	1	0	0
T72	0	3	0	0
T73	0	4	0	0
T74	0	1	0	0
T75	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	60	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	49	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	49	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	32277	0	0
T1	21441	381	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	195	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	419	0	0
T31	0	26	0	0
T34	0	53	0	0
T71	0	169	0	0
T72	0	260	0	0
T73	0	317	0	0
T74	0	394	0	0
T75	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	571251	0	0
T1	21441	249	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	352	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	110	0	0
T31	0	104	0	0
T34	0	157030	0	0
T71	0	80	0	0
T72	0	104	0	0
T73	0	287503	0	0
T74	0	70873	0	0
T75	0	219	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T10,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T23,T71

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T23
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T10,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T71
0	1	Covered	T1,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T23,T71
0	1	Unreachable
1	0	Covered	T1,T23,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T23
DetectSt	168	Covered	T1,T23,T71
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T23,T71

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T23,T71
DebounceSt->IdleSt	163	Covered	T1,T10,T75
DetectSt->IdleSt	186	Covered	T1,T80,T81
DetectSt->StableSt	191	Covered	T1,T23,T71
IdleSt->DebounceSt	148	Covered	T1,T10,T23
StableSt->IdleSt	206	Covered	T1,T23,T71

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T23
0	1	Covered	T1,T10,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T23,T71
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T23,T71
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T10,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T23
DetectSt	-	-	-	-	1	-	-	Covered	T1,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T1,T23,T71
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T23,T71
StableSt	-	-	-	-	-	-	0	Covered	T1,T23,T71
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	144	0	0
CntIncr_A	7138179	220645	0	0
CntNoWrap_A	7138179	6471907	0	0
DetectStDropOut_A	7138179	5	0	0
DetectedOut_A	7138179	82746	0	0
DetectedPulseOut_A	7138179	49	0	0
DisabledIdleSt_A	7138179	5667368	0	0
DisabledNoDetection_A	7138179	5669757	0	0
EnterDebounceSt_A	7138179	90	0	0
EnterDetectSt_A	7138179	54	0	0
EnterStableSt_A	7138179	49	0	0
PulseIsPulse_A	7138179	49	0	0
StayInStableSt	7138179	82697	0	0
gen_high_event_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_sticky_sva.StableStDropOut_A	7138179	496903	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	144	0	0
T1	21441	7	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	2	0	0
T31	0	2	0	0
T34	0	3	0	0
T71	0	2	0	0
T72	0	4	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	220645	0	0
T1	21441	216	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	392	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	21	0	0
T31	0	59	0	0
T34	0	157065	0	0
T71	0	81	0	0
T72	0	54	0	0
T73	0	130	0	0
T74	0	34	0	0
T75	0	170	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471907	0	0
T1	21441	14646	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T127	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	82746	0	0
T1	21441	57	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	156	0	0
T31	0	31	0	0
T71	0	228	0	0
T72	0	295	0	0
T73	0	739	0	0
T74	0	117	0	0
T83	0	23	0	0
T109	0	264	0	0
T110	0	448	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	49	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T83	0	1	0	0
T109	0	2	0	0
T110	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5667368	0	0
T1	21441	13953	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5669757	0	0
T1	21441	13972	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	90	0	0
T1	21441	4	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T10	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T34	0	3	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T75	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	54	0	0
T1	21441	3	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T80	0	1	0	0
T109	0	2	0	0
T110	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	49	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T83	0	1	0	0
T109	0	2	0	0
T110	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	49	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	1	0	0
T31	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	2	0	0
T74	0	1	0	0
T83	0	1	0	0
T109	0	2	0	0
T110	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	82697	0	0
T1	21441	56	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	155	0	0
T31	0	30	0	0
T71	0	227	0	0
T72	0	293	0	0
T73	0	737	0	0
T74	0	116	0	0
T83	0	22	0	0
T109	0	262	0	0
T110	0	447	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	496903	0	0
T1	21441	178	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T23	0	460	0	0
T31	0	112	0	0
T71	0	37	0	0
T72	0	294	0	0
T73	0	287693	0	0
T74	0	71215	0	0
T83	0	274	0	0
T109	0	185	0	0
T110	0	272	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T36,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T36,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T36,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T36,T25
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T36,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T36,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T36,T34
0	1	Covered	T34,T128,T129
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T36,T34
1	-	Covered	T34,T128,T129

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T36,T34
DetectSt	168	Covered	T1,T36,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T36,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T36,T34
DebounceSt->IdleSt	163	Covered	T77,T130,T78
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T36,T34
IdleSt->DebounceSt	148	Covered	T1,T36,T34
StableSt->IdleSt	206	Covered	T1,T34,T128

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T36,T34
0	1	Covered	T1,T36,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T36,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T36,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T36,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T130
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T36,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T36,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T34,T128,T129
StableSt	-	-	-	-	-	-	0	Covered	T1,T36,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	69	0	0
CntIncr_A	7138179	1967	0	0
CntNoWrap_A	7138179	6471982	0	0
DetectStDropOut_A	7138179	0	0	0
DetectedOut_A	7138179	3099	0	0
DetectedPulseOut_A	7138179	33	0	0
DisabledIdleSt_A	7138179	6452164	0	0
DisabledNoDetection_A	7138179	6454500	0	0
EnterDebounceSt_A	7138179	36	0	0
EnterDetectSt_A	7138179	33	0	0
EnterStableSt_A	7138179	33	0	0
PulseIsPulse_A	7138179	33	0	0
StayInStableSt	7138179	3047	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	69	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T77	0	1	0	0
T80	0	2	0	0
T110	0	2	0	0
T128	0	6	0	0
T129	0	4	0	0
T131	0	4	0	0
T132	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1967	0	0
T1	21441	57	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	31	0	0
T36	0	96	0	0
T77	0	16	0	0
T80	0	93	0	0
T110	0	22	0	0
T128	0	175	0	0
T129	0	36	0	0
T131	0	24	0	0
T132	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471982	0	0
T1	21441	14651	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3099	0	0
T1	21441	141	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	11	0	0
T36	0	112	0	0
T80	0	274	0	0
T110	0	65	0	0
T128	0	140	0	0
T129	0	109	0	0
T131	0	151	0	0
T132	0	24	0	0
T133	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	33	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T80	0	1	0	0
T110	0	1	0	0
T128	0	3	0	0
T129	0	2	0	0
T131	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6452164	0	0
T1	21441	14071	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6454500	0	0
T1	21441	14089	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	36	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T77	0	1	0	0
T80	0	1	0	0
T110	0	1	0	0
T128	0	3	0	0
T129	0	2	0	0
T131	0	2	0	0
T132	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	33	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T80	0	1	0	0
T110	0	1	0	0
T128	0	3	0	0
T129	0	2	0	0
T131	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	33	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T80	0	1	0	0
T110	0	1	0	0
T128	0	3	0	0
T129	0	2	0	0
T131	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	33	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T80	0	1	0	0
T110	0	1	0	0
T128	0	3	0	0
T129	0	2	0	0
T131	0	2	0	0
T132	0	1	0	0
T133	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3047	0	0
T1	21441	139	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	10	0	0
T36	0	110	0	0
T80	0	272	0	0
T110	0	64	0	0
T128	0	135	0	0
T129	0	106	0	0
T131	0	148	0	0
T132	0	23	0	0
T133	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	14	0	0
T34	291233	1	0	0
T77	6257	0	0	0
T110	0	1	0	0
T128	35239	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T137	1850	0	0	0
T138	15616	0	0	0
T139	496	0	0	0
T140	404	0	0	0
T141	6158	0	0	0
T142	444	0	0	0
T143	503	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T11,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T11,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T11,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T35
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T35
0	1	Covered	T144,T145
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T35
0	1	Covered	T9,T11,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T35
1	-	Covered	T9,T11,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T11,T35
DetectSt	168	Covered	T9,T11,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T11,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T35
DebounceSt->IdleSt	163	Covered	T11,T77,T146
DetectSt->IdleSt	186	Covered	T144,T145
DetectSt->StableSt	191	Covered	T9,T11,T35
IdleSt->DebounceSt	148	Covered	T9,T11,T35
StableSt->IdleSt	206	Covered	T9,T11,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T11,T35
0	1	Covered	T9,T11,T35
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T35
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T11,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T146,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T11,T35
DetectSt	-	-	-	-	1	-	-	Covered	T144,T145
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T35
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	119	0	0
CntIncr_A	7138179	3373	0	0
CntNoWrap_A	7138179	6471932	0	0
DetectStDropOut_A	7138179	2	0	0
DetectedOut_A	7138179	4643	0	0
DetectedPulseOut_A	7138179	54	0	0
DisabledIdleSt_A	7138179	6453770	0	0
DisabledNoDetection_A	7138179	6456106	0	0
EnterDebounceSt_A	7138179	63	0	0
EnterDetectSt_A	7138179	56	0	0
EnterStableSt_A	7138179	54	0	0
PulseIsPulse_A	7138179	54	0	0
StayInStableSt	7138179	4565	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138179	2762	0	0
gen_low_level_sva.LowLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	119	0	0
T9	875	4	0	0
T10	4873	0	0	0
T11	848	3	0	0
T12	13581	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	4	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T77	0	1	0	0
T80	0	2	0	0
T128	0	4	0	0
T137	0	2	0	0
T148	0	2	0	0
T149	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3373	0	0
T9	875	102	0	0
T10	4873	0	0	0
T11	848	86	0	0
T12	13581	0	0	0
T33	0	13	0	0
T34	0	40	0	0
T35	0	102	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T77	0	17	0	0
T80	0	43	0	0
T128	0	130	0	0
T137	0	18	0	0
T148	0	99	0	0
T149	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471932	0	0
T1	21441	14653	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2	0	0
T144	618	1	0	0
T145	0	1	0	0
T150	22317	0	0	0
T151	2151	0	0	0
T152	3667	0	0	0
T153	408	0	0	0
T154	503	0	0	0
T155	1082	0	0	0
T156	556	0	0	0
T157	415	0	0	0
T158	1008	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	4643	0	0
T9	875	156	0	0
T10	4873	0	0	0
T11	848	122	0	0
T12	13581	0	0	0
T33	0	59	0	0
T34	0	94	0	0
T35	0	40	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T80	0	69	0	0
T128	0	262	0	0
T137	0	66	0	0
T148	0	190	0	0
T149	402	0	0	0
T159	0	36	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	54	0	0
T9	875	2	0	0
T10	4873	0	0	0
T11	848	1	0	0
T12	13581	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T80	0	1	0	0
T128	0	2	0	0
T137	0	1	0	0
T148	0	1	0	0
T149	402	0	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6453770	0	0
T1	21441	14653	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6456106	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	63	0	0
T9	875	2	0	0
T10	4873	0	0	0
T11	848	2	0	0
T12	13581	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T77	0	1	0	0
T80	0	1	0	0
T128	0	2	0	0
T137	0	1	0	0
T148	0	1	0	0
T149	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	56	0	0
T9	875	2	0	0
T10	4873	0	0	0
T11	848	1	0	0
T12	13581	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T80	0	1	0	0
T128	0	2	0	0
T137	0	1	0	0
T148	0	1	0	0
T149	402	0	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	54	0	0
T9	875	2	0	0
T10	4873	0	0	0
T11	848	1	0	0
T12	13581	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T80	0	1	0	0
T128	0	2	0	0
T137	0	1	0	0
T148	0	1	0	0
T149	402	0	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	54	0	0
T9	875	2	0	0
T10	4873	0	0	0
T11	848	1	0	0
T12	13581	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T80	0	1	0	0
T128	0	2	0	0
T137	0	1	0	0
T148	0	1	0	0
T149	402	0	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	4565	0	0
T9	875	154	0	0
T10	4873	0	0	0
T11	848	121	0	0
T12	13581	0	0	0
T33	0	57	0	0
T34	0	92	0	0
T35	0	37	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T80	0	67	0	0
T128	0	260	0	0
T137	0	64	0	0
T148	0	188	0	0
T149	402	0	0	0
T159	0	34	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2762	0	0
T1	21441	24	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	1	0	0
T13	496	6	0	0
T14	527	5	0	0
T15	492	5	0	0
T16	7883	0	0	0
T17	504	6	0	0
T18	503	5	0	0
T40	0	17	0	0
T107	0	2	0	0
T108	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	30	0	0
T9	875	2	0	0
T10	4873	0	0	0
T11	848	1	0	0
T12	13581	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T128	0	2	0	0
T131	0	2	0	0
T132	0	1	0	0
T134	0	1	0	0
T149	402	0	0	0
T160	0	1	0	0
T161	0	2	0	0