Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T8,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T8,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T36
0	1	Covered	T8,T36,T35
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T36
1	-	Covered	T8,T36,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T36
DetectSt	168	Covered	T1,T8,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T8,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T36
DebounceSt->IdleSt	163	Covered	T77,T78,T135
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T8,T36
IdleSt->DebounceSt	148	Covered	T1,T8,T36
StableSt->IdleSt	206	Covered	T1,T8,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T36
0	1	Covered	T1,T8,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T135
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T36,T35
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	130	0	0
CntIncr_A	7138179	3894	0	0
CntNoWrap_A	7138179	6471921	0	0
DetectStDropOut_A	7138179	0	0	0
DetectedOut_A	7138179	5932	0	0
DetectedPulseOut_A	7138179	64	0	0
DisabledIdleSt_A	7138179	6453404	0	0
DisabledNoDetection_A	7138179	6455743	0	0
EnterDebounceSt_A	7138179	67	0	0
EnterDetectSt_A	7138179	64	0	0
EnterStableSt_A	7138179	63	0	0
PulseIsPulse_A	7138179	63	0	0
StayInStableSt	7138179	5840	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	130	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	2	0	0
T32	0	2	0	0
T34	0	4	0	0
T35	0	4	0	0
T36	0	4	0	0
T37	0	2	0	0
T77	0	1	0	0
T128	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3894	0	0
T1	21441	72	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	67	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	39	0	0
T32	0	64	0	0
T34	0	51	0	0
T35	0	102	0	0
T36	0	192	0	0
T37	0	79	0	0
T77	0	17	0	0
T128	0	110	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471921	0	0
T1	21441	14651	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5932	0	0
T1	21441	50	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	163	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	19	0	0
T32	0	45	0	0
T34	0	376	0	0
T35	0	133	0	0
T36	0	83	0	0
T37	0	46	0	0
T128	0	382	0	0
T168	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	64	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T128	0	2	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6453404	0	0
T1	21441	14455	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6455743	0	0
T1	21441	14473	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	67	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T77	0	1	0	0
T128	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	64	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T128	0	2	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	63	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T128	0	2	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	63	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T128	0	2	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5840	0	0
T1	21441	48	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T8	0	162	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	17	0	0
T32	0	43	0	0
T34	0	372	0	0
T35	0	130	0	0
T36	0	81	0	0
T37	0	44	0	0
T128	0	380	0	0
T168	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	35	0	0
T8	931	1	0	0
T24	20701	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T107	423	0	0	0
T108	448	0	0	0
T128	0	2	0	0
T131	0	2	0	0
T133	0	1	0	0
T159	0	1	0	0
T164	0	2	0	0
T166	0	1	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T131,T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T11
1	-	Covered	T1,T9,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T11
DetectSt	168	Covered	T1,T9,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T11
DebounceSt->IdleSt	163	Covered	T77,T190,T191
DetectSt->IdleSt	186	Covered	T131,T189
DetectSt->StableSt	191	Covered	T1,T9,T11
IdleSt->DebounceSt	148	Covered	T1,T9,T11
StableSt->IdleSt	206	Covered	T1,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T190,T191
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T131,T189
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	98	0	0
CntIncr_A	7138179	2564	0	0
CntNoWrap_A	7138179	6471953	0	0
DetectStDropOut_A	7138179	2	0	0
DetectedOut_A	7138179	2869	0	0
DetectedPulseOut_A	7138179	45	0	0
DisabledIdleSt_A	7138179	6452310	0	0
DisabledNoDetection_A	7138179	6454643	0	0
EnterDebounceSt_A	7138179	51	0	0
EnterDetectSt_A	7138179	47	0	0
EnterStableSt_A	7138179	45	0	0
PulseIsPulse_A	7138179	45	0	0
StayInStableSt	7138179	2801	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138179	6388	0	0
gen_low_level_sva.LowLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	98	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	2	0	0
T11	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	2	0	0
T36	0	4	0	0
T77	0	1	0	0
T80	0	2	0	0
T128	0	4	0	0
T129	0	2	0	0
T148	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2564	0	0
T1	21441	57	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	51	0	0
T11	0	86	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	51	0	0
T36	0	192	0	0
T77	0	17	0	0
T80	0	17	0	0
T128	0	110	0	0
T129	0	18	0	0
T148	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471953	0	0
T1	21441	14651	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2	0	0
T83	740	0	0	0
T131	625	1	0	0
T169	898	0	0	0
T189	0	1	0	0
T192	33198	0	0	0
T193	6234	0	0	0
T194	46566	0	0	0
T195	422	0	0	0
T196	504	0	0	0
T197	18382	0	0	0
T198	18002	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2869	0	0
T1	21441	29	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	41	0	0
T11	0	89	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	31	0	0
T36	0	129	0	0
T80	0	40	0	0
T128	0	240	0	0
T129	0	42	0	0
T148	0	45	0	0
T159	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	45	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T80	0	1	0	0
T128	0	2	0	0
T129	0	1	0	0
T148	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6452310	0	0
T1	21441	14071	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6454643	0	0
T1	21441	14089	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	51	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T77	0	1	0	0
T80	0	1	0	0
T128	0	2	0	0
T129	0	1	0	0
T148	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	47	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T80	0	1	0	0
T128	0	2	0	0
T129	0	1	0	0
T148	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	45	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T80	0	1	0	0
T128	0	2	0	0
T129	0	1	0	0
T148	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	45	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	1	0	0
T36	0	2	0	0
T80	0	1	0	0
T128	0	2	0	0
T129	0	1	0	0
T148	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2801	0	0
T1	21441	28	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	40	0	0
T11	0	86	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	30	0	0
T36	0	126	0	0
T80	0	39	0	0
T128	0	236	0	0
T129	0	40	0	0
T148	0	43	0	0
T159	0	47	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6388	0	0
T1	21441	39	0	0
T2	13902	29	0	0
T3	16928	12	0	0
T6	15299	29	0	0
T7	0	27	0	0
T13	496	7	0	0
T14	527	4	0	0
T15	492	7	0	0
T16	7883	0	0	0
T17	504	5	0	0
T18	503	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	22	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T80	0	1	0	0
T110	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0
T164	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T9,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T9,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T36,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T36
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T36,T25
0	1	Covered	T34,T169,T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T36,T25
0	1	Covered	T9,T36,T32
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T36,T25
1	-	Covered	T9,T36,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T36
DetectSt	168	Covered	T9,T36,T25
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T36,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T36,T25
DebounceSt->IdleSt	163	Covered	T1,T9,T34
DetectSt->IdleSt	186	Covered	T34,T169,T180
DetectSt->StableSt	191	Covered	T9,T36,T25
IdleSt->DebounceSt	148	Covered	T1,T9,T36
StableSt->IdleSt	206	Covered	T9,T36,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T36
0	1	Covered	T1,T9,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T36,T25
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T36
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T36,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T9,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T36
DetectSt	-	-	-	-	1	-	-	Covered	T34,T169,T180
DetectSt	-	-	-	-	0	1	-	Covered	T9,T36,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T36,T32
StableSt	-	-	-	-	-	-	0	Covered	T9,T36,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	133	0	0
CntIncr_A	7138179	3847	0	0
CntNoWrap_A	7138179	6471918	0	0
DetectStDropOut_A	7138179	5	0	0
DetectedOut_A	7138179	5127	0	0
DetectedPulseOut_A	7138179	58	0	0
DisabledIdleSt_A	7138179	6452983	0	0
DisabledNoDetection_A	7138179	6455316	0	0
EnterDebounceSt_A	7138179	70	0	0
EnterDetectSt_A	7138179	63	0	0
EnterStableSt_A	7138179	58	0	0
PulseIsPulse_A	7138179	58	0	0
StayInStableSt	7138179	5044	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	133	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	3	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	2	0	0
T32	0	2	0	0
T34	0	5	0	0
T35	0	2	0	0
T36	0	6	0	0
T77	0	1	0	0
T128	0	2	0	0
T137	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3847	0	0
T1	21441	72	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	102	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	39	0	0
T32	0	64	0	0
T34	0	71	0	0
T35	0	51	0	0
T36	0	288	0	0
T77	0	18	0	0
T128	0	45	0	0
T137	0	18	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471918	0	0
T1	21441	14652	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5	0	0
T34	291233	1	0	0
T77	6257	0	0	0
T128	35239	0	0	0
T137	1850	0	0	0
T138	15616	0	0	0
T139	496	0	0	0
T140	404	0	0	0
T141	6158	0	0	0
T142	444	0	0	0
T143	503	0	0	0
T169	0	1	0	0
T180	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5127	0	0
T9	875	133	0	0
T10	4873	0	0	0
T11	848	0	0	0
T12	13581	0	0	0
T25	0	60	0	0
T32	0	25	0	0
T34	0	42	0	0
T35	0	124	0	0
T36	1152	175	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T110	0	86	0	0
T128	0	96	0	0
T129	0	71	0	0
T137	0	6	0	0
T149	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	58	0	0
T9	875	1	0	0
T10	4873	0	0	0
T11	848	0	0	0
T12	13581	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	1152	3	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T110	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0
T137	0	1	0	0
T149	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6452983	0	0
T1	21441	14455	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6455316	0	0
T1	21441	14473	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	70	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	3	0	0
T35	0	1	0	0
T36	0	3	0	0
T77	0	1	0	0
T128	0	1	0	0
T137	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	63	0	0
T9	875	1	0	0
T10	4873	0	0	0
T11	848	0	0	0
T12	13581	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	1152	3	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T110	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0
T137	0	1	0	0
T149	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	58	0	0
T9	875	1	0	0
T10	4873	0	0	0
T11	848	0	0	0
T12	13581	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	1152	3	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T110	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0
T137	0	1	0	0
T149	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	58	0	0
T9	875	1	0	0
T10	4873	0	0	0
T11	848	0	0	0
T12	13581	0	0	0
T25	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	1152	3	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T110	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0
T137	0	1	0	0
T149	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	5044	0	0
T9	875	132	0	0
T10	4873	0	0	0
T11	848	0	0	0
T12	13581	0	0	0
T25	0	58	0	0
T32	0	24	0	0
T34	0	41	0	0
T35	0	122	0	0
T36	1152	171	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T110	0	84	0	0
T128	0	95	0	0
T129	0	70	0	0
T137	0	5	0	0
T149	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	33	0	0
T9	875	1	0	0
T10	4873	0	0	0
T11	848	0	0	0
T12	13581	0	0	0
T32	0	1	0	0
T34	0	1	0	0
T36	1152	2	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T110	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0
T137	0	1	0	0
T149	402	0	0	0
T160	0	1	0	0
T164	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T32,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T32,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T32,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T32,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T32,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T32,T33
0	1	Covered	T1,T33,T128
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T32,T33
1	-	Covered	T1,T33,T128

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T32,T33
DetectSt	168	Covered	T1,T32,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T32,T33
DebounceSt->IdleSt	163	Covered	T77,T191,T201
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T32,T33
IdleSt->DebounceSt	148	Covered	T1,T32,T33
StableSt->IdleSt	206	Covered	T1,T33,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T32,T33
0	1	Covered	T1,T32,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T32,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T32,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T32,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T191,T201
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T32,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T32,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T33,T128
StableSt	-	-	-	-	-	-	0	Covered	T1,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	82	0	0
CntIncr_A	7138179	2330	0	0
CntNoWrap_A	7138179	6471969	0	0
DetectStDropOut_A	7138179	0	0	0
DetectedOut_A	7138179	2486	0	0
DetectedPulseOut_A	7138179	39	0	0
DisabledIdleSt_A	7138179	6453679	0	0
DisabledNoDetection_A	7138179	6456014	0	0
EnterDebounceSt_A	7138179	43	0	0
EnterDetectSt_A	7138179	39	0	0
EnterStableSt_A	7138179	39	0	0
PulseIsPulse_A	7138179	39	0	0
StayInStableSt	7138179	2423	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138179	6368	0	0
gen_low_level_sva.LowLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	82	0	0
T1	21441	4	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T77	0	1	0	0
T128	0	4	0	0
T134	0	4	0	0
T160	0	6	0	0
T168	0	2	0	0
T171	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2330	0	0
T1	21441	129	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	64	0	0
T33	0	13	0	0
T34	0	31	0	0
T77	0	17	0	0
T128	0	110	0	0
T134	0	182	0	0
T160	0	62	0	0
T168	0	88	0	0
T171	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471969	0	0
T1	21441	14649	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2486	0	0
T1	21441	66	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	45	0	0
T33	0	5	0	0
T34	0	84	0	0
T128	0	238	0	0
T134	0	251	0	0
T160	0	119	0	0
T167	0	83	0	0
T168	0	39	0	0
T171	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	39	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T128	0	2	0	0
T134	0	2	0	0
T160	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6453679	0	0
T1	21441	13873	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6456014	0	0
T1	21441	13890	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	43	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T77	0	1	0	0
T128	0	2	0	0
T134	0	2	0	0
T160	0	3	0	0
T168	0	1	0	0
T171	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	39	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T128	0	2	0	0
T134	0	2	0	0
T160	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	39	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T128	0	2	0	0
T134	0	2	0	0
T160	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	39	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T128	0	2	0	0
T134	0	2	0	0
T160	0	3	0	0
T167	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2423	0	0
T1	21441	63	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	43	0	0
T33	0	4	0	0
T34	0	82	0	0
T128	0	235	0	0
T134	0	248	0	0
T160	0	114	0	0
T167	0	80	0	0
T168	0	37	0	0
T171	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6368	0	0
T1	21441	44	0	0
T2	13902	28	0	0
T3	16928	10	0	0
T6	15299	25	0	0
T7	0	23	0	0
T13	496	10	0	0
T14	527	5	0	0
T15	492	8	0	0
T16	7883	0	0	0
T17	504	5	0	0
T18	503	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	15	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	1	0	0
T128	0	1	0	0
T134	0	1	0	0
T136	0	1	0	0
T160	0	1	0	0
T163	0	1	0	0
T167	0	1	0	0
T181	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T32,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T32,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T32,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T35,T32
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T32,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T32,T34
0	1	Covered	T202,T200
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T32,T34
0	1	Covered	T1,T34,T128
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T32,T34
1	-	Covered	T1,T34,T128

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T32,T34
DetectSt	168	Covered	T1,T32,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T32,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T32,T34
DebounceSt->IdleSt	163	Covered	T1,T77,T110
DetectSt->IdleSt	186	Covered	T202,T200
DetectSt->StableSt	191	Covered	T1,T32,T34
IdleSt->DebounceSt	148	Covered	T1,T32,T34
StableSt->IdleSt	206	Covered	T1,T34,T128

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T32,T34
0	1	Covered	T1,T32,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T32,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T32,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T32,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T110,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T32,T34
DetectSt	-	-	-	-	1	-	-	Covered	T202,T200
DetectSt	-	-	-	-	0	1	-	Covered	T1,T32,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T34,T128
StableSt	-	-	-	-	-	-	0	Covered	T1,T32,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	113	0	0
CntIncr_A	7138179	3270	0	0
CntNoWrap_A	7138179	6471938	0	0
DetectStDropOut_A	7138179	2	0	0
DetectedOut_A	7138179	4707	0	0
DetectedPulseOut_A	7138179	51	0	0
DisabledIdleSt_A	7138179	6454997	0	0
DisabledNoDetection_A	7138179	6457336	0	0
EnterDebounceSt_A	7138179	61	0	0
EnterDetectSt_A	7138179	53	0	0
EnterStableSt_A	7138179	51	0	0
PulseIsPulse_A	7138179	51	0	0
StayInStableSt	7138179	4637	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	113	0	0
T1	21441	5	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	2	0	0
T34	0	4	0	0
T77	0	1	0	0
T80	0	8	0	0
T110	0	4	0	0
T128	0	2	0	0
T129	0	2	0	0
T155	0	2	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3270	0	0
T1	21441	186	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	64	0	0
T34	0	40	0	0
T77	0	16	0	0
T80	0	220	0	0
T110	0	66	0	0
T128	0	45	0	0
T129	0	18	0	0
T155	0	92	0	0
T159	0	90	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471938	0	0
T1	21441	14648	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2	0	0
T200	0	1	0	0
T202	886	1	0	0
T203	422	0	0	0
T204	16675	0	0	0
T205	458	0	0	0
T206	424	0	0	0
T207	738	0	0	0
T208	424	0	0	0
T209	720	0	0	0
T210	627	0	0	0
T211	17829	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	4707	0	0
T1	21441	70	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	136	0	0
T34	0	104	0	0
T80	0	257	0	0
T110	0	5	0	0
T128	0	11	0	0
T129	0	79	0	0
T132	0	143	0	0
T155	0	71	0	0
T159	0	175	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	51	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T80	0	4	0	0
T110	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T132	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6454997	0	0
T1	21441	13873	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6457336	0	0
T1	21441	13890	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	61	0	0
T1	21441	3	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T77	0	1	0	0
T80	0	4	0	0
T110	0	3	0	0
T128	0	1	0	0
T129	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	53	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T80	0	4	0	0
T110	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T132	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	51	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T80	0	4	0	0
T110	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T132	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	51	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	1	0	0
T34	0	2	0	0
T80	0	4	0	0
T110	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T132	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	4637	0	0
T1	21441	68	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T32	0	134	0	0
T34	0	102	0	0
T80	0	252	0	0
T110	0	4	0	0
T128	0	10	0	0
T129	0	78	0	0
T132	0	141	0	0
T155	0	70	0	0
T159	0	173	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	32	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T34	0	2	0	0
T80	0	3	0	0
T110	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T134	0	1	0	0
T155	0	1	0	0
T165	0	1	0	0
T170	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T2
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T11
1	0	Covered	T4,T1,T2
1	1	Covered	T1,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T34
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T11
0	1	Covered	T9,T11,T33
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T11
1	-	Covered	T9,T11,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T11
DetectSt	168	Covered	T1,T9,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T11
DebounceSt->IdleSt	163	Covered	T9,T77,T110
DetectSt->IdleSt	186	Covered	T34
DetectSt->StableSt	191	Covered	T1,T9,T11
IdleSt->DebounceSt	148	Covered	T1,T9,T11
StableSt->IdleSt	206	Covered	T1,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T11
0	1	Covered	T1,T9,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	1	-	-	Covered	T34
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T33
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	86	0	0
CntIncr_A	7138179	2401	0	0
CntNoWrap_A	7138179	6471965	0	0
DetectStDropOut_A	7138179	1	0	0
DetectedOut_A	7138179	3662	0	0
DetectedPulseOut_A	7138179	40	0	0
DisabledIdleSt_A	7138179	6454217	0	0
DisabledNoDetection_A	7138179	6456556	0	0
EnterDebounceSt_A	7138179	46	0	0
EnterDetectSt_A	7138179	41	0	0
EnterStableSt_A	7138179	40	0	0
PulseIsPulse_A	7138179	40	0	0
StayInStableSt	7138179	3600	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7138179	7090	0	0
gen_low_level_sva.LowLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	86	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	3	0	0
T11	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T77	0	1	0	0
T80	0	6	0	0
T110	0	4	0	0
T128	0	2	0	0
T148	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2401	0	0
T1	21441	72	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	102	0	0
T11	0	43	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	13	0	0
T34	0	40	0	0
T77	0	16	0	0
T80	0	127	0	0
T110	0	50	0	0
T128	0	45	0	0
T148	0	99	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471965	0	0
T1	21441	14651	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1	0	0
T34	291233	1	0	0
T77	6257	0	0	0
T128	35239	0	0	0
T137	1850	0	0	0
T138	15616	0	0	0
T139	496	0	0	0
T140	404	0	0	0
T141	6158	0	0	0
T142	444	0	0	0
T143	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3662	0	0
T1	21441	49	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	41	0	0
T11	0	207	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	6	0	0
T34	0	39	0	0
T80	0	104	0	0
T110	0	87	0	0
T128	0	184	0	0
T131	0	52	0	0
T148	0	330	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	40	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T80	0	3	0	0
T110	0	2	0	0
T128	0	1	0	0
T131	0	1	0	0
T148	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6454217	0	0
T1	21441	14455	0	0
T2	13902	13473	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6456556	0	0
T1	21441	14473	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	46	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	2	0	0
T11	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T77	0	1	0	0
T80	0	3	0	0
T110	0	3	0	0
T128	0	1	0	0
T148	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	41	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T80	0	3	0	0
T110	0	2	0	0
T128	0	1	0	0
T131	0	1	0	0
T148	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	40	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T80	0	3	0	0
T110	0	2	0	0
T128	0	1	0	0
T131	0	1	0	0
T148	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	40	0	0
T1	21441	1	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T80	0	3	0	0
T110	0	2	0	0
T128	0	1	0	0
T131	0	1	0	0
T148	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3600	0	0
T1	21441	47	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T9	0	40	0	0
T11	0	206	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T33	0	5	0	0
T34	0	37	0	0
T80	0	100	0	0
T110	0	85	0	0
T128	0	182	0	0
T131	0	51	0	0
T148	0	328	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	7090	0	0
T1	21441	46	0	0
T2	13902	31	0	0
T3	16928	12	0	0
T4	202500	4	0	0
T5	797	0	0	0
T13	496	8	0	0
T14	527	3	0	0
T15	492	4	0	0
T16	7883	4	0	0
T17	504	6	0	0
T18	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	18	0	0
T9	875	1	0	0
T10	4873	0	0	0
T11	848	1	0	0
T12	13581	0	0	0
T33	0	1	0	0
T36	1152	0	0	0
T55	525	0	0	0
T56	525	0	0	0
T57	794	0	0	0
T66	523	0	0	0
T80	0	2	0	0
T110	0	2	0	0
T131	0	1	0	0
T134	0	1	0	0
T149	402	0	0	0
T160	0	1	0	0
T161	0	1	0	0
T191	0	1	0	0