Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T12
1	1	Covered	T2,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T39,T42,T70
1	0	Covered	T77,T212,T89

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
1	0	Covered	T38,T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T7
1	-	Covered	T2,T6,T7

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T7
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T6,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T77,T213,T214
DetectSt->IdleSt	186	Covered	T39,T42,T70
DetectSt->StableSt	191	Covered	T2,T6,T7
IdleSt->DebounceSt	148	Covered	T2,T6,T7
StableSt->IdleSt	206	Covered	T2,T6,T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T2,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T213,T214
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T39,T42,T70
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T7
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	2911	0	0
CntIncr_A	7138179	98099	0	0
CntNoWrap_A	7138179	6469140	0	0
DetectStDropOut_A	7138179	410	0	0
DetectedOut_A	7138179	70242	0	0
DetectedPulseOut_A	7138179	873	0	0
DisabledIdleSt_A	7138179	6031468	0	0
DisabledNoDetection_A	7138179	6033669	0	0
EnterDebounceSt_A	7138179	1466	0	0
EnterDetectSt_A	7138179	1445	0	0
EnterStableSt_A	7138179	873	0	0
PulseIsPulse_A	7138179	873	0	0
StayInStableSt	7138179	69270	0	0
gen_high_event_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	759	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2911	0	0
T2	13902	18	0	0
T3	16928	0	0	0
T6	15299	18	0	0
T7	0	20	0	0
T12	0	10	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	24	0	0
T38	0	28	0	0
T39	0	56	0	0
T42	0	18	0	0
T50	782	0	0	0
T68	0	2	0	0
T69	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	98099	0	0
T2	13902	324	0	0
T3	16928	0	0	0
T6	15299	792	0	0
T7	0	510	0	0
T12	0	210	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	816	0	0
T38	0	966	0	0
T39	0	1933	0	0
T42	0	574	0	0
T50	782	0	0	0
T68	0	21	0	0
T69	0	1325	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6469140	0	0
T1	21441	14653	0	0
T2	13902	13455	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	410	0	0
T9	875	0	0	0
T24	20701	0	0	0
T39	6073	28	0	0
T40	3761	0	0	0
T42	0	9	0	0
T51	425	0	0	0
T52	411	0	0	0
T53	4415	0	0	0
T54	501	0	0	0
T70	0	30	0	0
T77	0	1	0	0
T88	0	5	0	0
T89	0	4	0	0
T91	0	4	0	0
T92	0	9	0	0
T94	0	15	0	0
T95	0	28	0	0
T107	423	0	0	0
T108	448	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	70242	0	0
T2	13902	771	0	0
T3	16928	0	0	0
T6	15299	358	0	0
T7	0	1509	0	0
T12	0	121	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1784	0	0
T38	0	170	0	0
T50	782	0	0	0
T68	0	27	0	0
T69	0	877	0	0
T215	0	149	0	0
T216	0	953	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	873	0	0
T2	13902	9	0	0
T3	16928	0	0	0
T6	15299	9	0	0
T7	0	10	0	0
T12	0	5	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	12	0	0
T38	0	14	0	0
T50	782	0	0	0
T68	0	1	0	0
T69	0	25	0	0
T215	0	5	0	0
T216	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6031468	0	0
T1	21441	14653	0	0
T2	13902	10071	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6033669	0	0
T1	21441	14672	0	0
T2	13902	10071	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1466	0	0
T2	13902	9	0	0
T3	16928	0	0	0
T6	15299	9	0	0
T7	0	10	0	0
T12	0	5	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	12	0	0
T38	0	14	0	0
T39	0	28	0	0
T42	0	9	0	0
T50	782	0	0	0
T68	0	1	0	0
T69	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1445	0	0
T2	13902	9	0	0
T3	16928	0	0	0
T6	15299	9	0	0
T7	0	10	0	0
T12	0	5	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	12	0	0
T38	0	14	0	0
T39	0	28	0	0
T42	0	9	0	0
T50	782	0	0	0
T68	0	1	0	0
T69	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	873	0	0
T2	13902	9	0	0
T3	16928	0	0	0
T6	15299	9	0	0
T7	0	10	0	0
T12	0	5	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	12	0	0
T38	0	14	0	0
T50	782	0	0	0
T68	0	1	0	0
T69	0	25	0	0
T215	0	5	0	0
T216	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	873	0	0
T2	13902	9	0	0
T3	16928	0	0	0
T6	15299	9	0	0
T7	0	10	0	0
T12	0	5	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	12	0	0
T38	0	14	0	0
T50	782	0	0	0
T68	0	1	0	0
T69	0	25	0	0
T215	0	5	0	0
T216	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	69270	0	0
T2	13902	758	0	0
T3	16928	0	0	0
T6	15299	348	0	0
T7	0	1499	0	0
T12	0	116	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1772	0	0
T38	0	156	0	0
T50	782	0	0	0
T68	0	25	0	0
T69	0	851	0	0
T215	0	144	0	0
T216	0	943	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	759	0	0
T2	13902	5	0	0
T3	16928	0	0	0
T6	15299	8	0	0
T7	0	10	0	0
T12	0	5	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	12	0	0
T50	782	0	0	0
T69	0	24	0	0
T141	0	27	0	0
T215	0	5	0	0
T216	0	4	0	0
T217	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T76,T87,T90
1	0	Covered	T77,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T3,T40,T25
DetectSt->IdleSt	186	Covered	T76,T87,T77
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T40,T25
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T76,T87,T77
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	970	0	0
CntIncr_A	7138179	48764	0	0
CntNoWrap_A	7138179	6471081	0	0
DetectStDropOut_A	7138179	27	0	0
DetectedOut_A	7138179	16388	0	0
DetectedPulseOut_A	7138179	415	0	0
DisabledIdleSt_A	7138179	6052595	0	0
DisabledNoDetection_A	7138179	6054237	0	0
EnterDebounceSt_A	7138179	526	0	0
EnterDetectSt_A	7138179	446	0	0
EnterStableSt_A	7138179	415	0	0
PulseIsPulse_A	7138179	415	0	0
StayInStableSt	7138179	15941	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	379	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	970	0	0
T1	21441	2	0	0
T2	13902	8	0	0
T3	16928	3	0	0
T6	15299	2	0	0
T7	0	8	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	2	0	0
T28	0	8	0	0
T40	0	1	0	0
T64	0	14	0	0
T86	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	48764	0	0
T1	21441	25	0	0
T2	13902	164	0	0
T3	16928	191	0	0
T6	15299	71	0	0
T7	0	236	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	45	0	0
T28	0	396	0	0
T40	0	20	0	0
T64	0	1001	0	0
T86	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471081	0	0
T1	21441	14651	0	0
T2	13902	13465	0	0
T3	16928	16484	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	27	0	0
T65	490	0	0	0
T69	13821	0	0	0
T72	1107	0	0	0
T76	12479	1	0	0
T81	0	3	0	0
T87	0	6	0	0
T90	0	3	0	0
T93	0	1	0	0
T96	0	4	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	503	0	0	0
T102	1384	0	0	0
T103	522	0	0	0
T104	502	0	0	0
T105	435	0	0	0
T106	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	16388	0	0
T1	21441	3	0	0
T2	13902	292	0	0
T3	16928	56	0	0
T6	15299	63	0	0
T7	0	309	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	3	0	0
T28	0	178	0	0
T30	0	16	0	0
T64	0	229	0	0
T86	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	415	0	0
T1	21441	1	0	0
T2	13902	4	0	0
T3	16928	1	0	0
T6	15299	1	0	0
T7	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T28	0	4	0	0
T30	0	1	0	0
T64	0	7	0	0
T86	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6052595	0	0
T1	21441	9265	0	0
T2	13902	12706	0	0
T3	16928	12088	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6054237	0	0
T1	21441	9280	0	0
T2	13902	12707	0	0
T3	16928	12088	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	526	0	0
T1	21441	1	0	0
T2	13902	4	0	0
T3	16928	2	0	0
T6	15299	1	0	0
T7	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	2	0	0
T28	0	4	0	0
T40	0	1	0	0
T64	0	7	0	0
T86	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	446	0	0
T1	21441	1	0	0
T2	13902	4	0	0
T3	16928	1	0	0
T6	15299	1	0	0
T7	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T28	0	4	0	0
T30	0	1	0	0
T64	0	7	0	0
T86	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	415	0	0
T1	21441	1	0	0
T2	13902	4	0	0
T3	16928	1	0	0
T6	15299	1	0	0
T7	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T28	0	4	0	0
T30	0	1	0	0
T64	0	7	0	0
T86	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	415	0	0
T1	21441	1	0	0
T2	13902	4	0	0
T3	16928	1	0	0
T6	15299	1	0	0
T7	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T28	0	4	0	0
T30	0	1	0	0
T64	0	7	0	0
T86	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	15941	0	0
T1	21441	2	0	0
T2	13902	288	0	0
T3	16928	55	0	0
T6	15299	62	0	0
T7	0	305	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	2	0	0
T28	0	174	0	0
T30	0	15	0	0
T64	0	222	0	0
T86	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	379	0	0
T1	21441	1	0	0
T2	13902	4	0	0
T3	16928	1	0	0
T6	15299	1	0	0
T7	0	4	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T25	0	1	0	0
T28	0	4	0	0
T30	0	1	0	0
T64	0	7	0	0
T86	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T7,T39
1	0	Covered	T2,T7,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T28
0	1	Covered	T6,T12,T28
1	0	Covered	T77,T79,T218

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T12,T28
1	-	Covered	T6,T12,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T7
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T12,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T77,T213,T214
DetectSt->IdleSt	186	Covered	T2,T7,T39
DetectSt->StableSt	191	Covered	T6,T12,T28
IdleSt->DebounceSt	148	Covered	T2,T6,T7
StableSt->IdleSt	206	Covered	T6,T12,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T2,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T213,T214
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T2,T7,T39
DetectSt	-	-	-	-	0	1	-	Covered	T6,T12,T28
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T6,T12,T28
StableSt	-	-	-	-	-	-	0	Covered	T6,T12,T28
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	3120	0	0
CntIncr_A	7138179	95457	0	0
CntNoWrap_A	7138179	6468931	0	0
DetectStDropOut_A	7138179	433	0	0
DetectedOut_A	7138179	73376	0	0
DetectedPulseOut_A	7138179	975	0	0
DisabledIdleSt_A	7138179	6029441	0	0
DisabledNoDetection_A	7138179	6031633	0	0
EnterDebounceSt_A	7138179	1568	0	0
EnterDetectSt_A	7138179	1552	0	0
EnterStableSt_A	7138179	975	0	0
PulseIsPulse_A	7138179	975	0	0
StayInStableSt	7138179	72293	0	0
gen_high_event_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	862	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	3120	0	0
T2	13902	54	0	0
T3	16928	0	0	0
T6	15299	16	0	0
T7	0	54	0	0
T12	0	48	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	42	0	0
T38	0	6	0	0
T39	0	20	0	0
T42	0	24	0	0
T50	782	0	0	0
T69	0	44	0	0
T70	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	95457	0	0
T2	13902	1377	0	0
T3	16928	0	0	0
T6	15299	504	0	0
T7	0	1525	0	0
T12	0	864	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1491	0	0
T38	0	234	0	0
T39	0	684	0	0
T42	0	763	0	0
T50	782	0	0	0
T69	0	1384	0	0
T70	0	351	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6468931	0	0
T1	21441	14653	0	0
T2	13902	13419	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	433	0	0
T2	13902	24	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T7	0	17	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T39	0	10	0	0
T42	0	12	0	0
T50	782	0	0	0
T69	0	6	0	0
T70	0	6	0	0
T77	0	1	0	0
T79	0	7	0	0
T88	0	22	0	0
T91	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	73376	0	0
T6	15299	674	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	869	0	0
T24	20701	0	0	0
T28	0	1853	0	0
T38	0	13	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	304	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	1058	0	0
T215	0	485	0	0
T216	0	1606	0	0
T217	0	1997	0	0
T219	0	1420	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	975	0	0
T6	15299	8	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	24	0	0
T24	20701	0	0	0
T28	0	21	0	0
T38	0	3	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	31	0	0
T215	0	6	0	0
T216	0	14	0	0
T217	0	10	0	0
T219	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6029441	0	0
T1	21441	14653	0	0
T2	13902	10704	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6031633	0	0
T1	21441	14672	0	0
T2	13902	10708	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1568	0	0
T2	13902	27	0	0
T3	16928	0	0	0
T6	15299	8	0	0
T7	0	27	0	0
T12	0	24	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	21	0	0
T38	0	3	0	0
T39	0	10	0	0
T42	0	12	0	0
T50	782	0	0	0
T69	0	22	0	0
T70	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1552	0	0
T2	13902	27	0	0
T3	16928	0	0	0
T6	15299	8	0	0
T7	0	27	0	0
T12	0	24	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	21	0	0
T38	0	3	0	0
T39	0	10	0	0
T42	0	12	0	0
T50	782	0	0	0
T69	0	22	0	0
T70	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	975	0	0
T6	15299	8	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	24	0	0
T24	20701	0	0	0
T28	0	21	0	0
T38	0	3	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	31	0	0
T215	0	6	0	0
T216	0	14	0	0
T217	0	10	0	0
T219	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	975	0	0
T6	15299	8	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	24	0	0
T24	20701	0	0	0
T28	0	21	0	0
T38	0	3	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	31	0	0
T215	0	6	0	0
T216	0	14	0	0
T217	0	10	0	0
T219	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	72293	0	0
T6	15299	664	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	844	0	0
T24	20701	0	0	0
T28	0	1831	0	0
T38	0	10	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	299	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	1027	0	0
T215	0	477	0	0
T216	0	1584	0	0
T217	0	1984	0	0
T219	0	1396	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	862	0	0
T6	15299	6	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	23	0	0
T24	20701	0	0	0
T28	0	20	0	0
T38	0	3	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	4	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	31	0	0
T215	0	4	0	0
T216	0	6	0	0
T217	0	7	0	0
T219	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T30,T110,T220
1	0	Covered	T77,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T3,T12
1	0	Covered	T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T6
1	-	Covered	T1,T3,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T3,T41,T64
DetectSt->IdleSt	186	Covered	T30,T77,T110
DetectSt->StableSt	191	Covered	T1,T3,T6
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T41,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T30,T77,T110
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	713	0	0
CntIncr_A	7138179	40417	0	0
CntNoWrap_A	7138179	6471338	0	0
DetectStDropOut_A	7138179	38	0	0
DetectedOut_A	7138179	11828	0	0
DetectedPulseOut_A	7138179	295	0	0
DisabledIdleSt_A	7138179	6069216	0	0
DisabledNoDetection_A	7138179	6070949	0	0
EnterDebounceSt_A	7138179	376	0	0
EnterDetectSt_A	7138179	337	0	0
EnterStableSt_A	7138179	295	0	0
PulseIsPulse_A	7138179	295	0	0
StayInStableSt	7138179	11494	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	254	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	713	0	0
T1	21441	4	0	0
T2	13902	0	0	0
T3	16928	8	0	0
T6	15299	4	0	0
T12	0	2	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	2	0	0
T29	0	4	0	0
T30	0	2	0	0
T41	0	11	0	0
T64	0	25	0	0
T76	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	40417	0	0
T1	21441	302	0	0
T2	13902	0	0	0
T3	16928	639	0	0
T6	15299	134	0	0
T12	0	51	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	65	0	0
T29	0	164	0	0
T30	0	122	0	0
T41	0	646	0	0
T64	0	2107	0	0
T76	0	435	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471338	0	0
T1	21441	14649	0	0
T2	13902	13473	0	0
T3	16928	16479	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	38	0	0
T30	6293	1	0	0
T62	1634	0	0	0
T71	2264	0	0	0
T81	0	1	0	0
T98	0	2	0	0
T110	0	2	0	0
T183	422	0	0	0
T184	502	0	0	0
T185	6795	0	0	0
T186	504	0	0	0
T187	536	0	0	0
T220	0	3	0	0
T221	0	5	0	0
T222	0	4	0	0
T223	0	3	0	0
T224	0	1	0	0
T225	0	3	0	0
T226	425	0	0	0
T227	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	11828	0	0
T1	21441	20	0	0
T2	13902	0	0	0
T3	16928	15	0	0
T6	15299	130	0	0
T12	0	66	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	78	0	0
T29	0	129	0	0
T41	0	56	0	0
T64	0	85	0	0
T76	0	12	0	0
T215	0	119	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	295	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	3	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1	0	0
T29	0	2	0	0
T41	0	5	0	0
T64	0	12	0	0
T76	0	3	0	0
T215	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6069216	0	0
T1	21441	9359	0	0
T2	13902	13473	0	0
T3	16928	12088	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6070949	0	0
T1	21441	9375	0	0
T2	13902	13478	0	0
T3	16928	12088	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	376	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	5	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T41	0	6	0	0
T64	0	13	0	0
T76	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	337	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	3	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T41	0	5	0	0
T64	0	12	0	0
T76	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	295	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	3	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1	0	0
T29	0	2	0	0
T41	0	5	0	0
T64	0	12	0	0
T76	0	3	0	0
T215	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	295	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	3	0	0
T6	15299	2	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1	0	0
T29	0	2	0	0
T41	0	5	0	0
T64	0	12	0	0
T76	0	3	0	0
T215	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	11494	0	0
T1	21441	18	0	0
T2	13902	0	0	0
T3	16928	12	0	0
T6	15299	126	0	0
T12	0	65	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	77	0	0
T29	0	127	0	0
T41	0	51	0	0
T64	0	73	0	0
T76	0	9	0	0
T215	0	115	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	254	0	0
T1	21441	2	0	0
T2	13902	0	0	0
T3	16928	3	0	0
T6	15299	0	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1	0	0
T29	0	2	0	0
T31	0	1	0	0
T41	0	5	0	0
T64	0	12	0	0
T76	0	3	0	0
T228	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T6,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T7
0	1	Covered	T2,T7,T39
1	0	Covered	T2,T7,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T28
0	1	Covered	T6,T12,T28
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T12,T28
1	-	Covered	T6,T12,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T7
DetectSt	168	Covered	T2,T6,T7
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T12,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T7
DebounceSt->IdleSt	163	Covered	T77,T213,T214
DetectSt->IdleSt	186	Covered	T2,T7,T39
DetectSt->StableSt	191	Covered	T6,T12,T28
IdleSt->DebounceSt	148	Covered	T2,T6,T7
StableSt->IdleSt	206	Covered	T6,T12,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T6,T7
0	1	Covered	T2,T6,T7
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T7
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T7
IdleSt	0	-	-	-	-	-	-	Covered	T2,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T77,T213,T214
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T7
DetectSt	-	-	-	-	1	-	-	Covered	T2,T7,T39
DetectSt	-	-	-	-	0	1	-	Covered	T6,T12,T28
DetectSt	-	-	-	-	0	0	-	Covered	T2,T6,T7
StableSt	-	-	-	-	-	-	1	Covered	T6,T12,T28
StableSt	-	-	-	-	-	-	0	Covered	T6,T12,T28
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	2990	0	0
CntIncr_A	7138179	104133	0	0
CntNoWrap_A	7138179	6469061	0	0
DetectStDropOut_A	7138179	372	0	0
DetectedOut_A	7138179	85427	0	0
DetectedPulseOut_A	7138179	1009	0	0
DisabledIdleSt_A	7138179	6019707	0	0
DisabledNoDetection_A	7138179	6021888	0	0
EnterDebounceSt_A	7138179	1505	0	0
EnterDetectSt_A	7138179	1487	0	0
EnterStableSt_A	7138179	1009	0	0
PulseIsPulse_A	7138179	1009	0	0
StayInStableSt	7138179	84300	0	0
gen_high_event_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	891	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	2990	0	0
T2	13902	26	0	0
T3	16928	0	0	0
T6	15299	52	0	0
T7	0	66	0	0
T12	0	50	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	44	0	0
T38	0	46	0	0
T39	0	10	0	0
T42	0	50	0	0
T50	782	0	0	0
T69	0	18	0	0
T70	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	104133	0	0
T2	13902	669	0	0
T3	16928	0	0	0
T6	15299	1378	0	0
T7	0	1856	0	0
T12	0	1375	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	1914	0	0
T38	0	1035	0	0
T39	0	341	0	0
T42	0	1605	0	0
T50	782	0	0	0
T69	0	564	0	0
T70	0	1299	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6469061	0	0
T1	21441	14653	0	0
T2	13902	13447	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	372	0	0
T2	13902	4	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T7	0	27	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T39	0	5	0	0
T42	0	25	0	0
T50	782	0	0	0
T70	0	22	0	0
T77	0	1	0	0
T79	0	8	0	0
T88	0	22	0	0
T91	0	16	0	0
T94	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	85427	0	0
T6	15299	2387	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	1850	0	0
T24	20701	0	0	0
T28	0	1998	0	0
T38	0	1130	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	318	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	356	0	0
T215	0	3233	0	0
T216	0	755	0	0
T217	0	5373	0	0
T219	0	75	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1009	0	0
T6	15299	26	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	25	0	0
T24	20701	0	0	0
T28	0	22	0	0
T38	0	23	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	14	0	0
T215	0	25	0	0
T216	0	8	0	0
T217	0	24	0	0
T219	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6019707	0	0
T1	21441	14653	0	0
T2	13902	10704	0	0
T3	16928	16487	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6021888	0	0
T1	21441	14672	0	0
T2	13902	10708	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1505	0	0
T2	13902	13	0	0
T3	16928	0	0	0
T6	15299	26	0	0
T7	0	33	0	0
T12	0	25	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	22	0	0
T38	0	23	0	0
T39	0	5	0	0
T42	0	25	0	0
T50	782	0	0	0
T69	0	9	0	0
T70	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1487	0	0
T2	13902	13	0	0
T3	16928	0	0	0
T6	15299	26	0	0
T7	0	33	0	0
T12	0	25	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T28	0	22	0	0
T38	0	23	0	0
T39	0	5	0	0
T42	0	25	0	0
T50	782	0	0	0
T69	0	9	0	0
T70	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1009	0	0
T6	15299	26	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	25	0	0
T24	20701	0	0	0
T28	0	22	0	0
T38	0	23	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	14	0	0
T215	0	25	0	0
T216	0	8	0	0
T217	0	24	0	0
T219	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	1009	0	0
T6	15299	26	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	25	0	0
T24	20701	0	0	0
T28	0	22	0	0
T38	0	23	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	14	0	0
T215	0	25	0	0
T216	0	8	0	0
T217	0	24	0	0
T219	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	84300	0	0
T6	15299	2359	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	1822	0	0
T24	20701	0	0	0
T28	0	1976	0	0
T38	0	1107	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	313	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	342	0	0
T215	0	3201	0	0
T216	0	741	0	0
T217	0	5341	0	0
T219	0	70	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	891	0	0
T6	15299	24	0	0
T7	6881	0	0	0
T8	931	0	0	0
T12	0	22	0	0
T24	20701	0	0	0
T28	0	22	0	0
T38	0	23	0	0
T39	6073	0	0	0
T40	3761	0	0	0
T50	782	0	0	0
T51	425	0	0	0
T77	0	5	0	0
T107	423	0	0	0
T108	448	0	0	0
T141	0	14	0	0
T215	0	18	0	0
T216	0	2	0	0
T217	0	16	0	0
T219	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T76,T77
1	0	Covered	T77,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T12
0	1	Covered	T3,T6,T12
1	0	Covered	T78

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T12
1	-	Covered	T3,T6,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T6,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T30,T31,T228
DetectSt->IdleSt	186	Covered	T1,T76,T77
DetectSt->StableSt	191	Covered	T3,T6,T12
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T3,T6,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T77,T78
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T31,T228
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T1,T76,T77
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T12
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7138179	893	0	0
CntIncr_A	7138179	49383	0	0
CntNoWrap_A	7138179	6471158	0	0
DetectStDropOut_A	7138179	55	0	0
DetectedOut_A	7138179	15754	0	0
DetectedPulseOut_A	7138179	364	0	0
DisabledIdleSt_A	7138179	6047865	0	0
DisabledNoDetection_A	7138179	6049579	0	0
EnterDebounceSt_A	7138179	473	0	0
EnterDetectSt_A	7138179	422	0	0
EnterStableSt_A	7138179	364	0	0
PulseIsPulse_A	7138179	364	0	0
StayInStableSt	7138179	15339	0	0
gen_high_level_sva.HighLevelEvent_A	7138179	6474440	0	0
gen_not_sticky_sva.StableStDropOut_A	7138179	309	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	893	0	0
T1	21441	14	0	0
T2	13902	0	0	0
T3	16928	4	0	0
T6	15299	4	0	0
T12	0	6	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	9	0	0
T31	0	19	0	0
T64	0	10	0	0
T76	0	2	0	0
T185	0	18	0	0
T215	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	49383	0	0
T1	21441	1135	0	0
T2	13902	0	0	0
T3	16928	246	0	0
T6	15299	144	0	0
T12	0	171	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	449	0	0
T31	0	1602	0	0
T64	0	470	0	0
T76	0	149	0	0
T185	0	1341	0	0
T215	0	490	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6471158	0	0
T1	21441	14639	0	0
T2	13902	13473	0	0
T3	16928	16483	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	55	0	0
T1	21441	7	0	0
T2	13902	0	0	0
T3	16928	0	0	0
T6	15299	0	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T76	0	1	0	0
T77	0	1	0	0
T81	0	8	0	0
T100	0	6	0	0
T223	0	1	0	0
T229	0	3	0	0
T230	0	1	0	0
T231	0	7	0	0
T232	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	15754	0	0
T3	16928	70	0	0
T6	15299	121	0	0
T7	6881	0	0	0
T12	0	176	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	107	0	0
T31	0	140	0	0
T50	782	0	0	0
T64	0	406	0	0
T185	0	83	0	0
T215	0	360	0	0
T216	0	107	0	0
T228	0	137	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	364	0	0
T3	16928	2	0	0
T6	15299	2	0	0
T7	6881	0	0	0
T12	0	3	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	4	0	0
T31	0	9	0	0
T50	782	0	0	0
T64	0	5	0	0
T185	0	9	0	0
T215	0	7	0	0
T216	0	2	0	0
T228	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6047865	0	0
T1	21441	9359	0	0
T2	13902	13473	0	0
T3	16928	12088	0	0
T4	202500	202099	0	0
T5	797	396	0	0
T13	496	95	0	0
T14	527	126	0	0
T15	492	91	0	0
T16	7883	7482	0	0
T17	504	103	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6049579	0	0
T1	21441	9375	0	0
T2	13902	13478	0	0
T3	16928	12088	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	473	0	0
T1	21441	7	0	0
T2	13902	0	0	0
T3	16928	2	0	0
T6	15299	2	0	0
T12	0	3	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	5	0	0
T31	0	10	0	0
T64	0	5	0	0
T76	0	1	0	0
T185	0	9	0	0
T215	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	422	0	0
T1	21441	7	0	0
T2	13902	0	0	0
T3	16928	2	0	0
T6	15299	2	0	0
T12	0	3	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	4	0	0
T31	0	9	0	0
T64	0	5	0	0
T76	0	1	0	0
T185	0	9	0	0
T215	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	364	0	0
T3	16928	2	0	0
T6	15299	2	0	0
T7	6881	0	0	0
T12	0	3	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	4	0	0
T31	0	9	0	0
T50	782	0	0	0
T64	0	5	0	0
T185	0	9	0	0
T215	0	7	0	0
T216	0	2	0	0
T228	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	364	0	0
T3	16928	2	0	0
T6	15299	2	0	0
T7	6881	0	0	0
T12	0	3	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	4	0	0
T31	0	9	0	0
T50	782	0	0	0
T64	0	5	0	0
T185	0	9	0	0
T215	0	7	0	0
T216	0	2	0	0
T228	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	15339	0	0
T3	16928	68	0	0
T6	15299	118	0	0
T7	6881	0	0	0
T12	0	171	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	103	0	0
T31	0	131	0	0
T50	782	0	0	0
T64	0	401	0	0
T185	0	74	0	0
T215	0	346	0	0
T216	0	103	0	0
T228	0	127	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	6474440	0	0
T1	21441	14672	0	0
T2	13902	13478	0	0
T3	16928	16493	0	0
T4	202500	202100	0	0
T5	797	397	0	0
T13	496	96	0	0
T14	527	127	0	0
T15	492	92	0	0
T16	7883	7483	0	0
T17	504	104	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7138179	309	0	0
T3	16928	2	0	0
T6	15299	1	0	0
T7	6881	0	0	0
T12	0	1	0	0
T13	496	0	0	0
T14	527	0	0	0
T15	492	0	0	0
T16	7883	0	0	0
T17	504	0	0	0
T18	503	0	0	0
T30	0	4	0	0
T31	0	9	0	0
T50	782	0	0	0
T64	0	5	0	0
T185	0	9	0	0
T217	0	2	0	0
T228	0	10	0	0
T233	0	9	0	0